Commit | Line | Data |
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7637af2e SW |
1 | NVIDIA Tegra audio complex, with MAX98090 CODEC |
2 | ||
3 | Required properties: | |
4 | - compatible : "nvidia,tegra-audio-max98090" | |
5 | - clocks : Must contain an entry for each entry in clock-names. | |
6 | See ../clocks/clock-bindings.txt for details. | |
7 | - clock-names : Must include the following entries: | |
8 | - pll_a | |
9 | - pll_a_out0 | |
10 | - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) | |
11 | - nvidia,model : The user-visible name of this sound complex. | |
12 | - nvidia,audio-routing : A list of the connections between audio components. | |
13 | Each entry is a pair of strings, the first being the connection's sink, | |
14 | the second being the connection's source. Valid names for sources and | |
15 | sinks are the MAX98090's pins (as documented in its binding), and the jacks | |
16 | on the board: | |
17 | ||
18 | * Headphones | |
19 | * Speakers | |
20 | * Mic Jack | |
3a4562f7 | 21 | * Int Mic |
7637af2e SW |
22 | |
23 | - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's | |
24 | connected to the CODEC. | |
25 | - nvidia,audio-codec : The phandle of the MAX98090 audio codec. | |
26 | ||
27 | Optional properties: | |
28 | - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in | |
9766a1cf | 29 | - nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in |
7637af2e SW |
30 | |
31 | Example: | |
32 | ||
33 | sound { | |
34 | compatible = "nvidia,tegra-audio-max98090-venice2", | |
35 | "nvidia,tegra-audio-max98090"; | |
36 | nvidia,model = "NVIDIA Tegra Venice2"; | |
37 | ||
38 | nvidia,audio-routing = | |
39 | "Headphones", "HPR", | |
40 | "Headphones", "HPL", | |
41 | "Speakers", "SPKR", | |
42 | "Speakers", "SPKL", | |
43 | "Mic Jack", "MICBIAS", | |
44 | "IN34", "Mic Jack"; | |
45 | ||
46 | nvidia,i2s-controller = <&tegra_i2s1>; | |
47 | nvidia,audio-codec = <&acodec>; | |
48 | ||
49 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
50 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
51 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
52 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
53 | }; |