Commit | Line | Data |
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3c320f3f DR |
1 | NVIDIA Tegra30 HDA controller |
2 | ||
3 | Required properties: | |
193c9d23 PW |
4 | - compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise, |
5 | must contain '"nvidia,<chip>-hda", "nvidia,tegra30-hda"', where <chip> is | |
6 | tegra114, tegra124, or tegra132. | |
3c320f3f DR |
7 | - reg : Should contain the HDA registers location and length. |
8 | - interrupts : The interrupt from the HDA controller. | |
9 | - clocks : Must contain an entry for each required entry in clock-names. | |
10 | See ../clocks/clock-bindings.txt for details. | |
5cf4af3b | 11 | - clock-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x |
3c320f3f DR |
12 | - resets : Must contain an entry for each entry in reset-names. |
13 | See ../reset/reset.txt for details. | |
5cf4af3b | 14 | - reset-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x |
3c320f3f DR |
15 | |
16 | Example: | |
17 | ||
f43521e9 | 18 | hda@70030000 { |
3c320f3f DR |
19 | compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; |
20 | reg = <0x0 0x70030000 0x0 0x10000>; | |
21 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
22 | clocks = <&tegra_car TEGRA124_CLK_HDA>, | |
23 | <&tegra_car TEGRA124_CLK_HDA2HDMI>, | |
24 | <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; | |
2c6db77c | 25 | clock-names = "hda", "hda2hdmi", "hda2codec_2x"; |
3c320f3f | 26 | resets = <&tegra_car 125>, /* hda */ |
42a8679c MZ |
27 | <&tegra_car 128>, /* hda2hdmi */ |
28 | <&tegra_car 111>; /* hda2codec_2x */ | |
2c6db77c | 29 | reset-names = "hda", "hda2hdmi", "hda2codec_2x"; |
3c320f3f | 30 | }; |