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4fb0384f SW |
1 | NVIDIA Tegra30 I2S controller |
2 | ||
3 | Required properties: | |
193c9d23 PW |
4 | - compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124, |
5 | must contain "nvidia,tegra124-i2s". Otherwise, must contain | |
6 | "nvidia,<chip>-i2s" plus at least one of the above, where <chip> is | |
7 | tegra114 or tegra132. | |
4fb0384f | 8 | - reg : Should contain I2S registers location and length |
d8f64797 SW |
9 | - clocks : Must contain one entry, for the module clock. |
10 | See ../clocks/clock-bindings.txt for details. | |
07999587 SW |
11 | - resets : Must contain an entry for each entry in reset-names. |
12 | See ../reset/reset.txt for details. | |
13 | - reset-names : Must include the following entries: | |
14 | - i2s | |
4fb0384f SW |
15 | - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback) |
16 | first, tx (capture) second. See nvidia,tegra30-ahub.txt for values. | |
17 | ||
18 | Example: | |
19 | ||
d8f64797 | 20 | i2s@70080300 { |
4fb0384f SW |
21 | compatible = "nvidia,tegra30-i2s"; |
22 | reg = <0x70080300 0x100>; | |
23 | nvidia,ahub-cif-ids = <4 4>; | |
d8f64797 | 24 | clocks = <&tegra_car 11>; |
07999587 SW |
25 | resets = <&tegra_car 11>; |
26 | reset-names = "i2s"; | |
4fb0384f | 27 | }; |