Commit | Line | Data |
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11dd5864 PU |
1 | * Texas Instruments OMAP2+ McBSP module |
2 | ||
3 | Required properties: | |
4 | - compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420 | |
5 | "ti,omap2430-mcbsp" for McBSP on OMAP2430 | |
6 | "ti,omap3-mcbsp" for McBSP on OMAP3 | |
7 | "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC | |
8 | - reg: Register location and size, for OMAP4+ as an array: | |
9 | <MPU access base address, size>, | |
10 | <L3 interconnect address, size>; | |
b8101048 | 11 | - reg-names: Array of strings associated with the address space |
11dd5864 PU |
12 | - interrupts: Interrupt numbers for the McBSP port, as an array in case the |
13 | McBSP IP have more interrupt lines: | |
14 | <OCP compliant irq>, | |
15 | <TX irq>, | |
16 | <RX irq>; | |
b8101048 | 17 | - interrupt-names: Array of strings associated with the interrupt numbers |
11dd5864 PU |
18 | - interrupt-parent: The parent interrupt controller |
19 | - ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC) | |
20 | - ti,hwmods: Name of the hwmod associated to the McBSP port | |
21 | ||
11dd5864 PU |
22 | Example: |
23 | ||
24 | mcbsp2: mcbsp@49022000 { | |
25 | compatible = "ti,omap3-mcbsp"; | |
b8101048 PU |
26 | reg = <0x49022000 0xff>, |
27 | <0x49028000 0xff>; | |
28 | reg-names = "mpu", "sidetone"; | |
29 | interrupts = <0 17 0x4>, /* OCP compliant interrupt */ | |
30 | <0 62 0x4>, /* TX interrupt */ | |
31 | <0 63 0x4>, /* RX interrupt */ | |
32 | <0 4 0x4>; /* Sidetone */ | |
33 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
11dd5864 PU |
34 | interrupt-parent = <&intc>; |
35 | ti,buffer-size = <1280>; | |
36 | ti,hwmods = "mcbsp2"; | |
11dd5864 | 37 | }; |