Commit | Line | Data |
---|---|---|
11dd5864 PU |
1 | * Texas Instruments OMAP2+ McBSP module |
2 | ||
3 | Required properties: | |
4 | - compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420 | |
5 | "ti,omap2430-mcbsp" for McBSP on OMAP2430 | |
6 | "ti,omap3-mcbsp" for McBSP on OMAP3 | |
7 | "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC | |
8 | - reg: Register location and size, for OMAP4+ as an array: | |
9 | <MPU access base address, size>, | |
10 | <L3 interconnect address, size>; | |
11 | - interrupts: Interrupt numbers for the McBSP port, as an array in case the | |
12 | McBSP IP have more interrupt lines: | |
13 | <OCP compliant irq>, | |
14 | <TX irq>, | |
15 | <RX irq>; | |
16 | - interrupt-parent: The parent interrupt controller | |
17 | - ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC) | |
18 | - ti,hwmods: Name of the hwmod associated to the McBSP port | |
19 | ||
20 | Sidetone support for OMAP3 McBSP2 and 3 ports: | |
21 | - sidetone { }: Within this section the following parameters are required: | |
22 | - reg: Register location and size for the ST block | |
23 | - interrupts: The interrupt number for the ST block | |
24 | - interrupt-parent: The parent interrupt controller for the ST block | |
25 | ||
26 | Example: | |
27 | ||
28 | mcbsp2: mcbsp@49022000 { | |
29 | compatible = "ti,omap3-mcbsp"; | |
30 | #address-cells = <1>; | |
31 | #size-cells = <1>; | |
32 | reg = <0x49022000 0xff>; | |
33 | interrupts = <0 17 0x4>, /* OCP compliant interrup */ | |
34 | <0 62 0x4>, /* TX interrup */ | |
35 | <0 63 0x4>; /* RX interrup */ | |
36 | interrupt-parent = <&intc>; | |
37 | ti,buffer-size = <1280>; | |
38 | ti,hwmods = "mcbsp2"; | |
39 | ||
40 | sidetone { | |
41 | reg = <0x49028000 0xff>; | |
42 | interrupts = <0 4 0x4>; | |
43 | interrupt-parent = <&intc>; | |
44 | }; | |
45 | }; |