Commit | Line | Data |
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cf9c86ef BH |
1 | Renesas MSIOF spi controller |
2 | ||
3 | Required properties: | |
beb74bb0 GU |
4 | - compatible : "renesas,msiof-<soctype>" for SoCs, |
5 | "renesas,sh-msiof" for SuperH, or | |
32d3b2d1 | 6 | "renesas,sh-mobile-msiof" for SH Mobile series. |
beb74bb0 | 7 | Examples with soctypes are: |
beb74bb0 | 8 | "renesas,msiof-r8a7790" (R-Car H2) |
e221cc99 GU |
9 | "renesas,msiof-r8a7791" (R-Car M2-W) |
10 | "renesas,msiof-r8a7792" (R-Car V2H) | |
11 | "renesas,msiof-r8a7793" (R-Car M2-N) | |
12 | "renesas,msiof-r8a7794" (R-Car E2) | |
ec7f9eb4 | 13 | "renesas,msiof-sh73a0" (SH-Mobile AG5) |
a6be4de6 GU |
14 | - reg : A list of offsets and lengths of the register sets for |
15 | the device. | |
16 | If only one register set is present, it is to be used | |
17 | by both the CPU and the DMA engine. | |
18 | If two register sets are present, the first is to be | |
19 | used by the CPU, and the second is to be used by the | |
20 | DMA engine. | |
32d3b2d1 GU |
21 | - interrupt-parent : The phandle for the interrupt controller that |
22 | services interrupts for this device | |
23 | - interrupts : Interrupt specifier | |
24 | - #address-cells : Must be <1> | |
25 | - #size-cells : Must be <0> | |
cf9c86ef BH |
26 | |
27 | Optional properties: | |
32d3b2d1 GU |
28 | - clocks : Must contain a reference to the functional clock. |
29 | - num-cs : Total number of chip-selects (default is 1) | |
a6be4de6 GU |
30 | - dmas : Must contain a list of two references to DMA |
31 | specifiers, one for transmission, and one for | |
32 | reception. | |
33 | - dma-names : Must contain a list of two DMA names, "tx" and "rx". | |
3110628d YS |
34 | - renesas,dtdl : delay sync signal (setup) in transmit mode. |
35 | Must contain one of the following values: | |
36 | 0 (no bit delay) | |
37 | 50 (0.5-clock-cycle delay) | |
38 | 100 (1-clock-cycle delay) | |
39 | 150 (1.5-clock-cycle delay) | |
40 | 200 (2-clock-cycle delay) | |
41 | ||
42 | - renesas,syncdl : delay sync signal (hold) in transmit mode. | |
43 | Must contain one of the following values: | |
44 | 0 (no bit delay) | |
45 | 50 (0.5-clock-cycle delay) | |
46 | 100 (1-clock-cycle delay) | |
47 | 150 (1.5-clock-cycle delay) | |
48 | 200 (2-clock-cycle delay) | |
49 | 300 (3-clock-cycle delay) | |
beb74bb0 GU |
50 | |
51 | Optional properties, deprecated for soctype-specific bindings: | |
32d3b2d1 GU |
52 | - renesas,tx-fifo-size : Overrides the default tx fifo size given in words |
53 | (default is 64) | |
54 | - renesas,rx-fifo-size : Overrides the default rx fifo size given in words | |
eb8d0ac4 | 55 | (default is 64) |
32d3b2d1 GU |
56 | |
57 | Pinctrl properties might be needed, too. See | |
58 | Documentation/devicetree/bindings/pinctrl/renesas,*. | |
beb74bb0 GU |
59 | |
60 | Example: | |
61 | ||
62 | msiof0: spi@e6e20000 { | |
63 | compatible = "renesas,msiof-r8a7791"; | |
cb6d08a2 | 64 | reg = <0 0xe6e20000 0 0x0064>; |
beb74bb0 GU |
65 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
66 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | |
a6be4de6 GU |
67 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
68 | dma-names = "tx", "rx"; | |
beb74bb0 GU |
69 | #address-cells = <1>; |
70 | #size-cells = <0>; | |
71 | status = "disabled"; | |
72 | }; |