Commit | Line | Data |
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20e5ea19 BS |
1 | Synopsys DesignWare SPI master |
2 | ||
3 | Required properties: | |
4 | - compatible: should be "snps,designware-spi" | |
5 | - #address-cells: see spi-bus.txt | |
6 | - #size-cells: see spi-bus.txt | |
7 | - reg: address and length of the spi master registers | |
8 | - interrupts: should contain one interrupt | |
9 | - clocks: spi clock phandle | |
10 | - num-cs: see spi-bus.txt | |
11 | ||
12 | Optional properties: | |
13 | - cs-gpios: see spi-bus.txt | |
14 | ||
15 | Example: | |
16 | ||
17 | spi: spi@4020a000 { | |
18 | compatible = "snps,designware-spi"; | |
19 | interrupts = <11 1>; | |
20 | reg = <0x4020a000 0x1000>; | |
21 | clocks = <&pclk>; | |
22 | num-cs = <2>; | |
23 | cs-gpios = <&banka 0 0>; | |
24 | }; |