Commit | Line | Data |
---|---|---|
0d850e7c LL |
1 | Binding for MTK SPI controller |
2 | ||
3 | Required properties: | |
4 | - compatible: should be one of the following. | |
5c5e09f6 | 5 | - mediatek,mt2701-spi: for mt2701 platforms |
0d850e7c | 6 | - mediatek,mt6589-spi: for mt6589 platforms |
5c5e09f6 LL |
7 | - mediatek,mt8135-spi: for mt8135 platforms |
8 | - mediatek,mt8173-spi: for mt8173 platforms | |
0d850e7c LL |
9 | |
10 | - #address-cells: should be 1. | |
11 | ||
12 | - #size-cells: should be 0. | |
13 | ||
14 | - reg: Address and length of the register set for the device | |
15 | ||
16 | - interrupts: Should contain spi interrupt | |
17 | ||
18 | - clocks: phandles to input clocks. | |
3d4fe182 | 19 | The first should be one of the following. It's PLL. |
0d850e7c LL |
20 | - <&clk26m>: specify parent clock 26MHZ. |
21 | - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ. | |
22 | It's the default one. | |
23 | - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ. | |
24 | - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ. | |
25 | - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ. | |
3d4fe182 LL |
26 | The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux. |
27 | The third is <&pericfg CLK_PERI_SPI0>. It's clock gate. | |
0d850e7c | 28 | |
3d4fe182 LL |
29 | - clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the |
30 | muxes clock, and "spi-clk" for the clock gate. | |
0d850e7c LL |
31 | |
32 | Optional properties: | |
6e6a9cd4 | 33 | -cs-gpios: see spi-bus.txt. |
eca3a1ee | 34 | |
0d850e7c | 35 | - mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi |
fbdb5d78 | 36 | controller used. This is an array, the element value should be 0~3, |
eca3a1ee | 37 | only required for MT8173. |
0d850e7c LL |
38 | 0: specify GPIO69,70,71,72 for spi pins. |
39 | 1: specify GPIO102,103,104,105 for spi pins. | |
40 | 2: specify GPIO128,129,130,131 for spi pins. | |
41 | 3: specify GPIO5,6,7,8 for spi pins. | |
42 | ||
43 | Example: | |
44 | ||
45 | - SoC Specific Portion: | |
46 | spi: spi@1100a000 { | |
47 | compatible = "mediatek,mt8173-spi"; | |
48 | #address-cells = <1>; | |
49 | #size-cells = <0>; | |
50 | reg = <0 0x1100a000 0 0x1000>; | |
51 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; | |
3d4fe182 LL |
52 | clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, |
53 | <&topckgen CLK_TOP_SPI_SEL>, | |
54 | <&pericfg CLK_PERI_SPI0>; | |
55 | clock-names = "parent-clk", "sel-clk", "spi-clk"; | |
eca3a1ee LL |
56 | cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>; |
57 | mediatek,pad-select = <1>, <0>; | |
0d850e7c LL |
58 | status = "disabled"; |
59 | }; |