Commit | Line | Data |
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2b908075 TA |
1 | * Samsung SPI Controller |
2 | ||
3 | The Samsung SPI controller is used to interface with various devices such as flash | |
4 | and display controllers using the SPI communication interface. | |
5 | ||
6 | Required SoC Specific Properties: | |
7 | ||
8 | - compatible: should be one of the following. | |
9 | - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms | |
10 | - samsung,s3c6410-spi: for s3c6410 platforms | |
2b908075 | 11 | - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms |
bf77cba9 | 12 | - samsung,exynos7-spi: for exynos7 platforms |
2b908075 TA |
13 | |
14 | - reg: physical base address of the controller and length of memory mapped | |
15 | region. | |
16 | ||
17 | - interrupts: The interrupt number to the cpu. The interrupt specifier format | |
18 | depends on the interrupt controller. | |
19 | ||
09a5ae80 SK |
20 | - dmas : Two or more DMA channel specifiers following the convention outlined |
21 | in bindings/dma/dma.txt | |
5d74c8a0 | 22 | |
09a5ae80 SK |
23 | - dma-names: Names for the dma channels. There must be at least one channel |
24 | named "tx" for transmit and named "rx" for receive. | |
2b908075 TA |
25 | |
26 | Required Board Specific Properties: | |
27 | ||
28 | - #address-cells: should be 1. | |
29 | - #size-cells: should be 0. | |
2b908075 TA |
30 | |
31 | Optional Board Specific Properties: | |
32 | ||
33 | - samsung,spi-src-clk: If the spi controller includes a internal clock mux to | |
34 | select the clock source for the spi bus clock, this property can be used to | |
35 | indicate the clock to be used for driving the spi bus clock. If not specified, | |
36 | the clock number 0 is used as default. | |
37 | ||
38 | - num-cs: Specifies the number of chip select lines supported. If | |
39 | not specified, the default number of chip select lines is set to 1. | |
40 | ||
797bf3a2 NKC |
41 | - cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt) |
42 | ||
2b908075 TA |
43 | SPI Controller specific data in SPI slave nodes: |
44 | ||
45 | - The spi slave nodes should provide the following information which is required | |
46 | by the spi controller. | |
47 | ||
2b908075 TA |
48 | - samsung,spi-feedback-delay: The sampling phase shift to be applied on the |
49 | miso line (to account for any lag in the miso line). The following are the | |
50 | valid values. | |
51 | ||
52 | - 0: No phase shift. | |
53 | - 1: 90 degree phase shift sampling. | |
54 | - 2: 180 degree phase shift sampling. | |
55 | - 3: 270 degree phase shift sampling. | |
56 | ||
57 | Aliases: | |
58 | ||
59 | - All the SPI controller nodes should be represented in the aliases node using | |
60 | the following format 'spi{n}' where n is a unique number for the alias. | |
61 | ||
62 | ||
63 | Example: | |
64 | ||
65 | - SoC Specific Portion: | |
66 | ||
67 | spi_0: spi@12d20000 { | |
68 | compatible = "samsung,exynos4210-spi"; | |
69 | reg = <0x12d20000 0x100>; | |
70 | interrupts = <0 66 0>; | |
09a5ae80 SK |
71 | dmas = <&pdma0 5 |
72 | &pdma0 4>; | |
73 | dma-names = "tx", "rx"; | |
74 | #address-cells = <1>; | |
75 | #size-cells = <0>; | |
2b908075 TA |
76 | }; |
77 | ||
78 | - Board Specific Portion: | |
79 | ||
80 | spi_0: spi@12d20000 { | |
81 | #address-cells = <1>; | |
82 | #size-cells = <0>; | |
00ab5392 TA |
83 | pinctrl-names = "default"; |
84 | pinctrl-0 = <&spi0_bus>; | |
797bf3a2 | 85 | cs-gpios = <&gpa2 5 0>; |
2b908075 TA |
86 | |
87 | w25q80bw@0 { | |
88 | #address-cells = <1>; | |
89 | #size-cells = <1>; | |
90 | compatible = "w25x80"; | |
91 | reg = <0>; | |
92 | spi-max-frequency = <10000>; | |
93 | ||
94 | controller-data { | |
2b908075 TA |
95 | samsung,spi-feedback-delay = <0>; |
96 | }; | |
97 | ||
98 | partition@0 { | |
99 | label = "U-Boot"; | |
100 | reg = <0x0 0x40000>; | |
101 | read-only; | |
102 | }; | |
103 | ||
104 | partition@40000 { | |
105 | label = "Kernel"; | |
106 | reg = <0x40000 0xc0000>; | |
107 | }; | |
108 | }; | |
109 | }; |