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36ba5d52 TA |
1 | Samsung's Multi Core Timer (MCT) |
2 | ||
3 | The Samsung's Multi Core Timer (MCT) module includes two main blocks, the | |
4 | global timer and CPU local timers. The global timer is a 64-bit free running | |
5 | up-counter and can generate 4 interrupts when the counter reaches one of the | |
6 | four preset counter values. The CPU local timers are 32-bit free running | |
7 | down-counters and generate an interrupt when the counter expires. There is | |
8 | one CPU local timer instantiated in MCT for every CPU in the system. | |
9 | ||
10 | Required properties: | |
11 | ||
12 | - compatible: should be "samsung,exynos4210-mct". | |
13 | (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct. | |
14 | (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct. | |
15 | ||
16 | - reg: base address of the mct controller and length of the address space | |
17 | it occupies. | |
18 | ||
19 | - interrupts: the list of interrupts generated by the controller. The following | |
20 | should be the order of the interrupts specified. The local timer interrupts | |
21 | should be specified after the four global timer interrupts have been | |
22 | specified. | |
23 | ||
24 | 0: Global Timer Interrupt 0 | |
25 | 1: Global Timer Interrupt 1 | |
26 | 2: Global Timer Interrupt 2 | |
27 | 3: Global Timer Interrupt 3 | |
28 | 4: Local Timer Interrupt 0 | |
29 | 5: Local Timer Interrupt 1 | |
30 | 6: .. | |
31 | 7: .. | |
32 | i: Local Timer Interrupt n | |
33 | ||
59832556 TF |
34 | For MCT block that uses a per-processor interrupt for local timers, such |
35 | as ones compatible with "samsung,exynos4412-mct", only one local timer | |
36 | interrupt might be specified, meaning that all local timers use the same | |
37 | per processor interrupt. | |
38 | ||
39 | Example 1: In this example, the IP contains two local timers, using separate | |
40 | interrupts, so two local timer interrupts have been specified, | |
41 | in addition to four global timer interrupts. | |
36ba5d52 TA |
42 | |
43 | mct@10050000 { | |
44 | compatible = "samsung,exynos4210-mct"; | |
45 | reg = <0x10050000 0x800>; | |
59832556 | 46 | interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, |
36ba5d52 TA |
47 | <0 42 0>, <0 48 0>; |
48 | }; | |
49 | ||
59832556 TF |
50 | Example 2: In this example, the timer interrupts are connected to two separate |
51 | interrupt controllers. Hence, an interrupt-map is created to map | |
52 | the interrupts to the respective interrupt controllers. | |
36ba5d52 TA |
53 | |
54 | mct@101C0000 { | |
55 | compatible = "samsung,exynos4210-mct"; | |
56 | reg = <0x101C0000 0x800>; | |
36ba5d52 | 57 | interrupt-parent = <&mct_map>; |
59832556 | 58 | interrupts = <0>, <1>, <2>, <3>, <4>, <5>; |
36ba5d52 TA |
59 | |
60 | mct_map: mct-map { | |
59832556 | 61 | #interrupt-cells = <1>; |
36ba5d52 TA |
62 | #address-cells = <0>; |
63 | #size-cells = <0>; | |
59832556 TF |
64 | interrupt-map = <0 &gic 0 57 0>, |
65 | <1 &gic 0 69 0>, | |
66 | <2 &combiner 12 6>, | |
67 | <3 &combiner 12 7>, | |
68 | <4 &gic 0 42 0>, | |
69 | <5 &gic 0 48 0>; | |
36ba5d52 TA |
70 | }; |
71 | }; | |
59832556 TF |
72 | |
73 | Example 3: In this example, the IP contains four local timers, but using | |
74 | a per-processor interrupt to handle them. Either all the local | |
75 | timer interrupts can be specified, with the same interrupt specifier | |
76 | value or just the first one. | |
77 | ||
78 | mct@10050000 { | |
79 | compatible = "samsung,exynos4412-mct"; | |
80 | reg = <0x10050000 0x800>; | |
81 | ||
82 | /* Both ways are possible in this case. Either: */ | |
83 | interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, | |
84 | <0 42 0>; | |
85 | /* or: */ | |
86 | interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>, | |
87 | <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>; | |
88 | }; |