Merge tag 'firewire-update2' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee139...
[deliverable/linux.git] / Documentation / devicetree / bindings / usb / mt8173-xhci.txt
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1MT8173 xHCI
2
3The device node for Mediatek SOC USB3.0 host controller
4
5Required properties:
6 - compatible : should contain "mediatek,mt8173-xhci"
7 - reg : specifies physical base address and size of the registers,
8 the first one for MAC, the second for IPPC
9 - interrupts : interrupt used by the controller
10 - power-domains : a phandle to USB power domain node to control USB's
11 mtcmos
12 - vusb33-supply : regulator of USB avdd3.3v
13
14 - clocks : a list of phandle + clock-specifier pairs, one for each
15 entry in clock-names
16 - clock-names : must contain
17 "sys_ck": for clock of xHCI MAC
18 "wakeup_deb_p0": for USB wakeup debounce clock of port0
19 "wakeup_deb_p1": for USB wakeup debounce clock of port1
20
21 - phys : a list of phandle + phy specifier pairs
22
23Optional properties:
24 - mediatek,wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup
25 mode;
26 - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup
27 control register, it depends on "mediatek,wakeup-src".
28 - vbus-supply : reference to the VBUS regulator;
29 - usb3-lpm-capable : supports USB3.0 LPM
30
31Example:
32usb30: usb@11270000 {
33 compatible = "mediatek,mt8173-xhci";
34 reg = <0 0x11270000 0 0x1000>,
35 <0 0x11280700 0 0x0100>;
36 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
37 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
38 clocks = <&topckgen CLK_TOP_USB30_SEL>,
39 <&pericfg CLK_PERI_USB0>,
40 <&pericfg CLK_PERI_USB1>;
41 clock-names = "sys_ck",
42 "wakeup_deb_p0",
43 "wakeup_deb_p1";
44 phys = <&phy_port0 PHY_TYPE_USB3>,
45 <&phy_port1 PHY_TYPE_USB2>;
46 vusb33-supply = <&mt6397_vusb_reg>;
47 vbus-supply = <&usb_p1_vbus>;
48 usb3-lpm-capable;
49 mediatek,syscon-wakeup = <&pericfg>;
50 mediatek,wakeup-src = <1>;
51};
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