[deliverable/linux.git] / Documentation / devicetree / bindings / video / exynos_dp.txt

The Exynos display port interface should be configured based on
the type of panel connected to it.

We use two nodes:
	-dp-controller node
	-dptx-phy node(defined inside dp-controller node)

For the DP-PHY initialization, we use the dptx-phy node.
Required properties for dptx-phy: deprecated, use phys and phy-names
	-reg: deprecated
		Base address of DP PHY register.
	-samsung,enable-mask: deprecated
		The bit-mask used to enable/disable DP PHY.

For the Panel initialization, we read data from dp-controller node.
Required properties for dp-controller:
	-compatible:
		should be "samsung,exynos5-dp".
	-reg:
		physical base address of the controller and length
		of memory mapped region.
	-interrupts:
		interrupt combiner values.
	-clocks:
		from common clock binding: handle to dp clock.
	-clock-names:
		from common clock binding: Shall be "dp".
	-interrupt-parent:
		phandle to Interrupt combiner node.
	-phys:
		from general PHY binding: the phandle for the PHY device.
	-phy-names:
		from general PHY binding: Should be "dp".
	-samsung,color-space:
		input video data format.
			COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
	-samsung,dynamic-range:
		dynamic range for input video data.
			VESA = 0, CEA = 1
	-samsung,ycbcr-coeff:
		YCbCr co-efficients for input video.
			COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
	-samsung,color-depth:
		number of bits per colour component.
			COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
	-samsung,link-rate:
		link rate supported by the panel.
			LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
	-samsung,lane-count:
		number of lanes supported by the panel.
			LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4

Optional properties for dp-controller:
	-interlaced:
		interlace scan mode.
			Progressive if defined, Interlaced if not defined
	-vsync-active-high:
		VSYNC polarity configuration.
			High if defined, Low if not defined
	-hsync-active-high:
		HSYNC polarity configuration.
			High if defined, Low if not defined

Example:

SOC specific portion:
	dp-controller {
		compatible = "samsung,exynos5-dp";
		reg = <0x145b0000 0x10000>;
		interrupts = <10 3>;
		interrupt-parent = <&combiner>;
		clocks = <&clock 342>;
		clock-names = "dp";

		phys = <&dp_phy>;
		phy-names = "dp";
	};

Board Specific portion:
	dp-controller {
		samsung,color-space = <0>;
		samsung,dynamic-range = <0>;
		samsung,ycbcr-coeff = <0>;
		samsung,color-depth = <1>;
		samsung,link-rate = <0x0a>;
		samsung,lane-count = <4>;
	};
Commit	Line	Data
825e90d0 AK	1	The Exynos display port interface should be configured based on
	2	the type of panel connected to it.
	3
	4	We use two nodes:
	5	-dp-controller node
	6	-dptx-phy node(defined inside dp-controller node)
	7
	8	For the DP-PHY initialization, we use the dptx-phy node.
8114fabc JH	9	Required properties for dptx-phy: deprecated, use phys and phy-names
8114fabc JH	10	-reg: deprecated
825e90d0	11	Base address of DP PHY register.
8114fabc	12	-samsung,enable-mask: deprecated
825e90d0 AK	13	The bit-mask used to enable/disable DP PHY.
	14
	15	For the Panel initialization, we read data from dp-controller node.
	16	Required properties for dp-controller:
	17	-compatible:
	18	should be "samsung,exynos5-dp".
	19	-reg:
	20	physical base address of the controller and length
	21	of memory mapped region.
	22	-interrupts:
	23	interrupt combiner values.
60e69858 JH	24	-clocks:
	25	from common clock binding: handle to dp clock.
	26	-clock-names:
	27	from common clock binding: Shall be "dp".
825e90d0 AK	28	-interrupt-parent:
825e90d0 AK	29	phandle to Interrupt combiner node.
8114fabc JH	30	-phys:
	31	from general PHY binding: the phandle for the PHY device.
	32	-phy-names:
	33	from general PHY binding: Should be "dp".
825e90d0 AK	34	-samsung,color-space:
	35	input video data format.
	36	COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
	37	-samsung,dynamic-range:
	38	dynamic range for input video data.
	39	VESA = 0, CEA = 1
	40	-samsung,ycbcr-coeff:
	41	YCbCr co-efficients for input video.
	42	COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
	43	-samsung,color-depth:
	44	number of bits per colour component.
	45	COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
	46	-samsung,link-rate:
	47	link rate supported by the panel.
	48	LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
	49	-samsung,lane-count:
	50	number of lanes supported by the panel.
	51	LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
	52
	53	Optional properties for dp-controller:
	54	-interlaced:
	55	interlace scan mode.
	56	Progressive if defined, Interlaced if not defined
	57	-vsync-active-high:
	58	VSYNC polarity configuration.
	59	High if defined, Low if not defined
	60	-hsync-active-high:
	61	HSYNC polarity configuration.
	62	High if defined, Low if not defined
	63
	64	Example:
	65
	66	SOC specific portion:
	67	dp-controller {
	68	compatible = "samsung,exynos5-dp";
	69	reg = <0x145b0000 0x10000>;
	70	interrupts = <10 3>;
	71	interrupt-parent = <&combiner>;
60e69858 JH	72	clocks = <&clock 342>;
60e69858 JH	73	clock-names = "dp";
825e90d0	74
8114fabc JH	75	phys = <&dp_phy>;
8114fabc JH	76	phy-names = "dp";
825e90d0 AK	77	};
	78
	79	Board Specific portion:
	80	dp-controller {
	81	samsung,color-space = <0>;
	82	samsung,dynamic-range = <0>;
	83	samsung,ycbcr-coeff = <0>;
	84	samsung,color-depth = <1>;
	85	samsung,link-rate = <0x0a>;
	86	samsung,lane-count = <4>;
	87	};