projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| df2634f4 SAS |
1 | CE4100 Device Tree Bindings |
| 2 | --------------------------- | |
| 3 | ||
| 4 | The CE4100 SoC uses for in core peripherals the following compatible | |
| 5 | format: <vendor>,<chip>-<device>. | |
| 6 | Many of the "generic" devices like HPET or IO APIC have the ce4100 | |
| 7 | name in their compatible property because they first appeared in this | |
| 8 | SoC. | |
| 9 | ||
| 10 | The CPU node | |
| 11 | ------------ | |
| 12 | cpu@0 { | |
| 13 | device_type = "cpu"; | |
| 14 | compatible = "intel,ce4100"; | |
| 15 | reg = <0>; | |
| 16 | lapic = <&lapic0>; | |
| 17 | }; | |
| 18 | ||
| 19 | The reg property describes the CPU number. The lapic property points to | |
| 20 | the local APIC timer. | |
| 21 | ||
| 22 | The SoC node | |
| 23 | ------------ | |
| 24 | ||
| 25 | This node describes the in-core peripherals. Required property: | |
| 26 | compatible = "intel,ce4100-cp"; | |
| 27 | ||
| 28 | The PCI node | |
| 29 | ------------ | |
| 30 | This node describes the PCI bus on the SoC. Its property should be | |
| 31 | compatible = "intel,ce4100-pci", "pci"; | |
| 32 | ||
| 33 | If the OS is using the IO-APIC for interrupt routing then the reported | |
| 34 | interrupt numbers for devices is no longer true. In order to obtain the | |
| 35 | correct interrupt number, the child node which represents the device has | |
| 36 | to contain the interrupt property. Besides the interrupt property it has | |
| 37 | to contain at least the reg property containing the PCI bus address and | |
| 38 | compatible property according to "PCI Bus Binding Revision 2.1". |