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1 | STMicroelectronics 10/100/1000 Synopsys Ethernet driver |
2 | ||
0b7a43d3 | 3 | Copyright (C) 2007-2015 STMicroelectronics Ltd |
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4 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
5 | ||
6 | This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers | |
5b993268 | 7 | (Synopsys IP blocks). |
a1d6f3f6 | 8 | |
233b36cf | 9 | Currently this network device driver is for all STi embedded MAC/GMAC |
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10 | (i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000 |
11 | FF1152AMT0221 D1215994A VIRTEX FPGA board. | |
a1d6f3f6 | 12 | |
49cfbf67 | 13 | DWC Ether MAC 10/100/1000 Universal version 3.70a (and older) and DWC Ether |
3d237714 | 14 | MAC 10/100 Universal version 4.0 have been used for developing this driver. |
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15 | |
16 | This driver supports both the platform bus and PCI. | |
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17 | |
18 | Please, for more information also visit: www.stlinux.com | |
19 | ||
20 | 1) Kernel Configuration | |
21 | The kernel configuration option is STMMAC_ETH: | |
22 | Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) ---> | |
23 | STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH) | |
24 | ||
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25 | CONFIG_STMMAC_PLATFORM: is to enable the platform driver. |
26 | CONFIG_STMMAC_PCI: is to enable the pci driver. | |
27 | ||
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28 | 2) Driver parameters list: |
29 | debug: message level (0: no output, 16: all); | |
30 | phyaddr: to manually provide the physical address to the PHY device; | |
31 | dma_rxsize: DMA rx ring size; | |
32 | dma_txsize: DMA tx ring size; | |
33 | buf_sz: DMA buffer size; | |
34 | tc: control the HW FIFO threshold; | |
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35 | watchdog: transmit timeout (in milliseconds); |
36 | flow_ctrl: Flow control ability [on/off]; | |
37 | pause: Flow Control Pause Time; | |
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38 | eee_timer: tx EEE timer; |
39 | chain_mode: select chain mode instead of ring. | |
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40 | |
41 | 3) Command line options | |
42 | Driver parameters can be also passed in command line by using: | |
43 | stmmaceth=dma_rxsize:128,dma_txsize:512 | |
44 | ||
45 | 4) Driver information and notes | |
46 | ||
47 | 4.1) Transmit process | |
48 | The xmit method is invoked when the kernel needs to transmit a packet; it sets | |
49 | the descriptors in the ring and informs the DMA engine that there is a packet | |
50 | ready to be transmitted. | |
a1d6f3f6 | 51 | By default, the driver sets the NETIF_F_SG bit in the features field of the |
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52 | net_device structure enabling the scatter-gather feature. This is true on |
53 | chips and configurations where the checksum can be done in hardware. | |
54 | Once the controller has finished transmitting the packet, napi will be | |
55 | scheduled to release the transmit resources. | |
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56 | |
57 | 4.2) Receive process | |
58 | When one or more packets are received, an interrupt happens. The interrupts | |
59 | are not queued so the driver has to scan all the descriptors in the ring during | |
60 | the receive process. | |
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61 | This is based on NAPI so the interrupt handler signals only if there is work |
62 | to be done, and it exits. | |
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63 | Then the poll method will be scheduled at some future point. |
64 | The incoming packets are stored, by the DMA, in a list of pre-allocated socket | |
233b36cf | 65 | buffers in order to avoid the memcpy (zero-copy). |
a1d6f3f6 | 66 | |
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67 | 4.3) Interrupt Mitigation |
68 | The driver is able to mitigate the number of its DMA interrupts | |
69 | using NAPI for the reception on chips older than the 3.50. | |
70 | New chips have an HW RX-Watchdog used for this mitigation. | |
f9e01b55 | 71 | Mitigation parameters can be tuned by ethtool. |
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72 | |
73 | 4.4) WOL | |
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74 | Wake up on Lan feature through Magic and Unicast frames are supported for the |
75 | GMAC core. | |
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76 | |
77 | 4.5) DMA descriptors | |
233b36cf | 78 | Driver handles both normal and alternate descriptors. The latter has been only |
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79 | tested on DWC Ether MAC 10/100/1000 Universal version 3.41a and later. |
80 | ||
81 | STMMAC supports DMA descriptor to operate both in dual buffer (RING) | |
82 | and linked-list(CHAINED) mode. In RING each descriptor points to two | |
83 | data buffer pointers whereas in CHAINED mode they point to only one data | |
84 | buffer pointer. RING mode is the default. | |
85 | ||
86 | In CHAINED mode each descriptor will have pointer to next descriptor in | |
87 | the list, hence creating the explicit chaining in the descriptor itself, | |
88 | whereas such explicit chaining is not possible in RING mode. | |
a1d6f3f6 | 89 | |
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90 | 4.5.1) Extended descriptors |
91 | The extended descriptors give us information about the Ethernet payload | |
92 | when it is carrying PTP packets or TCP/UDP/ICMP over IP. | |
93 | These are not available on GMAC Synopsys chips older than the 3.50. | |
94 | At probe time the driver will decide if these can be actually used. | |
95 | This support also is mandatory for PTPv2 because the extra descriptors | |
96 | are used for saving the hardware timestamps and Extended Status. | |
97 | ||
a1d6f3f6 | 98 | 4.6) Ethtool support |
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99 | Ethtool is supported. |
100 | ||
101 | For example, driver statistics (including RMON), internal errors can be taken | |
102 | using: | |
103 | # ethtool -S ethX command | |
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104 | |
105 | 4.7) Jumbo and Segmentation Offloading | |
106 | Jumbo frames are supported and tested for the GMAC. | |
107 | The GSO has been also added but it's performed in software. | |
108 | LRO is not supported. | |
109 | ||
110 | 4.8) Physical | |
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111 | The driver is compatible with Physical Abstraction Layer to be connected with |
112 | PHY and GPHY devices. | |
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113 | |
114 | 4.9) Platform information | |
233b36cf | 115 | Several information can be passed through the platform and device-tree. |
a1d6f3f6 | 116 | |
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117 | struct plat_stmmacenet_data { |
118 | char *phy_bus_name; | |
f5539b5b | 119 | int bus_id; |
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120 | int phy_addr; |
121 | int interface; | |
122 | struct stmmac_mdio_bus_data *mdio_bus_data; | |
8327eb65 | 123 | struct stmmac_dma_cfg *dma_cfg; |
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124 | int clk_csr; |
125 | int has_gmac; | |
126 | int enh_desc; | |
127 | int tx_coe; | |
55f9a4d6 | 128 | int rx_coe; |
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129 | int bugged_jumbo; |
130 | int pmt; | |
557e2a39 | 131 | int force_sf_dma_mode; |
e2a240c7 | 132 | int force_thresh_dma_mode; |
f9e01b55 | 133 | int riwt_off; |
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134 | int max_speed; |
135 | int maxmtu; | |
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136 | void (*fix_mac_speed)(void *priv, unsigned int speed); |
137 | void (*bus_setup)(void __iomem *ioaddr); | |
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138 | int (*init)(struct platform_device *pdev, void *priv); |
139 | void (*exit)(struct platform_device *pdev, void *priv); | |
557e2a39 | 140 | void *bsp_priv; |
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141 | int has_gmac4; |
142 | bool tso_en; | |
233b36cf | 143 | }; |
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144 | |
145 | Where: | |
3d237714 | 146 | o phy_bus_name: phy bus name to attach to the stmmac. |
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147 | o bus_id: bus identifier. |
148 | o phy_addr: the physical address can be passed from the platform. | |
149 | If it is set to -1 the driver will automatically | |
150 | detect it at run-time by probing all the 32 addresses. | |
151 | o interface: PHY device's interface. | |
152 | o mdio_bus_data: specific platform fields for the MDIO bus. | |
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153 | o dma_cfg: internal DMA parameters |
154 | o pbl: the Programmable Burst Length is maximum number of beats to | |
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155 | be transferred in one DMA transaction. |
156 | GMAC also enables the 4xPBL by default. | |
3d237714 | 157 | o fixed_burst/mixed_burst/burst_len |
cd7201f4 | 158 | o clk_csr: fixed CSR Clock range selection. |
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159 | o has_gmac: uses the GMAC core. |
160 | o enh_desc: if sets the MAC will use the enhanced descriptor structure. | |
161 | o tx_coe: core is able to perform the tx csum in HW. | |
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162 | o rx_coe: the supports three check sum offloading engine types: |
163 | type_1, type_2 (full csum) and no RX coe. | |
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164 | o bugged_jumbo: some HWs are not able to perform the csum in HW for |
165 | over-sized frames due to limited buffer sizes. | |
166 | Setting this flag the csum will be done in SW on | |
167 | JUMBO frames. | |
168 | o pmt: core has the embedded power module (optional). | |
169 | o force_sf_dma_mode: force DMA to use the Store and Forward mode | |
170 | instead of the Threshold. | |
c17cb8b5 | 171 | o force_thresh_dma_mode: force DMA to use the Threshold mode other than |
e2a240c7 | 172 | the Store and Forward mode. |
f9e01b55 | 173 | o riwt_off: force to disable the RX watchdog feature and switch to NAPI mode. |
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174 | o fix_mac_speed: this callback is used for modifying some syscfg registers |
175 | (on ST SoCs) according to the link speed negotiated by the | |
176 | physical layer . | |
177 | o bus_setup: perform HW setup of the bus. For example, on some ST platforms | |
178 | this field is used to configure the AMBA bridge to generate more | |
179 | efficient STBus traffic. | |
75fee595 | 180 | o init/exit: callbacks used for calling a custom initialization; |
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181 | this is sometime necessary on some platforms (e.g. ST boxes) |
182 | where the HW needs to have set some PIO lines or system cfg | |
75fee595 | 183 | registers. init/exit callbacks should not use or modify |
938dfdaa | 184 | platform data. |
c17cb8b5 | 185 | o bsp_priv: another private pointer. |
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186 | o has_gmac4: uses GMAC4 core. |
187 | o tso_en: Enables TSO (TCP Segmentation Offload) feature. | |
557e2a39 | 188 | |
8327eb65 | 189 | For MDIO bus The we have: |
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190 | |
191 | struct stmmac_mdio_bus_data { | |
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192 | int (*phy_reset)(void *priv); |
193 | unsigned int phy_mask; | |
194 | int *irqs; | |
195 | int probed_phy_irq; | |
196 | }; | |
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197 | |
198 | Where: | |
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199 | o phy_reset: hook to reset the phy device attached to the bus. |
200 | o phy_mask: phy mask passed when register the MDIO bus within the driver. | |
201 | o irqs: list of IRQs, one per PHY. | |
202 | o probed_phy_irq: if irqs is NULL, use this for probed PHY. | |
203 | ||
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204 | For DMA engine we have the following internal fields that should be |
205 | tuned according to the HW capabilities. | |
206 | ||
207 | struct stmmac_dma_cfg { | |
208 | int pbl; | |
209 | int fixed_burst; | |
210 | int burst_len_supported; | |
211 | }; | |
212 | ||
213 | Where: | |
214 | o pbl: Programmable Burst Length | |
215 | o fixed_burst: program the DMA to use the fixed burst mode | |
216 | o burst_len: this is the value we put in the register | |
217 | supported values are provided as macros in | |
218 | linux/stmmac.h header file. | |
219 | ||
220 | --- | |
221 | ||
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222 | Below an example how the structures above are using on ST platforms. |
223 | ||
224 | static struct plat_stmmacenet_data stxYYY_ethernet_platform_data = { | |
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225 | .has_gmac = 0, |
226 | .enh_desc = 0, | |
227 | .fix_mac_speed = stxYYY_ethernet_fix_mac_speed, | |
228 | | | |
229 | |-> to write an internal syscfg | |
230 | | on this platform when the | |
231 | | link speed changes from 10 to | |
232 | | 100 and viceversa | |
233 | .init = &stmmac_claim_resource, | |
234 | | | |
235 | |-> On ST SoC this calls own "PAD" | |
236 | | manager framework to claim | |
237 | | all the resources necessary | |
238 | | (GPIO ...). The .custom_cfg field | |
239 | | is used to pass a custom config. | |
240 | }; | |
241 | ||
242 | Below the usage of the stmmac_mdio_bus_data: on this SoC, in fact, | |
243 | there are two MAC cores: one MAC is for MDIO Bus/PHY emulation | |
244 | with fixed_link support. | |
245 | ||
246 | static struct stmmac_mdio_bus_data stmmac1_mdio_bus = { | |
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247 | .phy_reset = phy_reset; |
248 | | | |
249 | |-> function to provide the phy_reset on this board | |
250 | .phy_mask = 0, | |
251 | }; | |
252 | ||
253 | static struct fixed_phy_status stmmac0_fixed_phy_status = { | |
254 | .link = 1, | |
255 | .speed = 100, | |
256 | .duplex = 1, | |
257 | }; | |
258 | ||
259 | During the board's device_init we can configure the first | |
260 | MAC for fixed_link by calling: | |
a5597008 | 261 | fixed_phy_add(PHY_POLL, 1, &stmmac0_fixed_phy_status, -1); |
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262 | and the second one, with a real PHY device attached to the bus, |
263 | by using the stmmac_mdio_bus_data structure (to provide the id, the | |
264 | reset procedure etc). | |
265 | ||
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266 | Note that, starting from new chips, where it is available the HW capability |
267 | register, many configurations are discovered at run-time for example to | |
268 | understand if EEE, HW csum, PTP, enhanced descriptor etc are actually | |
269 | available. As strategy adopted in this driver, the information from the HW | |
270 | capability register can replace what has been passed from the platform. | |
271 | ||
272 | 4.10) Device-tree support. | |
273 | ||
274 | Please see the following document: | |
275 | Documentation/devicetree/bindings/net/stmmac.txt | |
276 | ||
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277 | 4.11) This is a summary of the content of some relevant files: |
278 | o stmmac_main.c: to implement the main network device driver; | |
279 | o stmmac_mdio.c: to provide mdio functions; | |
280 | o stmmac_pci: this the PCI driver; | |
281 | o stmmac_platform.c: this the platform driver (OF supported) | |
282 | o stmmac_ethtool.c: to implement the ethtool support; | |
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283 | o stmmac.h: private driver structure; |
284 | o common.h: common definitions and VFTs; | |
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285 | o mmc_core.c/mmc.h: Management MAC Counters; |
286 | o stmmac_hwtstamp.c: HW timestamp support for PTP; | |
287 | o stmmac_ptp.c: PTP 1588 clock; | |
288 | o dwmac-<XXX>.c: these are for the platform glue-logic file; e.g. dwmac-sti.c | |
289 | for STMicroelectronics SoCs. | |
290 | ||
291 | - GMAC 3.x | |
557e2a39 | 292 | o descs.h: descriptor structure definitions; |
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293 | o dwmac1000_core.c: dwmac GiGa core functions; |
294 | o dwmac1000_dma.c: dma functions for the GMAC chip; | |
295 | o dwmac1000.h: specific header file for the dwmac GiGa; | |
296 | o dwmac100_core: dwmac 100 core code; | |
297 | o dwmac100_dma.c: dma functions for the dwmac 100 chip; | |
557e2a39 | 298 | o dwmac1000.h: specific header file for the MAC; |
233b36cf | 299 | o dwmac_lib.c: generic DMA functions; |
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300 | o enh_desc.c: functions for handling enhanced descriptors; |
301 | o norm_desc.c: functions for handling normal descriptors; | |
302 | o chain_mode.c/ring_mode.c:: functions to manage RING/CHAINED modes; | |
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303 | |
304 | - GMAC4.x generation | |
305 | o dwmac4_core.c: dwmac GMAC4.x core functions; | |
306 | o dwmac4_desc.c: functions for handling GMAC4.x descriptors; | |
307 | o dwmac4_descs.h: descriptor definitions; | |
308 | o dwmac4_dma.c: dma functions for the GMAC4.x chip; | |
309 | o dwmac4_dma.h: dma definitions for the GMAC4.x chip; | |
310 | o dwmac4.h: core definitions for the GMAC4.x chip; | |
311 | o dwmac4_lib.c: generic GMAC4.x functions; | |
312 | ||
313 | 4.12) TSO support (GMAC4.x) | |
314 | ||
315 | TSO (Tcp Segmentation Offload) feature is supported by GMAC 4.x chip family. | |
316 | When a packet is sent through TCP protocol, the TCP stack ensures that | |
317 | the SKB provided to the low level driver (stmmac in our case) matches with | |
318 | the maximum frame len (IP header + TCP header + payload <= 1500 bytes (for | |
319 | MTU set to 1500)). It means that if an application using TCP want to send a | |
320 | packet which will have a length (after adding headers) > 1514 the packet | |
321 | will be split in several TCP packets: The data payload is split and headers | |
322 | (TCP/IP ..) are added. It is done by software. | |
323 | ||
324 | When TSO is enabled, the TCP stack doesn't care about the maximum frame | |
325 | length and provide SKB packet to stmmac as it is. The GMAC IP will have to | |
326 | perform the segmentation by it self to match with maximum frame length. | |
327 | ||
328 | This feature can be enabled in device tree through "snps,tso" entry. | |
557e2a39 | 329 | |
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330 | 5) Debug Information |
331 | ||
332 | The driver exports many information i.e. internal statistics, | |
333 | debug information, MAC and DMA registers etc. | |
334 | ||
335 | These can be read in several ways depending on the | |
336 | type of the information actually needed. | |
337 | ||
338 | For example a user can be use the ethtool support | |
339 | to get statistics: e.g. using: ethtool -S ethX | |
340 | (that shows the Management counters (MMC) if supported) | |
341 | or sees the MAC/DMA registers: e.g. using: ethtool -d ethX | |
342 | ||
233b36cf | 343 | Compiling the Kernel with CONFIG_DEBUG_FS the driver will export the following |
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344 | debugfs entries: |
345 | ||
346 | /sys/kernel/debug/stmmaceth/descriptors_status | |
347 | To show the DMA TX/RX descriptor rings | |
348 | ||
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349 | Developer can also use the "debug" module parameter to get further debug |
350 | information (please see: NETIF Msg Level). | |
4f2f25f9 | 351 | |
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352 | 6) Energy Efficient Ethernet |
353 | ||
354 | Energy Efficient Ethernet(EEE) enables IEEE 802.3 MAC sublayer along | |
355 | with a family of Physical layer to operate in the Low power Idle(LPI) | |
356 | mode. The EEE mode supports the IEEE 802.3 MAC operation at 100Mbps, | |
357 | 1000Mbps & 10Gbps. | |
358 | ||
359 | The LPI mode allows power saving by switching off parts of the | |
360 | communication device functionality when there is no data to be | |
361 | transmitted & received. The system on both the side of the link can | |
362 | disable some functionalities & save power during the period of low-link | |
363 | utilization. The MAC controls whether the system should enter or exit | |
364 | the LPI mode & communicate this to PHY. | |
365 | ||
366 | As soon as the interface is opened, the driver verifies if the EEE can | |
367 | be supported. This is done by looking at both the DMA HW capability | |
368 | register and the PHY devices MCD registers. | |
369 | To enter in Tx LPI mode the driver needs to have a software timer | |
370 | that enable and disable the LPI mode when there is nothing to be | |
371 | transmitted. | |
372 | ||
233b36cf | 373 | 7) Precision Time Protocol (PTP) |
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374 | The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP), |
375 | which enables precise synchronization of clocks in measurement and | |
376 | control systems implemented with technologies such as network | |
377 | communication. | |
378 | ||
379 | In addition to the basic timestamp features mentioned in IEEE 1588-2002 | |
380 | Timestamps, new GMAC cores support the advanced timestamp features. | |
381 | IEEE 1588-2008 that can be enabled when configure the Kernel. | |
382 | ||
233b36cf | 383 | 8) SGMII/RGMII supports |
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384 | New GMAC devices provide own way to manage RGMII/SGMII. |
385 | This information is available at run-time by looking at the | |
386 | HW capability register. This means that the stmmac can manage | |
387 | auto-negotiation and link status w/o using the PHYLIB stuff | |
388 | In fact, the HW provides a subset of extended registers to | |
389 | restart the ANE, verify Full/Half duplex mode and Speed. | |
390 | Also thanks to these registers it is possible to look at the | |
391 | Auto-negotiated Link Parter Ability. |