Commit | Line | Data |
---|---|---|
2744e8af LW |
1 | PINCTRL (PIN CONTROL) subsystem |
2 | This document outlines the pin control subsystem in Linux | |
3 | ||
4 | This subsystem deals with: | |
5 | ||
6 | - Enumerating and naming controllable pins | |
7 | ||
8 | - Multiplexing of pins, pads, fingers (etc) see below for details | |
9 | ||
ae6b4d85 LW |
10 | - Configuration of pins, pads, fingers (etc), such as software-controlled |
11 | biasing and driving mode specific pins, such as pull-up/down, open drain, | |
12 | load capacitance etc. | |
2744e8af LW |
13 | |
14 | Top-level interface | |
15 | =================== | |
16 | ||
17 | Definition of PIN CONTROLLER: | |
18 | ||
19 | - A pin controller is a piece of hardware, usually a set of registers, that | |
20 | can control PINs. It may be able to multiplex, bias, set load capacitance, | |
21 | set drive strength etc for individual pins or groups of pins. | |
22 | ||
23 | Definition of PIN: | |
24 | ||
25 | - PINS are equal to pads, fingers, balls or whatever packaging input or | |
26 | output line you want to control and these are denoted by unsigned integers | |
27 | in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so | |
28 | there may be several such number spaces in a system. This pin space may | |
29 | be sparse - i.e. there may be gaps in the space with numbers where no | |
30 | pin exists. | |
31 | ||
336cdba0 | 32 | When a PIN CONTROLLER is instantiated, it will register a descriptor to the |
2744e8af LW |
33 | pin control framework, and this descriptor contains an array of pin descriptors |
34 | describing the pins handled by this specific pin controller. | |
35 | ||
36 | Here is an example of a PGA (Pin Grid Array) chip seen from underneath: | |
37 | ||
38 | A B C D E F G H | |
39 | ||
40 | 8 o o o o o o o o | |
41 | ||
42 | 7 o o o o o o o o | |
43 | ||
44 | 6 o o o o o o o o | |
45 | ||
46 | 5 o o o o o o o o | |
47 | ||
48 | 4 o o o o o o o o | |
49 | ||
50 | 3 o o o o o o o o | |
51 | ||
52 | 2 o o o o o o o o | |
53 | ||
54 | 1 o o o o o o o o | |
55 | ||
56 | To register a pin controller and name all the pins on this package we can do | |
57 | this in our driver: | |
58 | ||
59 | #include <linux/pinctrl/pinctrl.h> | |
60 | ||
336cdba0 LW |
61 | const struct pinctrl_pin_desc foo_pins[] = { |
62 | PINCTRL_PIN(0, "A8"), | |
63 | PINCTRL_PIN(1, "B8"), | |
64 | PINCTRL_PIN(2, "C8"), | |
2744e8af | 65 | ... |
336cdba0 LW |
66 | PINCTRL_PIN(61, "F1"), |
67 | PINCTRL_PIN(62, "G1"), | |
68 | PINCTRL_PIN(63, "H1"), | |
2744e8af LW |
69 | }; |
70 | ||
71 | static struct pinctrl_desc foo_desc = { | |
72 | .name = "foo", | |
73 | .pins = foo_pins, | |
74 | .npins = ARRAY_SIZE(foo_pins), | |
75 | .maxpin = 63, | |
76 | .owner = THIS_MODULE, | |
77 | }; | |
78 | ||
79 | int __init foo_probe(void) | |
80 | { | |
81 | struct pinctrl_dev *pctl; | |
82 | ||
83 | pctl = pinctrl_register(&foo_desc, <PARENT>, NULL); | |
84 | if (IS_ERR(pctl)) | |
85 | pr_err("could not register foo pin driver\n"); | |
86 | } | |
87 | ||
ae6b4d85 LW |
88 | To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and |
89 | selected drivers, you need to select them from your machine's Kconfig entry, | |
90 | since these are so tightly integrated with the machines they are used on. | |
91 | See for example arch/arm/mach-u300/Kconfig for an example. | |
92 | ||
2744e8af LW |
93 | Pins usually have fancier names than this. You can find these in the dataheet |
94 | for your chip. Notice that the core pinctrl.h file provides a fancy macro | |
95 | called PINCTRL_PIN() to create the struct entries. As you can see I enumerated | |
336cdba0 LW |
96 | the pins from 0 in the upper left corner to 63 in the lower right corner. |
97 | This enumeration was arbitrarily chosen, in practice you need to think | |
2744e8af LW |
98 | through your numbering system so that it matches the layout of registers |
99 | and such things in your driver, or the code may become complicated. You must | |
100 | also consider matching of offsets to the GPIO ranges that may be handled by | |
101 | the pin controller. | |
102 | ||
103 | For a padring with 467 pads, as opposed to actual pins, I used an enumeration | |
104 | like this, walking around the edge of the chip, which seems to be industry | |
105 | standard too (all these pads had names, too): | |
106 | ||
107 | ||
108 | 0 ..... 104 | |
109 | 466 105 | |
110 | . . | |
111 | . . | |
112 | 358 224 | |
113 | 357 .... 225 | |
114 | ||
115 | ||
116 | Pin groups | |
117 | ========== | |
118 | ||
119 | Many controllers need to deal with groups of pins, so the pin controller | |
120 | subsystem has a mechanism for enumerating groups of pins and retrieving the | |
121 | actual enumerated pins that are part of a certain group. | |
122 | ||
123 | For example, say that we have a group of pins dealing with an SPI interface | |
124 | on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins | |
125 | on { 24, 25 }. | |
126 | ||
127 | These two groups are presented to the pin control subsystem by implementing | |
128 | some generic pinctrl_ops like this: | |
129 | ||
130 | #include <linux/pinctrl/pinctrl.h> | |
131 | ||
132 | struct foo_group { | |
133 | const char *name; | |
134 | const unsigned int *pins; | |
135 | const unsigned num_pins; | |
136 | }; | |
137 | ||
336cdba0 LW |
138 | static const unsigned int spi0_pins[] = { 0, 8, 16, 24 }; |
139 | static const unsigned int i2c0_pins[] = { 24, 25 }; | |
2744e8af LW |
140 | |
141 | static const struct foo_group foo_groups[] = { | |
142 | { | |
143 | .name = "spi0_grp", | |
144 | .pins = spi0_pins, | |
145 | .num_pins = ARRAY_SIZE(spi0_pins), | |
146 | }, | |
147 | { | |
148 | .name = "i2c0_grp", | |
149 | .pins = i2c0_pins, | |
150 | .num_pins = ARRAY_SIZE(i2c0_pins), | |
151 | }, | |
152 | }; | |
153 | ||
154 | ||
d1e90e9e | 155 | static int foo_get_groups_count(struct pinctrl_dev *pctldev) |
2744e8af | 156 | { |
d1e90e9e | 157 | return ARRAY_SIZE(foo_groups); |
2744e8af LW |
158 | } |
159 | ||
160 | static const char *foo_get_group_name(struct pinctrl_dev *pctldev, | |
161 | unsigned selector) | |
162 | { | |
163 | return foo_groups[selector].name; | |
164 | } | |
165 | ||
166 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
167 | unsigned ** const pins, | |
168 | unsigned * const num_pins) | |
169 | { | |
170 | *pins = (unsigned *) foo_groups[selector].pins; | |
171 | *num_pins = foo_groups[selector].num_pins; | |
172 | return 0; | |
173 | } | |
174 | ||
175 | static struct pinctrl_ops foo_pctrl_ops = { | |
d1e90e9e | 176 | .get_groups_count = foo_get_groups_count, |
2744e8af LW |
177 | .get_group_name = foo_get_group_name, |
178 | .get_group_pins = foo_get_group_pins, | |
179 | }; | |
180 | ||
181 | ||
182 | static struct pinctrl_desc foo_desc = { | |
183 | ... | |
184 | .pctlops = &foo_pctrl_ops, | |
185 | }; | |
186 | ||
d1e90e9e VK |
187 | The pin control subsystem will call the .get_groups_count() function to |
188 | determine total number of legal selectors, then it will call the other functions | |
189 | to retrieve the name and pins of the group. Maintaining the data structure of | |
190 | the groups is up to the driver, this is just a simple example - in practice you | |
191 | may need more entries in your group structure, for example specific register | |
192 | ranges associated with each group and so on. | |
2744e8af LW |
193 | |
194 | ||
ae6b4d85 LW |
195 | Pin configuration |
196 | ================= | |
197 | ||
198 | Pins can sometimes be software-configured in an various ways, mostly related | |
199 | to their electronic properties when used as inputs or outputs. For example you | |
200 | may be able to make an output pin high impedance, or "tristate" meaning it is | |
201 | effectively disconnected. You may be able to connect an input pin to VDD or GND | |
202 | using a certain resistor value - pull up and pull down - so that the pin has a | |
203 | stable value when nothing is driving the rail it is connected to, or when it's | |
204 | unconnected. | |
205 | ||
1e2082b5 SW |
206 | Pin configuration can be programmed either using the explicit APIs described |
207 | immediately below, or by adding configuration entries into the mapping table; | |
208 | see section "Board/machine configuration" below. | |
209 | ||
210 | For example, a platform may do the following to pull up a pin to VDD: | |
ae6b4d85 | 211 | |
28a8d14c LW |
212 | #include <linux/pinctrl/consumer.h> |
213 | ||
43699dea | 214 | ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP); |
ae6b4d85 | 215 | |
1e2082b5 SW |
216 | The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP |
217 | above, is entirely defined by the pin controller driver. | |
218 | ||
219 | The pin configuration driver implements callbacks for changing pin | |
220 | configuration in the pin controller ops like this: | |
ae6b4d85 LW |
221 | |
222 | #include <linux/pinctrl/pinctrl.h> | |
223 | #include <linux/pinctrl/pinconf.h> | |
224 | #include "platform_x_pindefs.h" | |
225 | ||
e6337c3c | 226 | static int foo_pin_config_get(struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
227 | unsigned offset, |
228 | unsigned long *config) | |
229 | { | |
230 | struct my_conftype conf; | |
231 | ||
232 | ... Find setting for pin @ offset ... | |
233 | ||
234 | *config = (unsigned long) conf; | |
235 | } | |
236 | ||
e6337c3c | 237 | static int foo_pin_config_set(struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
238 | unsigned offset, |
239 | unsigned long config) | |
240 | { | |
241 | struct my_conftype *conf = (struct my_conftype *) config; | |
242 | ||
243 | switch (conf) { | |
244 | case PLATFORM_X_PULL_UP: | |
245 | ... | |
246 | } | |
247 | } | |
248 | } | |
249 | ||
e6337c3c | 250 | static int foo_pin_config_group_get (struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
251 | unsigned selector, |
252 | unsigned long *config) | |
253 | { | |
254 | ... | |
255 | } | |
256 | ||
e6337c3c | 257 | static int foo_pin_config_group_set (struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
258 | unsigned selector, |
259 | unsigned long config) | |
260 | { | |
261 | ... | |
262 | } | |
263 | ||
264 | static struct pinconf_ops foo_pconf_ops = { | |
265 | .pin_config_get = foo_pin_config_get, | |
266 | .pin_config_set = foo_pin_config_set, | |
267 | .pin_config_group_get = foo_pin_config_group_get, | |
268 | .pin_config_group_set = foo_pin_config_group_set, | |
269 | }; | |
270 | ||
271 | /* Pin config operations are handled by some pin controller */ | |
272 | static struct pinctrl_desc foo_desc = { | |
273 | ... | |
274 | .confops = &foo_pconf_ops, | |
275 | }; | |
276 | ||
277 | Since some controllers have special logic for handling entire groups of pins | |
278 | they can exploit the special whole-group pin control function. The | |
279 | pin_config_group_set() callback is allowed to return the error code -EAGAIN, | |
280 | for groups it does not want to handle, or if it just wants to do some | |
281 | group-level handling and then fall through to iterate over all pins, in which | |
282 | case each individual pin will be treated by separate pin_config_set() calls as | |
283 | well. | |
284 | ||
285 | ||
2744e8af LW |
286 | Interaction with the GPIO subsystem |
287 | =================================== | |
288 | ||
289 | The GPIO drivers may want to perform operations of various types on the same | |
290 | physical pins that are also registered as pin controller pins. | |
291 | ||
c31a00cd LW |
292 | First and foremost, the two subsystems can be used as completely orthogonal, |
293 | see the section named "pin control requests from drivers" and | |
294 | "drivers needing both pin control and GPIOs" below for details. But in some | |
295 | situations a cross-subsystem mapping between pins and GPIOs is needed. | |
296 | ||
2744e8af LW |
297 | Since the pin controller subsystem have its pinspace local to the pin |
298 | controller we need a mapping so that the pin control subsystem can figure out | |
299 | which pin controller handles control of a certain GPIO pin. Since a single | |
300 | pin controller may be muxing several GPIO ranges (typically SoCs that have | |
301 | one set of pins but internally several GPIO silicon blocks, each modeled as | |
302 | a struct gpio_chip) any number of GPIO ranges can be added to a pin controller | |
303 | instance like this: | |
304 | ||
305 | struct gpio_chip chip_a; | |
306 | struct gpio_chip chip_b; | |
307 | ||
308 | static struct pinctrl_gpio_range gpio_range_a = { | |
309 | .name = "chip a", | |
310 | .id = 0, | |
311 | .base = 32, | |
3c739ad0 | 312 | .pin_base = 32, |
2744e8af LW |
313 | .npins = 16, |
314 | .gc = &chip_a; | |
315 | }; | |
316 | ||
3c739ad0 | 317 | static struct pinctrl_gpio_range gpio_range_b = { |
2744e8af LW |
318 | .name = "chip b", |
319 | .id = 0, | |
320 | .base = 48, | |
3c739ad0 | 321 | .pin_base = 64, |
2744e8af LW |
322 | .npins = 8, |
323 | .gc = &chip_b; | |
324 | }; | |
325 | ||
2744e8af LW |
326 | { |
327 | struct pinctrl_dev *pctl; | |
328 | ... | |
329 | pinctrl_add_gpio_range(pctl, &gpio_range_a); | |
330 | pinctrl_add_gpio_range(pctl, &gpio_range_b); | |
331 | } | |
332 | ||
333 | So this complex system has one pin controller handling two different | |
3c739ad0 CP |
334 | GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and |
335 | "chip b" have different .pin_base, which means a start pin number of the | |
336 | GPIO range. | |
337 | ||
338 | The GPIO range of "chip a" starts from the GPIO base of 32 and actual | |
339 | pin range also starts from 32. However "chip b" has different starting | |
340 | offset for the GPIO range and pin range. The GPIO range of "chip b" starts | |
341 | from GPIO number 48, while the pin range of "chip b" starts from 64. | |
2744e8af | 342 | |
3c739ad0 CP |
343 | We can convert a gpio number to actual pin number using this "pin_base". |
344 | They are mapped in the global GPIO pin space at: | |
345 | ||
346 | chip a: | |
347 | - GPIO range : [32 .. 47] | |
348 | - pin range : [32 .. 47] | |
349 | chip b: | |
350 | - GPIO range : [48 .. 55] | |
351 | - pin range : [64 .. 71] | |
2744e8af LW |
352 | |
353 | When GPIO-specific functions in the pin control subsystem are called, these | |
336cdba0 | 354 | ranges will be used to look up the appropriate pin controller by inspecting |
2744e8af LW |
355 | and matching the pin to the pin ranges across all controllers. When a |
356 | pin controller handling the matching range is found, GPIO-specific functions | |
357 | will be called on that specific pin controller. | |
358 | ||
359 | For all functionalities dealing with pin biasing, pin muxing etc, the pin | |
360 | controller subsystem will subtract the range's .base offset from the passed | |
3c739ad0 CP |
361 | in gpio number, and add the ranges's .pin_base offset to retrive a pin number. |
362 | After that, the subsystem passes it on to the pin control driver, so the driver | |
363 | will get an pin number into its handled number range. Further it is also passed | |
2744e8af LW |
364 | the range ID value, so that the pin controller knows which range it should |
365 | deal with. | |
366 | ||
f23f1516 SH |
367 | Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see |
368 | section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind | |
369 | pinctrl and gpio drivers. | |
c31a00cd | 370 | |
2744e8af LW |
371 | PINMUX interfaces |
372 | ================= | |
373 | ||
374 | These calls use the pinmux_* naming prefix. No other calls should use that | |
375 | prefix. | |
376 | ||
377 | ||
378 | What is pinmuxing? | |
379 | ================== | |
380 | ||
381 | PINMUX, also known as padmux, ballmux, alternate functions or mission modes | |
382 | is a way for chip vendors producing some kind of electrical packages to use | |
383 | a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive | |
384 | functions, depending on the application. By "application" in this context | |
385 | we usually mean a way of soldering or wiring the package into an electronic | |
386 | system, even though the framework makes it possible to also change the function | |
387 | at runtime. | |
388 | ||
389 | Here is an example of a PGA (Pin Grid Array) chip seen from underneath: | |
390 | ||
391 | A B C D E F G H | |
392 | +---+ | |
393 | 8 | o | o o o o o o o | |
394 | | | | |
395 | 7 | o | o o o o o o o | |
396 | | | | |
397 | 6 | o | o o o o o o o | |
398 | +---+---+ | |
399 | 5 | o | o | o o o o o o | |
400 | +---+---+ +---+ | |
401 | 4 o o o o o o | o | o | |
402 | | | | |
403 | 3 o o o o o o | o | o | |
404 | | | | |
405 | 2 o o o o o o | o | o | |
406 | +-------+-------+-------+---+---+ | |
407 | 1 | o o | o o | o o | o | o | | |
408 | +-------+-------+-------+---+---+ | |
409 | ||
410 | This is not tetris. The game to think of is chess. Not all PGA/BGA packages | |
411 | are chessboard-like, big ones have "holes" in some arrangement according to | |
412 | different design patterns, but we're using this as a simple example. Of the | |
413 | pins you see some will be taken by things like a few VCC and GND to feed power | |
414 | to the chip, and quite a few will be taken by large ports like an external | |
415 | memory interface. The remaining pins will often be subject to pin multiplexing. | |
416 | ||
417 | The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to | |
418 | its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using | |
419 | pinctrl_register_pins() and a suitable data set as shown earlier. | |
420 | ||
421 | In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port | |
422 | (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as | |
423 | some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can | |
424 | be used as an I2C port (these are just two pins: SCL, SDA). Needless to say, | |
425 | we cannot use the SPI port and I2C port at the same time. However in the inside | |
426 | of the package the silicon performing the SPI logic can alternatively be routed | |
427 | out on pins { G4, G3, G2, G1 }. | |
428 | ||
429 | On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something | |
430 | special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will | |
431 | consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or | |
432 | { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI | |
433 | port on pins { G4, G3, G2, G1 } of course. | |
434 | ||
435 | This way the silicon blocks present inside the chip can be multiplexed "muxed" | |
436 | out on different pin ranges. Often contemporary SoC (systems on chip) will | |
437 | contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to | |
438 | different pins by pinmux settings. | |
439 | ||
440 | Since general-purpose I/O pins (GPIO) are typically always in shortage, it is | |
441 | common to be able to use almost any pin as a GPIO pin if it is not currently | |
442 | in use by some other I/O port. | |
443 | ||
444 | ||
445 | Pinmux conventions | |
446 | ================== | |
447 | ||
448 | The purpose of the pinmux functionality in the pin controller subsystem is to | |
449 | abstract and provide pinmux settings to the devices you choose to instantiate | |
450 | in your machine configuration. It is inspired by the clk, GPIO and regulator | |
451 | subsystems, so devices will request their mux setting, but it's also possible | |
452 | to request a single pin for e.g. GPIO. | |
453 | ||
454 | Definitions: | |
455 | ||
456 | - FUNCTIONS can be switched in and out by a driver residing with the pin | |
457 | control subsystem in the drivers/pinctrl/* directory of the kernel. The | |
458 | pin control driver knows the possible functions. In the example above you can | |
459 | identify three pinmux functions, one for spi, one for i2c and one for mmc. | |
460 | ||
461 | - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array. | |
462 | In this case the array could be something like: { spi0, i2c0, mmc0 } | |
463 | for the three available functions. | |
464 | ||
465 | - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain | |
466 | function is *always* associated with a certain set of pin groups, could | |
467 | be just a single one, but could also be many. In the example above the | |
468 | function i2c is associated with the pins { A5, B5 }, enumerated as | |
469 | { 24, 25 } in the controller pin space. | |
470 | ||
471 | The Function spi is associated with pin groups { A8, A7, A6, A5 } | |
472 | and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and | |
473 | { 38, 46, 54, 62 } respectively. | |
474 | ||
475 | Group names must be unique per pin controller, no two groups on the same | |
476 | controller may have the same name. | |
477 | ||
478 | - The combination of a FUNCTION and a PIN GROUP determine a certain function | |
479 | for a certain set of pins. The knowledge of the functions and pin groups | |
480 | and their machine-specific particulars are kept inside the pinmux driver, | |
481 | from the outside only the enumerators are known, and the driver core can: | |
482 | ||
483 | - Request the name of a function with a certain selector (>= 0) | |
484 | - A list of groups associated with a certain function | |
485 | - Request that a certain group in that list to be activated for a certain | |
486 | function | |
487 | ||
488 | As already described above, pin groups are in turn self-descriptive, so | |
489 | the core will retrieve the actual pin range in a certain group from the | |
490 | driver. | |
491 | ||
492 | - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain | |
493 | device by the board file, device tree or similar machine setup configuration | |
494 | mechanism, similar to how regulators are connected to devices, usually by | |
495 | name. Defining a pin controller, function and group thus uniquely identify | |
496 | the set of pins to be used by a certain device. (If only one possible group | |
497 | of pins is available for the function, no group name need to be supplied - | |
498 | the core will simply select the first and only group available.) | |
499 | ||
500 | In the example case we can define that this particular machine shall | |
501 | use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function | |
502 | fi2c0 group gi2c0, on the primary pin controller, we get mappings | |
503 | like these: | |
504 | ||
505 | { | |
506 | {"map-spi0", spi0, pinctrl0, fspi0, gspi0}, | |
507 | {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0} | |
508 | } | |
509 | ||
1681f5ae SW |
510 | Every map must be assigned a state name, pin controller, device and |
511 | function. The group is not compulsory - if it is omitted the first group | |
512 | presented by the driver as applicable for the function will be selected, | |
513 | which is useful for simple cases. | |
2744e8af LW |
514 | |
515 | It is possible to map several groups to the same combination of device, | |
516 | pin controller and function. This is for cases where a certain function on | |
517 | a certain pin controller may use different sets of pins in different | |
518 | configurations. | |
519 | ||
520 | - PINS for a certain FUNCTION using a certain PIN GROUP on a certain | |
521 | PIN CONTROLLER are provided on a first-come first-serve basis, so if some | |
522 | other device mux setting or GPIO pin request has already taken your physical | |
523 | pin, you will be denied the use of it. To get (activate) a new setting, the | |
524 | old one has to be put (deactivated) first. | |
525 | ||
526 | Sometimes the documentation and hardware registers will be oriented around | |
527 | pads (or "fingers") rather than pins - these are the soldering surfaces on the | |
528 | silicon inside the package, and may or may not match the actual number of | |
529 | pins/balls underneath the capsule. Pick some enumeration that makes sense to | |
530 | you. Define enumerators only for the pins you can control if that makes sense. | |
531 | ||
532 | Assumptions: | |
533 | ||
336cdba0 | 534 | We assume that the number of possible function maps to pin groups is limited by |
2744e8af LW |
535 | the hardware. I.e. we assume that there is no system where any function can be |
536 | mapped to any pin, like in a phone exchange. So the available pins groups for | |
537 | a certain function will be limited to a few choices (say up to eight or so), | |
538 | not hundreds or any amount of choices. This is the characteristic we have found | |
539 | by inspecting available pinmux hardware, and a necessary assumption since we | |
540 | expect pinmux drivers to present *all* possible function vs pin group mappings | |
541 | to the subsystem. | |
542 | ||
543 | ||
544 | Pinmux drivers | |
545 | ============== | |
546 | ||
547 | The pinmux core takes care of preventing conflicts on pins and calling | |
548 | the pin controller driver to execute different settings. | |
549 | ||
550 | It is the responsibility of the pinmux driver to impose further restrictions | |
551 | (say for example infer electronic limitations due to load etc) to determine | |
552 | whether or not the requested function can actually be allowed, and in case it | |
553 | is possible to perform the requested mux setting, poke the hardware so that | |
554 | this happens. | |
555 | ||
556 | Pinmux drivers are required to supply a few callback functions, some are | |
557 | optional. Usually the enable() and disable() functions are implemented, | |
558 | writing values into some certain registers to activate a certain mux setting | |
559 | for a certain pin. | |
560 | ||
561 | A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4 | |
562 | into some register named MUX to select a certain function with a certain | |
563 | group of pins would work something like this: | |
564 | ||
565 | #include <linux/pinctrl/pinctrl.h> | |
566 | #include <linux/pinctrl/pinmux.h> | |
567 | ||
568 | struct foo_group { | |
569 | const char *name; | |
570 | const unsigned int *pins; | |
571 | const unsigned num_pins; | |
572 | }; | |
573 | ||
574 | static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 }; | |
575 | static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 }; | |
576 | static const unsigned i2c0_pins[] = { 24, 25 }; | |
577 | static const unsigned mmc0_1_pins[] = { 56, 57 }; | |
578 | static const unsigned mmc0_2_pins[] = { 58, 59 }; | |
579 | static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 }; | |
580 | ||
581 | static const struct foo_group foo_groups[] = { | |
582 | { | |
583 | .name = "spi0_0_grp", | |
584 | .pins = spi0_0_pins, | |
585 | .num_pins = ARRAY_SIZE(spi0_0_pins), | |
586 | }, | |
587 | { | |
588 | .name = "spi0_1_grp", | |
589 | .pins = spi0_1_pins, | |
590 | .num_pins = ARRAY_SIZE(spi0_1_pins), | |
591 | }, | |
592 | { | |
593 | .name = "i2c0_grp", | |
594 | .pins = i2c0_pins, | |
595 | .num_pins = ARRAY_SIZE(i2c0_pins), | |
596 | }, | |
597 | { | |
598 | .name = "mmc0_1_grp", | |
599 | .pins = mmc0_1_pins, | |
600 | .num_pins = ARRAY_SIZE(mmc0_1_pins), | |
601 | }, | |
602 | { | |
603 | .name = "mmc0_2_grp", | |
604 | .pins = mmc0_2_pins, | |
605 | .num_pins = ARRAY_SIZE(mmc0_2_pins), | |
606 | }, | |
607 | { | |
608 | .name = "mmc0_3_grp", | |
609 | .pins = mmc0_3_pins, | |
610 | .num_pins = ARRAY_SIZE(mmc0_3_pins), | |
611 | }, | |
612 | }; | |
613 | ||
614 | ||
d1e90e9e | 615 | static int foo_get_groups_count(struct pinctrl_dev *pctldev) |
2744e8af | 616 | { |
d1e90e9e | 617 | return ARRAY_SIZE(foo_groups); |
2744e8af LW |
618 | } |
619 | ||
620 | static const char *foo_get_group_name(struct pinctrl_dev *pctldev, | |
621 | unsigned selector) | |
622 | { | |
623 | return foo_groups[selector].name; | |
624 | } | |
625 | ||
626 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
627 | unsigned ** const pins, | |
628 | unsigned * const num_pins) | |
629 | { | |
630 | *pins = (unsigned *) foo_groups[selector].pins; | |
631 | *num_pins = foo_groups[selector].num_pins; | |
632 | return 0; | |
633 | } | |
634 | ||
635 | static struct pinctrl_ops foo_pctrl_ops = { | |
d1e90e9e | 636 | .get_groups_count = foo_get_groups_count, |
2744e8af LW |
637 | .get_group_name = foo_get_group_name, |
638 | .get_group_pins = foo_get_group_pins, | |
639 | }; | |
640 | ||
641 | struct foo_pmx_func { | |
642 | const char *name; | |
643 | const char * const *groups; | |
644 | const unsigned num_groups; | |
645 | }; | |
646 | ||
eb181c35 | 647 | static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" }; |
2744e8af LW |
648 | static const char * const i2c0_groups[] = { "i2c0_grp" }; |
649 | static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", | |
650 | "mmc0_3_grp" }; | |
651 | ||
652 | static const struct foo_pmx_func foo_functions[] = { | |
653 | { | |
654 | .name = "spi0", | |
655 | .groups = spi0_groups, | |
656 | .num_groups = ARRAY_SIZE(spi0_groups), | |
657 | }, | |
658 | { | |
659 | .name = "i2c0", | |
660 | .groups = i2c0_groups, | |
661 | .num_groups = ARRAY_SIZE(i2c0_groups), | |
662 | }, | |
663 | { | |
664 | .name = "mmc0", | |
665 | .groups = mmc0_groups, | |
666 | .num_groups = ARRAY_SIZE(mmc0_groups), | |
667 | }, | |
668 | }; | |
669 | ||
d1e90e9e | 670 | int foo_get_functions_count(struct pinctrl_dev *pctldev) |
2744e8af | 671 | { |
d1e90e9e | 672 | return ARRAY_SIZE(foo_functions); |
2744e8af LW |
673 | } |
674 | ||
675 | const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) | |
676 | { | |
336cdba0 | 677 | return foo_functions[selector].name; |
2744e8af LW |
678 | } |
679 | ||
680 | static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
681 | const char * const **groups, | |
682 | unsigned * const num_groups) | |
683 | { | |
684 | *groups = foo_functions[selector].groups; | |
685 | *num_groups = foo_functions[selector].num_groups; | |
686 | return 0; | |
687 | } | |
688 | ||
689 | int foo_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
690 | unsigned group) | |
691 | { | |
336cdba0 | 692 | u8 regbit = (1 << selector + group); |
2744e8af LW |
693 | |
694 | writeb((readb(MUX)|regbit), MUX) | |
695 | return 0; | |
696 | } | |
697 | ||
336cdba0 | 698 | void foo_disable(struct pinctrl_dev *pctldev, unsigned selector, |
2744e8af LW |
699 | unsigned group) |
700 | { | |
336cdba0 | 701 | u8 regbit = (1 << selector + group); |
2744e8af LW |
702 | |
703 | writeb((readb(MUX) & ~(regbit)), MUX) | |
704 | return 0; | |
705 | } | |
706 | ||
707 | struct pinmux_ops foo_pmxops = { | |
d1e90e9e | 708 | .get_functions_count = foo_get_functions_count, |
2744e8af LW |
709 | .get_function_name = foo_get_fname, |
710 | .get_function_groups = foo_get_groups, | |
711 | .enable = foo_enable, | |
712 | .disable = foo_disable, | |
713 | }; | |
714 | ||
715 | /* Pinmux operations are handled by some pin controller */ | |
716 | static struct pinctrl_desc foo_desc = { | |
717 | ... | |
718 | .pctlops = &foo_pctrl_ops, | |
719 | .pmxops = &foo_pmxops, | |
720 | }; | |
721 | ||
722 | In the example activating muxing 0 and 1 at the same time setting bits | |
723 | 0 and 1, uses one pin in common so they would collide. | |
724 | ||
725 | The beauty of the pinmux subsystem is that since it keeps track of all | |
726 | pins and who is using them, it will already have denied an impossible | |
727 | request like that, so the driver does not need to worry about such | |
728 | things - when it gets a selector passed in, the pinmux subsystem makes | |
729 | sure no other device or GPIO assignment is already using the selected | |
730 | pins. Thus bits 0 and 1 in the control register will never be set at the | |
731 | same time. | |
732 | ||
733 | All the above functions are mandatory to implement for a pinmux driver. | |
734 | ||
735 | ||
e93bcee0 LW |
736 | Pin control interaction with the GPIO subsystem |
737 | =============================================== | |
2744e8af | 738 | |
fdba2d06 LW |
739 | Note that the following implies that the use case is to use a certain pin |
740 | from the Linux kernel using the API in <linux/gpio.h> with gpio_request() | |
741 | and similar functions. There are cases where you may be using something | |
742 | that your datasheet calls "GPIO mode" but actually is just an electrical | |
743 | configuration for a certain device. See the section below named | |
744 | "GPIO mode pitfalls" for more details on this scenario. | |
745 | ||
e93bcee0 LW |
746 | The public pinmux API contains two functions named pinctrl_request_gpio() |
747 | and pinctrl_free_gpio(). These two functions shall *ONLY* be called from | |
542e704f | 748 | gpiolib-based drivers as part of their gpio_request() and |
e93bcee0 | 749 | gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output] |
542e704f LW |
750 | shall only be called from within respective gpio_direction_[input|output] |
751 | gpiolib implementation. | |
752 | ||
753 | NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be | |
e93bcee0 LW |
754 | controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have |
755 | that driver request proper muxing and other control for its pins. | |
542e704f | 756 | |
2744e8af LW |
757 | The function list could become long, especially if you can convert every |
758 | individual pin into a GPIO pin independent of any other pins, and then try | |
759 | the approach to define every pin as a function. | |
760 | ||
761 | In this case, the function array would become 64 entries for each GPIO | |
762 | setting and then the device functions. | |
763 | ||
e93bcee0 | 764 | For this reason there are two functions a pin control driver can implement |
542e704f LW |
765 | to enable only GPIO on an individual pin: .gpio_request_enable() and |
766 | .gpio_disable_free(). | |
2744e8af LW |
767 | |
768 | This function will pass in the affected GPIO range identified by the pin | |
769 | controller core, so you know which GPIO pins are being affected by the request | |
770 | operation. | |
771 | ||
542e704f LW |
772 | If your driver needs to have an indication from the framework of whether the |
773 | GPIO pin shall be used for input or output you can implement the | |
774 | .gpio_set_direction() function. As described this shall be called from the | |
775 | gpiolib driver and the affected GPIO range, pin offset and desired direction | |
776 | will be passed along to this function. | |
777 | ||
778 | Alternatively to using these special functions, it is fully allowed to use | |
e93bcee0 | 779 | named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to |
542e704f LW |
780 | obtain the function "gpioN" where "N" is the global GPIO pin number if no |
781 | special GPIO-handler is registered. | |
2744e8af LW |
782 | |
783 | ||
fdba2d06 LW |
784 | GPIO mode pitfalls |
785 | ================== | |
786 | ||
787 | Sometime the developer may be confused by a datasheet talking about a pin | |
788 | being possible to set into "GPIO mode". It appears that what hardware | |
789 | engineers mean with "GPIO mode" is not necessarily the use case that is | |
790 | implied in the kernel interface <linux/gpio.h>: a pin that you grab from | |
791 | kernel code and then either listen for input or drive high/low to | |
792 | assert/deassert some external line. | |
793 | ||
794 | Rather hardware engineers think that "GPIO mode" means that you can | |
795 | software-control a few electrical properties of the pin that you would | |
796 | not be able to control if the pin was in some other mode, such as muxed in | |
797 | for a device. | |
798 | ||
799 | Example: a pin is usually muxed in to be used as a UART TX line. But during | |
800 | system sleep, we need to put this pin into "GPIO mode" and ground it. | |
801 | ||
802 | If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start | |
803 | to think that you need to come up with something real complex, that the | |
804 | pin shall be used for UART TX and GPIO at the same time, that you will grab | |
805 | a pin control handle and set it to a certain state to enable UART TX to be | |
806 | muxed in, then twist it over to GPIO mode and use gpio_direction_output() | |
807 | to drive it low during sleep, then mux it over to UART TX again when you | |
808 | wake up and maybe even gpio_request/gpio_free as part of this cycle. This | |
809 | all gets very complicated. | |
810 | ||
811 | The solution is to not think that what the datasheet calls "GPIO mode" | |
812 | has to be handled by the <linux/gpio.h> interface. Instead view this as | |
813 | a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h> | |
814 | and you find this in the documentation: | |
815 | ||
816 | PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument | |
817 | 1 to indicate high level, argument 0 to indicate low level. | |
818 | ||
819 | So it is perfectly possible to push a pin into "GPIO mode" and drive the | |
820 | line low as part of the usual pin control map. So for example your UART | |
821 | driver may look like this: | |
822 | ||
823 | #include <linux/pinctrl/consumer.h> | |
824 | ||
825 | struct pinctrl *pinctrl; | |
826 | struct pinctrl_state *pins_default; | |
827 | struct pinctrl_state *pins_sleep; | |
828 | ||
829 | pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT); | |
830 | pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP); | |
831 | ||
832 | /* Normal mode */ | |
833 | retval = pinctrl_select_state(pinctrl, pins_default); | |
834 | /* Sleep mode */ | |
835 | retval = pinctrl_select_state(pinctrl, pins_sleep); | |
836 | ||
837 | And your machine configuration may look like this: | |
838 | -------------------------------------------------- | |
839 | ||
840 | static unsigned long uart_default_mode[] = { | |
841 | PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0), | |
842 | }; | |
843 | ||
844 | static unsigned long uart_sleep_mode[] = { | |
845 | PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0), | |
846 | }; | |
847 | ||
848 | static struct pinctrl_map __initdata pinmap[] = { | |
849 | PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", | |
850 | "u0_group", "u0"), | |
851 | PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", | |
852 | "UART_TX_PIN", uart_default_mode), | |
853 | PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", | |
854 | "u0_group", "gpio-mode"), | |
855 | PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", | |
856 | "UART_TX_PIN", uart_sleep_mode), | |
857 | }; | |
858 | ||
859 | foo_init(void) { | |
860 | pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap)); | |
861 | } | |
862 | ||
863 | Here the pins we want to control are in the "u0_group" and there is some | |
864 | function called "u0" that can be enabled on this group of pins, and then | |
865 | everything is UART business as usual. But there is also some function | |
866 | named "gpio-mode" that can be mapped onto the same pins to move them into | |
867 | GPIO mode. | |
868 | ||
869 | This will give the desired effect without any bogus interaction with the | |
870 | GPIO subsystem. It is just an electrical configuration used by that device | |
871 | when going to sleep, it might imply that the pin is set into something the | |
872 | datasheet calls "GPIO mode" but that is not the point: it is still used | |
873 | by that UART device to control the pins that pertain to that very UART | |
874 | driver, putting them into modes needed by the UART. GPIO in the Linux | |
875 | kernel sense are just some 1-bit line, and is a different use case. | |
876 | ||
877 | How the registers are poked to attain the push/pull and output low | |
878 | configuration and the muxing of the "u0" or "gpio-mode" group onto these | |
879 | pins is a question for the driver. | |
880 | ||
881 | Some datasheets will be more helpful and refer to the "GPIO mode" as | |
882 | "low power mode" rather than anything to do with GPIO. This often means | |
883 | the same thing electrically speaking, but in this latter case the | |
884 | software engineers will usually quickly identify that this is some | |
885 | specific muxing/configuration rather than anything related to the GPIO | |
886 | API. | |
887 | ||
888 | ||
1e2082b5 | 889 | Board/machine configuration |
2744e8af LW |
890 | ================================== |
891 | ||
892 | Boards and machines define how a certain complete running system is put | |
893 | together, including how GPIOs and devices are muxed, how regulators are | |
894 | constrained and how the clock tree looks. Of course pinmux settings are also | |
895 | part of this. | |
896 | ||
1e2082b5 SW |
897 | A pin controller configuration for a machine looks pretty much like a simple |
898 | regulator configuration, so for the example array above we want to enable i2c | |
899 | and spi on the second function mapping: | |
2744e8af LW |
900 | |
901 | #include <linux/pinctrl/machine.h> | |
902 | ||
122dbe7e | 903 | static const struct pinctrl_map mapping[] __initconst = { |
2744e8af | 904 | { |
806d3143 | 905 | .dev_name = "foo-spi.0", |
110e4ec5 | 906 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 907 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 908 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 909 | .data.mux.function = "spi0", |
2744e8af LW |
910 | }, |
911 | { | |
806d3143 | 912 | .dev_name = "foo-i2c.0", |
110e4ec5 | 913 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 914 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 915 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 916 | .data.mux.function = "i2c0", |
2744e8af LW |
917 | }, |
918 | { | |
806d3143 | 919 | .dev_name = "foo-mmc.0", |
110e4ec5 | 920 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 921 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 922 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 923 | .data.mux.function = "mmc0", |
2744e8af LW |
924 | }, |
925 | }; | |
926 | ||
927 | The dev_name here matches to the unique device name that can be used to look | |
928 | up the device struct (just like with clockdev or regulators). The function name | |
929 | must match a function provided by the pinmux driver handling this pin range. | |
930 | ||
931 | As you can see we may have several pin controllers on the system and thus | |
932 | we need to specify which one of them that contain the functions we wish | |
9dfac4fd | 933 | to map. |
2744e8af LW |
934 | |
935 | You register this pinmux mapping to the pinmux subsystem by simply: | |
936 | ||
e93bcee0 | 937 | ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping)); |
2744e8af LW |
938 | |
939 | Since the above construct is pretty common there is a helper macro to make | |
51cd24ee | 940 | it even more compact which assumes you want to use pinctrl-foo and position |
2744e8af LW |
941 | 0 for mapping, for example: |
942 | ||
e93bcee0 | 943 | static struct pinctrl_map __initdata mapping[] = { |
1e2082b5 SW |
944 | PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"), |
945 | }; | |
946 | ||
947 | The mapping table may also contain pin configuration entries. It's common for | |
948 | each pin/group to have a number of configuration entries that affect it, so | |
949 | the table entries for configuration reference an array of config parameters | |
950 | and values. An example using the convenience macros is shown below: | |
951 | ||
952 | static unsigned long i2c_grp_configs[] = { | |
953 | FOO_PIN_DRIVEN, | |
954 | FOO_PIN_PULLUP, | |
955 | }; | |
956 | ||
957 | static unsigned long i2c_pin_configs[] = { | |
958 | FOO_OPEN_COLLECTOR, | |
959 | FOO_SLEW_RATE_SLOW, | |
960 | }; | |
961 | ||
962 | static struct pinctrl_map __initdata mapping[] = { | |
963 | PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"), | |
d1a83d3b DM |
964 | PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs), |
965 | PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs), | |
966 | PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs), | |
1e2082b5 SW |
967 | }; |
968 | ||
969 | Finally, some devices expect the mapping table to contain certain specific | |
970 | named states. When running on hardware that doesn't need any pin controller | |
971 | configuration, the mapping table must still contain those named states, in | |
972 | order to explicitly indicate that the states were provided and intended to | |
973 | be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining | |
974 | a named state without causing any pin controller to be programmed: | |
975 | ||
976 | static struct pinctrl_map __initdata mapping[] = { | |
977 | PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT), | |
2744e8af LW |
978 | }; |
979 | ||
980 | ||
981 | Complex mappings | |
982 | ================ | |
983 | ||
984 | As it is possible to map a function to different groups of pins an optional | |
985 | .group can be specified like this: | |
986 | ||
987 | ... | |
988 | { | |
806d3143 | 989 | .dev_name = "foo-spi.0", |
2744e8af | 990 | .name = "spi0-pos-A", |
1e2082b5 | 991 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 992 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
993 | .function = "spi0", |
994 | .group = "spi0_0_grp", | |
2744e8af LW |
995 | }, |
996 | { | |
806d3143 | 997 | .dev_name = "foo-spi.0", |
2744e8af | 998 | .name = "spi0-pos-B", |
1e2082b5 | 999 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1000 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
1001 | .function = "spi0", |
1002 | .group = "spi0_1_grp", | |
2744e8af LW |
1003 | }, |
1004 | ... | |
1005 | ||
1006 | This example mapping is used to switch between two positions for spi0 at | |
1007 | runtime, as described further below under the heading "Runtime pinmuxing". | |
1008 | ||
6e5e959d SW |
1009 | Further it is possible for one named state to affect the muxing of several |
1010 | groups of pins, say for example in the mmc0 example above, where you can | |
2744e8af LW |
1011 | additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all |
1012 | three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the | |
1013 | case), we define a mapping like this: | |
1014 | ||
1015 | ... | |
1016 | { | |
806d3143 | 1017 | .dev_name = "foo-mmc.0", |
f54367f9 | 1018 | .name = "2bit" |
1e2082b5 | 1019 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1020 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1021 | .function = "mmc0", |
336cdba0 | 1022 | .group = "mmc0_1_grp", |
2744e8af LW |
1023 | }, |
1024 | { | |
806d3143 | 1025 | .dev_name = "foo-mmc.0", |
f54367f9 | 1026 | .name = "4bit" |
1e2082b5 | 1027 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1028 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1029 | .function = "mmc0", |
336cdba0 | 1030 | .group = "mmc0_1_grp", |
2744e8af LW |
1031 | }, |
1032 | { | |
806d3143 | 1033 | .dev_name = "foo-mmc.0", |
f54367f9 | 1034 | .name = "4bit" |
1e2082b5 | 1035 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1036 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1037 | .function = "mmc0", |
336cdba0 | 1038 | .group = "mmc0_2_grp", |
2744e8af LW |
1039 | }, |
1040 | { | |
806d3143 | 1041 | .dev_name = "foo-mmc.0", |
f54367f9 | 1042 | .name = "8bit" |
1e2082b5 | 1043 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1044 | .ctrl_dev_name = "pinctrl-foo", |
6e5e959d | 1045 | .function = "mmc0", |
336cdba0 | 1046 | .group = "mmc0_1_grp", |
2744e8af LW |
1047 | }, |
1048 | { | |
806d3143 | 1049 | .dev_name = "foo-mmc.0", |
f54367f9 | 1050 | .name = "8bit" |
1e2082b5 | 1051 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1052 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1053 | .function = "mmc0", |
336cdba0 | 1054 | .group = "mmc0_2_grp", |
2744e8af LW |
1055 | }, |
1056 | { | |
806d3143 | 1057 | .dev_name = "foo-mmc.0", |
f54367f9 | 1058 | .name = "8bit" |
1e2082b5 | 1059 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1060 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1061 | .function = "mmc0", |
336cdba0 | 1062 | .group = "mmc0_3_grp", |
2744e8af LW |
1063 | }, |
1064 | ... | |
1065 | ||
1066 | The result of grabbing this mapping from the device with something like | |
1067 | this (see next paragraph): | |
1068 | ||
6d4ca1fb | 1069 | p = devm_pinctrl_get(dev); |
6e5e959d SW |
1070 | s = pinctrl_lookup_state(p, "8bit"); |
1071 | ret = pinctrl_select_state(p, s); | |
1072 | ||
1073 | or more simply: | |
1074 | ||
6d4ca1fb | 1075 | p = devm_pinctrl_get_select(dev, "8bit"); |
2744e8af LW |
1076 | |
1077 | Will be that you activate all the three bottom records in the mapping at | |
6e5e959d | 1078 | once. Since they share the same name, pin controller device, function and |
2744e8af LW |
1079 | device, and since we allow multiple groups to match to a single device, they |
1080 | all get selected, and they all get enabled and disable simultaneously by the | |
1081 | pinmux core. | |
1082 | ||
1083 | ||
c31a00cd LW |
1084 | Pin control requests from drivers |
1085 | ================================= | |
2744e8af | 1086 | |
ab78029e LW |
1087 | When a device driver is about to probe the device core will automatically |
1088 | attempt to issue pinctrl_get_select_default() on these devices. | |
1089 | This way driver writers do not need to add any of the boilerplate code | |
1090 | of the type found below. However when doing fine-grained state selection | |
1091 | and not using the "default" state, you may have to do some device driver | |
1092 | handling of the pinctrl handles and states. | |
1093 | ||
1094 | So if you just want to put the pins for a certain device into the default | |
1095 | state and be done with it, there is nothing you need to do besides | |
1096 | providing the proper mapping table. The device core will take care of | |
1097 | the rest. | |
1098 | ||
e93bcee0 LW |
1099 | Generally it is discouraged to let individual drivers get and enable pin |
1100 | control. So if possible, handle the pin control in platform code or some other | |
1101 | place where you have access to all the affected struct device * pointers. In | |
1102 | some cases where a driver needs to e.g. switch between different mux mappings | |
1103 | at runtime this is not possible. | |
2744e8af | 1104 | |
c31a00cd LW |
1105 | A typical case is if a driver needs to switch bias of pins from normal |
1106 | operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to | |
1107 | PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save | |
1108 | current in sleep mode. | |
1109 | ||
e93bcee0 LW |
1110 | A driver may request a certain control state to be activated, usually just the |
1111 | default state like this: | |
2744e8af | 1112 | |
28a8d14c | 1113 | #include <linux/pinctrl/consumer.h> |
2744e8af LW |
1114 | |
1115 | struct foo_state { | |
e93bcee0 | 1116 | struct pinctrl *p; |
6e5e959d | 1117 | struct pinctrl_state *s; |
2744e8af LW |
1118 | ... |
1119 | }; | |
1120 | ||
1121 | foo_probe() | |
1122 | { | |
6e5e959d SW |
1123 | /* Allocate a state holder named "foo" etc */ |
1124 | struct foo_state *foo = ...; | |
1125 | ||
6d4ca1fb | 1126 | foo->p = devm_pinctrl_get(&device); |
6e5e959d SW |
1127 | if (IS_ERR(foo->p)) { |
1128 | /* FIXME: clean up "foo" here */ | |
1129 | return PTR_ERR(foo->p); | |
1130 | } | |
2744e8af | 1131 | |
6e5e959d SW |
1132 | foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT); |
1133 | if (IS_ERR(foo->s)) { | |
6e5e959d SW |
1134 | /* FIXME: clean up "foo" here */ |
1135 | return PTR_ERR(s); | |
1136 | } | |
2744e8af | 1137 | |
6e5e959d SW |
1138 | ret = pinctrl_select_state(foo->s); |
1139 | if (ret < 0) { | |
6e5e959d SW |
1140 | /* FIXME: clean up "foo" here */ |
1141 | return ret; | |
1142 | } | |
2744e8af LW |
1143 | } |
1144 | ||
6e5e959d | 1145 | This get/lookup/select/put sequence can just as well be handled by bus drivers |
2744e8af LW |
1146 | if you don't want each and every driver to handle it and you know the |
1147 | arrangement on your bus. | |
1148 | ||
6e5e959d SW |
1149 | The semantics of the pinctrl APIs are: |
1150 | ||
1151 | - pinctrl_get() is called in process context to obtain a handle to all pinctrl | |
1152 | information for a given client device. It will allocate a struct from the | |
1153 | kernel memory to hold the pinmux state. All mapping table parsing or similar | |
1154 | slow operations take place within this API. | |
2744e8af | 1155 | |
6d4ca1fb SW |
1156 | - devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put() |
1157 | to be called automatically on the retrieved pointer when the associated | |
1158 | device is removed. It is recommended to use this function over plain | |
1159 | pinctrl_get(). | |
1160 | ||
6e5e959d SW |
1161 | - pinctrl_lookup_state() is called in process context to obtain a handle to a |
1162 | specific state for a the client device. This operation may be slow too. | |
2744e8af | 1163 | |
6e5e959d SW |
1164 | - pinctrl_select_state() programs pin controller hardware according to the |
1165 | definition of the state as given by the mapping table. In theory this is a | |
1166 | fast-path operation, since it only involved blasting some register settings | |
1167 | into hardware. However, note that some pin controllers may have their | |
1168 | registers on a slow/IRQ-based bus, so client devices should not assume they | |
1169 | can call pinctrl_select_state() from non-blocking contexts. | |
2744e8af | 1170 | |
6e5e959d | 1171 | - pinctrl_put() frees all information associated with a pinctrl handle. |
2744e8af | 1172 | |
6d4ca1fb SW |
1173 | - devm_pinctrl_put() is a variant of pinctrl_put() that may be used to |
1174 | explicitly destroy a pinctrl object returned by devm_pinctrl_get(). | |
1175 | However, use of this function will be rare, due to the automatic cleanup | |
1176 | that will occur even without calling it. | |
1177 | ||
1178 | pinctrl_get() must be paired with a plain pinctrl_put(). | |
1179 | pinctrl_get() may not be paired with devm_pinctrl_put(). | |
1180 | devm_pinctrl_get() can optionally be paired with devm_pinctrl_put(). | |
1181 | devm_pinctrl_get() may not be paired with plain pinctrl_put(). | |
1182 | ||
e93bcee0 LW |
1183 | Usually the pin control core handled the get/put pair and call out to the |
1184 | device drivers bookkeeping operations, like checking available functions and | |
1185 | the associated pins, whereas the enable/disable pass on to the pin controller | |
2744e8af LW |
1186 | driver which takes care of activating and/or deactivating the mux setting by |
1187 | quickly poking some registers. | |
1188 | ||
6d4ca1fb SW |
1189 | The pins are allocated for your device when you issue the devm_pinctrl_get() |
1190 | call, after this you should be able to see this in the debugfs listing of all | |
1191 | pins. | |
2744e8af | 1192 | |
c05127c4 LW |
1193 | NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the |
1194 | requested pinctrl handles, for example if the pinctrl driver has not yet | |
1195 | registered. Thus make sure that the error path in your driver gracefully | |
1196 | cleans up and is ready to retry the probing later in the startup process. | |
1197 | ||
2744e8af | 1198 | |
c31a00cd LW |
1199 | Drivers needing both pin control and GPIOs |
1200 | ========================================== | |
1201 | ||
1202 | Again, it is discouraged to let drivers lookup and select pin control states | |
1203 | themselves, but again sometimes this is unavoidable. | |
1204 | ||
1205 | So say that your driver is fetching its resources like this: | |
1206 | ||
1207 | #include <linux/pinctrl/consumer.h> | |
1208 | #include <linux/gpio.h> | |
1209 | ||
1210 | struct pinctrl *pinctrl; | |
1211 | int gpio; | |
1212 | ||
1213 | pinctrl = devm_pinctrl_get_select_default(&dev); | |
1214 | gpio = devm_gpio_request(&dev, 14, "foo"); | |
1215 | ||
1216 | Here we first request a certain pin state and then request GPIO 14 to be | |
1217 | used. If you're using the subsystems orthogonally like this, you should | |
1218 | nominally always get your pinctrl handle and select the desired pinctrl | |
1219 | state BEFORE requesting the GPIO. This is a semantic convention to avoid | |
1220 | situations that can be electrically unpleasant, you will certainly want to | |
1221 | mux in and bias pins in a certain way before the GPIO subsystems starts to | |
1222 | deal with them. | |
1223 | ||
ab78029e LW |
1224 | The above can be hidden: using the device core, the pinctrl core may be |
1225 | setting up the config and muxing for the pins right before the device is | |
1226 | probing, nevertheless orthogonal to the GPIO subsystem. | |
c31a00cd LW |
1227 | |
1228 | But there are also situations where it makes sense for the GPIO subsystem | |
1229 | to communicate directly with with the pinctrl subsystem, using the latter | |
1230 | as a back-end. This is when the GPIO driver may call out to the functions | |
1231 | described in the section "Pin control interaction with the GPIO subsystem" | |
1232 | above. This only involves per-pin multiplexing, and will be completely | |
1233 | hidden behind the gpio_*() function namespace. In this case, the driver | |
1234 | need not interact with the pin control subsystem at all. | |
1235 | ||
1236 | If a pin control driver and a GPIO driver is dealing with the same pins | |
1237 | and the use cases involve multiplexing, you MUST implement the pin controller | |
1238 | as a back-end for the GPIO driver like this, unless your hardware design | |
1239 | is such that the GPIO controller can override the pin controller's | |
1240 | multiplexing state through hardware without the need to interact with the | |
1241 | pin control system. | |
1242 | ||
1243 | ||
e93bcee0 LW |
1244 | System pin control hogging |
1245 | ========================== | |
2744e8af | 1246 | |
1681f5ae | 1247 | Pin control map entries can be hogged by the core when the pin controller |
6e5e959d SW |
1248 | is registered. This means that the core will attempt to call pinctrl_get(), |
1249 | lookup_state() and select_state() on it immediately after the pin control | |
1250 | device has been registered. | |
2744e8af | 1251 | |
6e5e959d SW |
1252 | This occurs for mapping table entries where the client device name is equal |
1253 | to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT. | |
2744e8af LW |
1254 | |
1255 | { | |
806d3143 | 1256 | .dev_name = "pinctrl-foo", |
46919ae6 | 1257 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 1258 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1259 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1260 | .function = "power_func", |
2744e8af LW |
1261 | }, |
1262 | ||
1263 | Since it may be common to request the core to hog a few always-applicable | |
1264 | mux settings on the primary pin controller, there is a convenience macro for | |
1265 | this: | |
1266 | ||
1e2082b5 | 1267 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func") |
2744e8af LW |
1268 | |
1269 | This gives the exact same result as the above construction. | |
1270 | ||
1271 | ||
1272 | Runtime pinmuxing | |
1273 | ================= | |
1274 | ||
1275 | It is possible to mux a certain function in and out at runtime, say to move | |
1276 | an SPI port from one set of pins to another set of pins. Say for example for | |
1277 | spi0 in the example above, we expose two different groups of pins for the same | |
1278 | function, but with different named in the mapping as described under | |
6e5e959d SW |
1279 | "Advanced mapping" above. So that for an SPI device, we have two states named |
1280 | "pos-A" and "pos-B". | |
2744e8af LW |
1281 | |
1282 | This snippet first muxes the function in the pins defined by group A, enables | |
1283 | it, disables and releases it, and muxes it in on the pins defined by group B: | |
1284 | ||
28a8d14c LW |
1285 | #include <linux/pinctrl/consumer.h> |
1286 | ||
6d4ca1fb SW |
1287 | struct pinctrl *p; |
1288 | struct pinctrl_state *s1, *s2; | |
6e5e959d | 1289 | |
6d4ca1fb SW |
1290 | foo_probe() |
1291 | { | |
6e5e959d | 1292 | /* Setup */ |
6d4ca1fb | 1293 | p = devm_pinctrl_get(&device); |
6e5e959d SW |
1294 | if (IS_ERR(p)) |
1295 | ... | |
1296 | ||
1297 | s1 = pinctrl_lookup_state(foo->p, "pos-A"); | |
1298 | if (IS_ERR(s1)) | |
1299 | ... | |
1300 | ||
1301 | s2 = pinctrl_lookup_state(foo->p, "pos-B"); | |
1302 | if (IS_ERR(s2)) | |
1303 | ... | |
6d4ca1fb | 1304 | } |
2744e8af | 1305 | |
6d4ca1fb SW |
1306 | foo_switch() |
1307 | { | |
2744e8af | 1308 | /* Enable on position A */ |
6e5e959d SW |
1309 | ret = pinctrl_select_state(s1); |
1310 | if (ret < 0) | |
1311 | ... | |
2744e8af | 1312 | |
6e5e959d | 1313 | ... |
2744e8af LW |
1314 | |
1315 | /* Enable on position B */ | |
6e5e959d SW |
1316 | ret = pinctrl_select_state(s2); |
1317 | if (ret < 0) | |
1318 | ... | |
1319 | ||
2744e8af LW |
1320 | ... |
1321 | } | |
1322 | ||
1a78958d LW |
1323 | The above has to be done from process context. The reservation of the pins |
1324 | will be done when the state is activated, so in effect one specific pin | |
1325 | can be used by different functions at different times on a running system. |