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2744e8af LW |
1 | PINCTRL (PIN CONTROL) subsystem |
2 | This document outlines the pin control subsystem in Linux | |
3 | ||
4 | This subsystem deals with: | |
5 | ||
6 | - Enumerating and naming controllable pins | |
7 | ||
8 | - Multiplexing of pins, pads, fingers (etc) see below for details | |
9 | ||
ae6b4d85 LW |
10 | - Configuration of pins, pads, fingers (etc), such as software-controlled |
11 | biasing and driving mode specific pins, such as pull-up/down, open drain, | |
12 | load capacitance etc. | |
2744e8af LW |
13 | |
14 | Top-level interface | |
15 | =================== | |
16 | ||
17 | Definition of PIN CONTROLLER: | |
18 | ||
19 | - A pin controller is a piece of hardware, usually a set of registers, that | |
20 | can control PINs. It may be able to multiplex, bias, set load capacitance, | |
21 | set drive strength etc for individual pins or groups of pins. | |
22 | ||
23 | Definition of PIN: | |
24 | ||
25 | - PINS are equal to pads, fingers, balls or whatever packaging input or | |
26 | output line you want to control and these are denoted by unsigned integers | |
27 | in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so | |
28 | there may be several such number spaces in a system. This pin space may | |
29 | be sparse - i.e. there may be gaps in the space with numbers where no | |
30 | pin exists. | |
31 | ||
336cdba0 | 32 | When a PIN CONTROLLER is instantiated, it will register a descriptor to the |
2744e8af LW |
33 | pin control framework, and this descriptor contains an array of pin descriptors |
34 | describing the pins handled by this specific pin controller. | |
35 | ||
36 | Here is an example of a PGA (Pin Grid Array) chip seen from underneath: | |
37 | ||
38 | A B C D E F G H | |
39 | ||
40 | 8 o o o o o o o o | |
41 | ||
42 | 7 o o o o o o o o | |
43 | ||
44 | 6 o o o o o o o o | |
45 | ||
46 | 5 o o o o o o o o | |
47 | ||
48 | 4 o o o o o o o o | |
49 | ||
50 | 3 o o o o o o o o | |
51 | ||
52 | 2 o o o o o o o o | |
53 | ||
54 | 1 o o o o o o o o | |
55 | ||
56 | To register a pin controller and name all the pins on this package we can do | |
57 | this in our driver: | |
58 | ||
59 | #include <linux/pinctrl/pinctrl.h> | |
60 | ||
336cdba0 LW |
61 | const struct pinctrl_pin_desc foo_pins[] = { |
62 | PINCTRL_PIN(0, "A8"), | |
63 | PINCTRL_PIN(1, "B8"), | |
64 | PINCTRL_PIN(2, "C8"), | |
2744e8af | 65 | ... |
336cdba0 LW |
66 | PINCTRL_PIN(61, "F1"), |
67 | PINCTRL_PIN(62, "G1"), | |
68 | PINCTRL_PIN(63, "H1"), | |
2744e8af LW |
69 | }; |
70 | ||
71 | static struct pinctrl_desc foo_desc = { | |
72 | .name = "foo", | |
73 | .pins = foo_pins, | |
74 | .npins = ARRAY_SIZE(foo_pins), | |
75 | .maxpin = 63, | |
76 | .owner = THIS_MODULE, | |
77 | }; | |
78 | ||
79 | int __init foo_probe(void) | |
80 | { | |
81 | struct pinctrl_dev *pctl; | |
82 | ||
83 | pctl = pinctrl_register(&foo_desc, <PARENT>, NULL); | |
84 | if (IS_ERR(pctl)) | |
85 | pr_err("could not register foo pin driver\n"); | |
86 | } | |
87 | ||
ae6b4d85 LW |
88 | To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and |
89 | selected drivers, you need to select them from your machine's Kconfig entry, | |
90 | since these are so tightly integrated with the machines they are used on. | |
91 | See for example arch/arm/mach-u300/Kconfig for an example. | |
92 | ||
2744e8af LW |
93 | Pins usually have fancier names than this. You can find these in the dataheet |
94 | for your chip. Notice that the core pinctrl.h file provides a fancy macro | |
95 | called PINCTRL_PIN() to create the struct entries. As you can see I enumerated | |
336cdba0 LW |
96 | the pins from 0 in the upper left corner to 63 in the lower right corner. |
97 | This enumeration was arbitrarily chosen, in practice you need to think | |
2744e8af LW |
98 | through your numbering system so that it matches the layout of registers |
99 | and such things in your driver, or the code may become complicated. You must | |
100 | also consider matching of offsets to the GPIO ranges that may be handled by | |
101 | the pin controller. | |
102 | ||
103 | For a padring with 467 pads, as opposed to actual pins, I used an enumeration | |
104 | like this, walking around the edge of the chip, which seems to be industry | |
105 | standard too (all these pads had names, too): | |
106 | ||
107 | ||
108 | 0 ..... 104 | |
109 | 466 105 | |
110 | . . | |
111 | . . | |
112 | 358 224 | |
113 | 357 .... 225 | |
114 | ||
115 | ||
116 | Pin groups | |
117 | ========== | |
118 | ||
119 | Many controllers need to deal with groups of pins, so the pin controller | |
120 | subsystem has a mechanism for enumerating groups of pins and retrieving the | |
121 | actual enumerated pins that are part of a certain group. | |
122 | ||
123 | For example, say that we have a group of pins dealing with an SPI interface | |
124 | on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins | |
125 | on { 24, 25 }. | |
126 | ||
127 | These two groups are presented to the pin control subsystem by implementing | |
128 | some generic pinctrl_ops like this: | |
129 | ||
130 | #include <linux/pinctrl/pinctrl.h> | |
131 | ||
132 | struct foo_group { | |
133 | const char *name; | |
134 | const unsigned int *pins; | |
135 | const unsigned num_pins; | |
136 | }; | |
137 | ||
336cdba0 LW |
138 | static const unsigned int spi0_pins[] = { 0, 8, 16, 24 }; |
139 | static const unsigned int i2c0_pins[] = { 24, 25 }; | |
2744e8af LW |
140 | |
141 | static const struct foo_group foo_groups[] = { | |
142 | { | |
143 | .name = "spi0_grp", | |
144 | .pins = spi0_pins, | |
145 | .num_pins = ARRAY_SIZE(spi0_pins), | |
146 | }, | |
147 | { | |
148 | .name = "i2c0_grp", | |
149 | .pins = i2c0_pins, | |
150 | .num_pins = ARRAY_SIZE(i2c0_pins), | |
151 | }, | |
152 | }; | |
153 | ||
154 | ||
d1e90e9e | 155 | static int foo_get_groups_count(struct pinctrl_dev *pctldev) |
2744e8af | 156 | { |
d1e90e9e | 157 | return ARRAY_SIZE(foo_groups); |
2744e8af LW |
158 | } |
159 | ||
160 | static const char *foo_get_group_name(struct pinctrl_dev *pctldev, | |
161 | unsigned selector) | |
162 | { | |
163 | return foo_groups[selector].name; | |
164 | } | |
165 | ||
166 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
167 | unsigned ** const pins, | |
168 | unsigned * const num_pins) | |
169 | { | |
170 | *pins = (unsigned *) foo_groups[selector].pins; | |
171 | *num_pins = foo_groups[selector].num_pins; | |
172 | return 0; | |
173 | } | |
174 | ||
175 | static struct pinctrl_ops foo_pctrl_ops = { | |
d1e90e9e | 176 | .get_groups_count = foo_get_groups_count, |
2744e8af LW |
177 | .get_group_name = foo_get_group_name, |
178 | .get_group_pins = foo_get_group_pins, | |
179 | }; | |
180 | ||
181 | ||
182 | static struct pinctrl_desc foo_desc = { | |
183 | ... | |
184 | .pctlops = &foo_pctrl_ops, | |
185 | }; | |
186 | ||
d1e90e9e VK |
187 | The pin control subsystem will call the .get_groups_count() function to |
188 | determine total number of legal selectors, then it will call the other functions | |
189 | to retrieve the name and pins of the group. Maintaining the data structure of | |
190 | the groups is up to the driver, this is just a simple example - in practice you | |
191 | may need more entries in your group structure, for example specific register | |
192 | ranges associated with each group and so on. | |
2744e8af LW |
193 | |
194 | ||
ae6b4d85 LW |
195 | Pin configuration |
196 | ================= | |
197 | ||
198 | Pins can sometimes be software-configured in an various ways, mostly related | |
199 | to their electronic properties when used as inputs or outputs. For example you | |
200 | may be able to make an output pin high impedance, or "tristate" meaning it is | |
201 | effectively disconnected. You may be able to connect an input pin to VDD or GND | |
202 | using a certain resistor value - pull up and pull down - so that the pin has a | |
203 | stable value when nothing is driving the rail it is connected to, or when it's | |
204 | unconnected. | |
205 | ||
1e2082b5 SW |
206 | Pin configuration can be programmed either using the explicit APIs described |
207 | immediately below, or by adding configuration entries into the mapping table; | |
208 | see section "Board/machine configuration" below. | |
209 | ||
210 | For example, a platform may do the following to pull up a pin to VDD: | |
ae6b4d85 | 211 | |
28a8d14c LW |
212 | #include <linux/pinctrl/consumer.h> |
213 | ||
43699dea | 214 | ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP); |
ae6b4d85 | 215 | |
1e2082b5 SW |
216 | The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP |
217 | above, is entirely defined by the pin controller driver. | |
218 | ||
219 | The pin configuration driver implements callbacks for changing pin | |
220 | configuration in the pin controller ops like this: | |
ae6b4d85 LW |
221 | |
222 | #include <linux/pinctrl/pinctrl.h> | |
223 | #include <linux/pinctrl/pinconf.h> | |
224 | #include "platform_x_pindefs.h" | |
225 | ||
e6337c3c | 226 | static int foo_pin_config_get(struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
227 | unsigned offset, |
228 | unsigned long *config) | |
229 | { | |
230 | struct my_conftype conf; | |
231 | ||
232 | ... Find setting for pin @ offset ... | |
233 | ||
234 | *config = (unsigned long) conf; | |
235 | } | |
236 | ||
e6337c3c | 237 | static int foo_pin_config_set(struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
238 | unsigned offset, |
239 | unsigned long config) | |
240 | { | |
241 | struct my_conftype *conf = (struct my_conftype *) config; | |
242 | ||
243 | switch (conf) { | |
244 | case PLATFORM_X_PULL_UP: | |
245 | ... | |
246 | } | |
247 | } | |
248 | } | |
249 | ||
e6337c3c | 250 | static int foo_pin_config_group_get (struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
251 | unsigned selector, |
252 | unsigned long *config) | |
253 | { | |
254 | ... | |
255 | } | |
256 | ||
e6337c3c | 257 | static int foo_pin_config_group_set (struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
258 | unsigned selector, |
259 | unsigned long config) | |
260 | { | |
261 | ... | |
262 | } | |
263 | ||
264 | static struct pinconf_ops foo_pconf_ops = { | |
265 | .pin_config_get = foo_pin_config_get, | |
266 | .pin_config_set = foo_pin_config_set, | |
267 | .pin_config_group_get = foo_pin_config_group_get, | |
268 | .pin_config_group_set = foo_pin_config_group_set, | |
269 | }; | |
270 | ||
271 | /* Pin config operations are handled by some pin controller */ | |
272 | static struct pinctrl_desc foo_desc = { | |
273 | ... | |
274 | .confops = &foo_pconf_ops, | |
275 | }; | |
276 | ||
277 | Since some controllers have special logic for handling entire groups of pins | |
278 | they can exploit the special whole-group pin control function. The | |
279 | pin_config_group_set() callback is allowed to return the error code -EAGAIN, | |
280 | for groups it does not want to handle, or if it just wants to do some | |
281 | group-level handling and then fall through to iterate over all pins, in which | |
282 | case each individual pin will be treated by separate pin_config_set() calls as | |
283 | well. | |
284 | ||
285 | ||
2744e8af LW |
286 | Interaction with the GPIO subsystem |
287 | =================================== | |
288 | ||
289 | The GPIO drivers may want to perform operations of various types on the same | |
290 | physical pins that are also registered as pin controller pins. | |
291 | ||
292 | Since the pin controller subsystem have its pinspace local to the pin | |
293 | controller we need a mapping so that the pin control subsystem can figure out | |
294 | which pin controller handles control of a certain GPIO pin. Since a single | |
295 | pin controller may be muxing several GPIO ranges (typically SoCs that have | |
296 | one set of pins but internally several GPIO silicon blocks, each modeled as | |
297 | a struct gpio_chip) any number of GPIO ranges can be added to a pin controller | |
298 | instance like this: | |
299 | ||
300 | struct gpio_chip chip_a; | |
301 | struct gpio_chip chip_b; | |
302 | ||
303 | static struct pinctrl_gpio_range gpio_range_a = { | |
304 | .name = "chip a", | |
305 | .id = 0, | |
306 | .base = 32, | |
3c739ad0 | 307 | .pin_base = 32, |
2744e8af LW |
308 | .npins = 16, |
309 | .gc = &chip_a; | |
310 | }; | |
311 | ||
3c739ad0 | 312 | static struct pinctrl_gpio_range gpio_range_b = { |
2744e8af LW |
313 | .name = "chip b", |
314 | .id = 0, | |
315 | .base = 48, | |
3c739ad0 | 316 | .pin_base = 64, |
2744e8af LW |
317 | .npins = 8, |
318 | .gc = &chip_b; | |
319 | }; | |
320 | ||
2744e8af LW |
321 | { |
322 | struct pinctrl_dev *pctl; | |
323 | ... | |
324 | pinctrl_add_gpio_range(pctl, &gpio_range_a); | |
325 | pinctrl_add_gpio_range(pctl, &gpio_range_b); | |
326 | } | |
327 | ||
328 | So this complex system has one pin controller handling two different | |
3c739ad0 CP |
329 | GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and |
330 | "chip b" have different .pin_base, which means a start pin number of the | |
331 | GPIO range. | |
332 | ||
333 | The GPIO range of "chip a" starts from the GPIO base of 32 and actual | |
334 | pin range also starts from 32. However "chip b" has different starting | |
335 | offset for the GPIO range and pin range. The GPIO range of "chip b" starts | |
336 | from GPIO number 48, while the pin range of "chip b" starts from 64. | |
2744e8af | 337 | |
3c739ad0 CP |
338 | We can convert a gpio number to actual pin number using this "pin_base". |
339 | They are mapped in the global GPIO pin space at: | |
340 | ||
341 | chip a: | |
342 | - GPIO range : [32 .. 47] | |
343 | - pin range : [32 .. 47] | |
344 | chip b: | |
345 | - GPIO range : [48 .. 55] | |
346 | - pin range : [64 .. 71] | |
2744e8af LW |
347 | |
348 | When GPIO-specific functions in the pin control subsystem are called, these | |
336cdba0 | 349 | ranges will be used to look up the appropriate pin controller by inspecting |
2744e8af LW |
350 | and matching the pin to the pin ranges across all controllers. When a |
351 | pin controller handling the matching range is found, GPIO-specific functions | |
352 | will be called on that specific pin controller. | |
353 | ||
354 | For all functionalities dealing with pin biasing, pin muxing etc, the pin | |
355 | controller subsystem will subtract the range's .base offset from the passed | |
3c739ad0 CP |
356 | in gpio number, and add the ranges's .pin_base offset to retrive a pin number. |
357 | After that, the subsystem passes it on to the pin control driver, so the driver | |
358 | will get an pin number into its handled number range. Further it is also passed | |
2744e8af LW |
359 | the range ID value, so that the pin controller knows which range it should |
360 | deal with. | |
361 | ||
2744e8af LW |
362 | PINMUX interfaces |
363 | ================= | |
364 | ||
365 | These calls use the pinmux_* naming prefix. No other calls should use that | |
366 | prefix. | |
367 | ||
368 | ||
369 | What is pinmuxing? | |
370 | ================== | |
371 | ||
372 | PINMUX, also known as padmux, ballmux, alternate functions or mission modes | |
373 | is a way for chip vendors producing some kind of electrical packages to use | |
374 | a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive | |
375 | functions, depending on the application. By "application" in this context | |
376 | we usually mean a way of soldering or wiring the package into an electronic | |
377 | system, even though the framework makes it possible to also change the function | |
378 | at runtime. | |
379 | ||
380 | Here is an example of a PGA (Pin Grid Array) chip seen from underneath: | |
381 | ||
382 | A B C D E F G H | |
383 | +---+ | |
384 | 8 | o | o o o o o o o | |
385 | | | | |
386 | 7 | o | o o o o o o o | |
387 | | | | |
388 | 6 | o | o o o o o o o | |
389 | +---+---+ | |
390 | 5 | o | o | o o o o o o | |
391 | +---+---+ +---+ | |
392 | 4 o o o o o o | o | o | |
393 | | | | |
394 | 3 o o o o o o | o | o | |
395 | | | | |
396 | 2 o o o o o o | o | o | |
397 | +-------+-------+-------+---+---+ | |
398 | 1 | o o | o o | o o | o | o | | |
399 | +-------+-------+-------+---+---+ | |
400 | ||
401 | This is not tetris. The game to think of is chess. Not all PGA/BGA packages | |
402 | are chessboard-like, big ones have "holes" in some arrangement according to | |
403 | different design patterns, but we're using this as a simple example. Of the | |
404 | pins you see some will be taken by things like a few VCC and GND to feed power | |
405 | to the chip, and quite a few will be taken by large ports like an external | |
406 | memory interface. The remaining pins will often be subject to pin multiplexing. | |
407 | ||
408 | The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to | |
409 | its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using | |
410 | pinctrl_register_pins() and a suitable data set as shown earlier. | |
411 | ||
412 | In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port | |
413 | (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as | |
414 | some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can | |
415 | be used as an I2C port (these are just two pins: SCL, SDA). Needless to say, | |
416 | we cannot use the SPI port and I2C port at the same time. However in the inside | |
417 | of the package the silicon performing the SPI logic can alternatively be routed | |
418 | out on pins { G4, G3, G2, G1 }. | |
419 | ||
420 | On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something | |
421 | special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will | |
422 | consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or | |
423 | { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI | |
424 | port on pins { G4, G3, G2, G1 } of course. | |
425 | ||
426 | This way the silicon blocks present inside the chip can be multiplexed "muxed" | |
427 | out on different pin ranges. Often contemporary SoC (systems on chip) will | |
428 | contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to | |
429 | different pins by pinmux settings. | |
430 | ||
431 | Since general-purpose I/O pins (GPIO) are typically always in shortage, it is | |
432 | common to be able to use almost any pin as a GPIO pin if it is not currently | |
433 | in use by some other I/O port. | |
434 | ||
435 | ||
436 | Pinmux conventions | |
437 | ================== | |
438 | ||
439 | The purpose of the pinmux functionality in the pin controller subsystem is to | |
440 | abstract and provide pinmux settings to the devices you choose to instantiate | |
441 | in your machine configuration. It is inspired by the clk, GPIO and regulator | |
442 | subsystems, so devices will request their mux setting, but it's also possible | |
443 | to request a single pin for e.g. GPIO. | |
444 | ||
445 | Definitions: | |
446 | ||
447 | - FUNCTIONS can be switched in and out by a driver residing with the pin | |
448 | control subsystem in the drivers/pinctrl/* directory of the kernel. The | |
449 | pin control driver knows the possible functions. In the example above you can | |
450 | identify three pinmux functions, one for spi, one for i2c and one for mmc. | |
451 | ||
452 | - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array. | |
453 | In this case the array could be something like: { spi0, i2c0, mmc0 } | |
454 | for the three available functions. | |
455 | ||
456 | - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain | |
457 | function is *always* associated with a certain set of pin groups, could | |
458 | be just a single one, but could also be many. In the example above the | |
459 | function i2c is associated with the pins { A5, B5 }, enumerated as | |
460 | { 24, 25 } in the controller pin space. | |
461 | ||
462 | The Function spi is associated with pin groups { A8, A7, A6, A5 } | |
463 | and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and | |
464 | { 38, 46, 54, 62 } respectively. | |
465 | ||
466 | Group names must be unique per pin controller, no two groups on the same | |
467 | controller may have the same name. | |
468 | ||
469 | - The combination of a FUNCTION and a PIN GROUP determine a certain function | |
470 | for a certain set of pins. The knowledge of the functions and pin groups | |
471 | and their machine-specific particulars are kept inside the pinmux driver, | |
472 | from the outside only the enumerators are known, and the driver core can: | |
473 | ||
474 | - Request the name of a function with a certain selector (>= 0) | |
475 | - A list of groups associated with a certain function | |
476 | - Request that a certain group in that list to be activated for a certain | |
477 | function | |
478 | ||
479 | As already described above, pin groups are in turn self-descriptive, so | |
480 | the core will retrieve the actual pin range in a certain group from the | |
481 | driver. | |
482 | ||
483 | - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain | |
484 | device by the board file, device tree or similar machine setup configuration | |
485 | mechanism, similar to how regulators are connected to devices, usually by | |
486 | name. Defining a pin controller, function and group thus uniquely identify | |
487 | the set of pins to be used by a certain device. (If only one possible group | |
488 | of pins is available for the function, no group name need to be supplied - | |
489 | the core will simply select the first and only group available.) | |
490 | ||
491 | In the example case we can define that this particular machine shall | |
492 | use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function | |
493 | fi2c0 group gi2c0, on the primary pin controller, we get mappings | |
494 | like these: | |
495 | ||
496 | { | |
497 | {"map-spi0", spi0, pinctrl0, fspi0, gspi0}, | |
498 | {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0} | |
499 | } | |
500 | ||
1681f5ae SW |
501 | Every map must be assigned a state name, pin controller, device and |
502 | function. The group is not compulsory - if it is omitted the first group | |
503 | presented by the driver as applicable for the function will be selected, | |
504 | which is useful for simple cases. | |
2744e8af LW |
505 | |
506 | It is possible to map several groups to the same combination of device, | |
507 | pin controller and function. This is for cases where a certain function on | |
508 | a certain pin controller may use different sets of pins in different | |
509 | configurations. | |
510 | ||
511 | - PINS for a certain FUNCTION using a certain PIN GROUP on a certain | |
512 | PIN CONTROLLER are provided on a first-come first-serve basis, so if some | |
513 | other device mux setting or GPIO pin request has already taken your physical | |
514 | pin, you will be denied the use of it. To get (activate) a new setting, the | |
515 | old one has to be put (deactivated) first. | |
516 | ||
517 | Sometimes the documentation and hardware registers will be oriented around | |
518 | pads (or "fingers") rather than pins - these are the soldering surfaces on the | |
519 | silicon inside the package, and may or may not match the actual number of | |
520 | pins/balls underneath the capsule. Pick some enumeration that makes sense to | |
521 | you. Define enumerators only for the pins you can control if that makes sense. | |
522 | ||
523 | Assumptions: | |
524 | ||
336cdba0 | 525 | We assume that the number of possible function maps to pin groups is limited by |
2744e8af LW |
526 | the hardware. I.e. we assume that there is no system where any function can be |
527 | mapped to any pin, like in a phone exchange. So the available pins groups for | |
528 | a certain function will be limited to a few choices (say up to eight or so), | |
529 | not hundreds or any amount of choices. This is the characteristic we have found | |
530 | by inspecting available pinmux hardware, and a necessary assumption since we | |
531 | expect pinmux drivers to present *all* possible function vs pin group mappings | |
532 | to the subsystem. | |
533 | ||
534 | ||
535 | Pinmux drivers | |
536 | ============== | |
537 | ||
538 | The pinmux core takes care of preventing conflicts on pins and calling | |
539 | the pin controller driver to execute different settings. | |
540 | ||
541 | It is the responsibility of the pinmux driver to impose further restrictions | |
542 | (say for example infer electronic limitations due to load etc) to determine | |
543 | whether or not the requested function can actually be allowed, and in case it | |
544 | is possible to perform the requested mux setting, poke the hardware so that | |
545 | this happens. | |
546 | ||
547 | Pinmux drivers are required to supply a few callback functions, some are | |
548 | optional. Usually the enable() and disable() functions are implemented, | |
549 | writing values into some certain registers to activate a certain mux setting | |
550 | for a certain pin. | |
551 | ||
552 | A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4 | |
553 | into some register named MUX to select a certain function with a certain | |
554 | group of pins would work something like this: | |
555 | ||
556 | #include <linux/pinctrl/pinctrl.h> | |
557 | #include <linux/pinctrl/pinmux.h> | |
558 | ||
559 | struct foo_group { | |
560 | const char *name; | |
561 | const unsigned int *pins; | |
562 | const unsigned num_pins; | |
563 | }; | |
564 | ||
565 | static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 }; | |
566 | static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 }; | |
567 | static const unsigned i2c0_pins[] = { 24, 25 }; | |
568 | static const unsigned mmc0_1_pins[] = { 56, 57 }; | |
569 | static const unsigned mmc0_2_pins[] = { 58, 59 }; | |
570 | static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 }; | |
571 | ||
572 | static const struct foo_group foo_groups[] = { | |
573 | { | |
574 | .name = "spi0_0_grp", | |
575 | .pins = spi0_0_pins, | |
576 | .num_pins = ARRAY_SIZE(spi0_0_pins), | |
577 | }, | |
578 | { | |
579 | .name = "spi0_1_grp", | |
580 | .pins = spi0_1_pins, | |
581 | .num_pins = ARRAY_SIZE(spi0_1_pins), | |
582 | }, | |
583 | { | |
584 | .name = "i2c0_grp", | |
585 | .pins = i2c0_pins, | |
586 | .num_pins = ARRAY_SIZE(i2c0_pins), | |
587 | }, | |
588 | { | |
589 | .name = "mmc0_1_grp", | |
590 | .pins = mmc0_1_pins, | |
591 | .num_pins = ARRAY_SIZE(mmc0_1_pins), | |
592 | }, | |
593 | { | |
594 | .name = "mmc0_2_grp", | |
595 | .pins = mmc0_2_pins, | |
596 | .num_pins = ARRAY_SIZE(mmc0_2_pins), | |
597 | }, | |
598 | { | |
599 | .name = "mmc0_3_grp", | |
600 | .pins = mmc0_3_pins, | |
601 | .num_pins = ARRAY_SIZE(mmc0_3_pins), | |
602 | }, | |
603 | }; | |
604 | ||
605 | ||
d1e90e9e | 606 | static int foo_get_groups_count(struct pinctrl_dev *pctldev) |
2744e8af | 607 | { |
d1e90e9e | 608 | return ARRAY_SIZE(foo_groups); |
2744e8af LW |
609 | } |
610 | ||
611 | static const char *foo_get_group_name(struct pinctrl_dev *pctldev, | |
612 | unsigned selector) | |
613 | { | |
614 | return foo_groups[selector].name; | |
615 | } | |
616 | ||
617 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
618 | unsigned ** const pins, | |
619 | unsigned * const num_pins) | |
620 | { | |
621 | *pins = (unsigned *) foo_groups[selector].pins; | |
622 | *num_pins = foo_groups[selector].num_pins; | |
623 | return 0; | |
624 | } | |
625 | ||
626 | static struct pinctrl_ops foo_pctrl_ops = { | |
d1e90e9e | 627 | .get_groups_count = foo_get_groups_count, |
2744e8af LW |
628 | .get_group_name = foo_get_group_name, |
629 | .get_group_pins = foo_get_group_pins, | |
630 | }; | |
631 | ||
632 | struct foo_pmx_func { | |
633 | const char *name; | |
634 | const char * const *groups; | |
635 | const unsigned num_groups; | |
636 | }; | |
637 | ||
eb181c35 | 638 | static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" }; |
2744e8af LW |
639 | static const char * const i2c0_groups[] = { "i2c0_grp" }; |
640 | static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", | |
641 | "mmc0_3_grp" }; | |
642 | ||
643 | static const struct foo_pmx_func foo_functions[] = { | |
644 | { | |
645 | .name = "spi0", | |
646 | .groups = spi0_groups, | |
647 | .num_groups = ARRAY_SIZE(spi0_groups), | |
648 | }, | |
649 | { | |
650 | .name = "i2c0", | |
651 | .groups = i2c0_groups, | |
652 | .num_groups = ARRAY_SIZE(i2c0_groups), | |
653 | }, | |
654 | { | |
655 | .name = "mmc0", | |
656 | .groups = mmc0_groups, | |
657 | .num_groups = ARRAY_SIZE(mmc0_groups), | |
658 | }, | |
659 | }; | |
660 | ||
d1e90e9e | 661 | int foo_get_functions_count(struct pinctrl_dev *pctldev) |
2744e8af | 662 | { |
d1e90e9e | 663 | return ARRAY_SIZE(foo_functions); |
2744e8af LW |
664 | } |
665 | ||
666 | const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) | |
667 | { | |
336cdba0 | 668 | return foo_functions[selector].name; |
2744e8af LW |
669 | } |
670 | ||
671 | static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
672 | const char * const **groups, | |
673 | unsigned * const num_groups) | |
674 | { | |
675 | *groups = foo_functions[selector].groups; | |
676 | *num_groups = foo_functions[selector].num_groups; | |
677 | return 0; | |
678 | } | |
679 | ||
680 | int foo_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
681 | unsigned group) | |
682 | { | |
336cdba0 | 683 | u8 regbit = (1 << selector + group); |
2744e8af LW |
684 | |
685 | writeb((readb(MUX)|regbit), MUX) | |
686 | return 0; | |
687 | } | |
688 | ||
336cdba0 | 689 | void foo_disable(struct pinctrl_dev *pctldev, unsigned selector, |
2744e8af LW |
690 | unsigned group) |
691 | { | |
336cdba0 | 692 | u8 regbit = (1 << selector + group); |
2744e8af LW |
693 | |
694 | writeb((readb(MUX) & ~(regbit)), MUX) | |
695 | return 0; | |
696 | } | |
697 | ||
698 | struct pinmux_ops foo_pmxops = { | |
d1e90e9e | 699 | .get_functions_count = foo_get_functions_count, |
2744e8af LW |
700 | .get_function_name = foo_get_fname, |
701 | .get_function_groups = foo_get_groups, | |
702 | .enable = foo_enable, | |
703 | .disable = foo_disable, | |
704 | }; | |
705 | ||
706 | /* Pinmux operations are handled by some pin controller */ | |
707 | static struct pinctrl_desc foo_desc = { | |
708 | ... | |
709 | .pctlops = &foo_pctrl_ops, | |
710 | .pmxops = &foo_pmxops, | |
711 | }; | |
712 | ||
713 | In the example activating muxing 0 and 1 at the same time setting bits | |
714 | 0 and 1, uses one pin in common so they would collide. | |
715 | ||
716 | The beauty of the pinmux subsystem is that since it keeps track of all | |
717 | pins and who is using them, it will already have denied an impossible | |
718 | request like that, so the driver does not need to worry about such | |
719 | things - when it gets a selector passed in, the pinmux subsystem makes | |
720 | sure no other device or GPIO assignment is already using the selected | |
721 | pins. Thus bits 0 and 1 in the control register will never be set at the | |
722 | same time. | |
723 | ||
724 | All the above functions are mandatory to implement for a pinmux driver. | |
725 | ||
726 | ||
e93bcee0 LW |
727 | Pin control interaction with the GPIO subsystem |
728 | =============================================== | |
2744e8af | 729 | |
e93bcee0 LW |
730 | The public pinmux API contains two functions named pinctrl_request_gpio() |
731 | and pinctrl_free_gpio(). These two functions shall *ONLY* be called from | |
542e704f | 732 | gpiolib-based drivers as part of their gpio_request() and |
e93bcee0 | 733 | gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output] |
542e704f LW |
734 | shall only be called from within respective gpio_direction_[input|output] |
735 | gpiolib implementation. | |
736 | ||
737 | NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be | |
e93bcee0 LW |
738 | controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have |
739 | that driver request proper muxing and other control for its pins. | |
542e704f | 740 | |
2744e8af LW |
741 | The function list could become long, especially if you can convert every |
742 | individual pin into a GPIO pin independent of any other pins, and then try | |
743 | the approach to define every pin as a function. | |
744 | ||
745 | In this case, the function array would become 64 entries for each GPIO | |
746 | setting and then the device functions. | |
747 | ||
e93bcee0 | 748 | For this reason there are two functions a pin control driver can implement |
542e704f LW |
749 | to enable only GPIO on an individual pin: .gpio_request_enable() and |
750 | .gpio_disable_free(). | |
2744e8af LW |
751 | |
752 | This function will pass in the affected GPIO range identified by the pin | |
753 | controller core, so you know which GPIO pins are being affected by the request | |
754 | operation. | |
755 | ||
542e704f LW |
756 | If your driver needs to have an indication from the framework of whether the |
757 | GPIO pin shall be used for input or output you can implement the | |
758 | .gpio_set_direction() function. As described this shall be called from the | |
759 | gpiolib driver and the affected GPIO range, pin offset and desired direction | |
760 | will be passed along to this function. | |
761 | ||
762 | Alternatively to using these special functions, it is fully allowed to use | |
e93bcee0 | 763 | named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to |
542e704f LW |
764 | obtain the function "gpioN" where "N" is the global GPIO pin number if no |
765 | special GPIO-handler is registered. | |
2744e8af LW |
766 | |
767 | ||
1e2082b5 | 768 | Board/machine configuration |
2744e8af LW |
769 | ================================== |
770 | ||
771 | Boards and machines define how a certain complete running system is put | |
772 | together, including how GPIOs and devices are muxed, how regulators are | |
773 | constrained and how the clock tree looks. Of course pinmux settings are also | |
774 | part of this. | |
775 | ||
1e2082b5 SW |
776 | A pin controller configuration for a machine looks pretty much like a simple |
777 | regulator configuration, so for the example array above we want to enable i2c | |
778 | and spi on the second function mapping: | |
2744e8af LW |
779 | |
780 | #include <linux/pinctrl/machine.h> | |
781 | ||
122dbe7e | 782 | static const struct pinctrl_map mapping[] __initconst = { |
2744e8af | 783 | { |
806d3143 | 784 | .dev_name = "foo-spi.0", |
110e4ec5 | 785 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 786 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 787 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 788 | .data.mux.function = "spi0", |
2744e8af LW |
789 | }, |
790 | { | |
806d3143 | 791 | .dev_name = "foo-i2c.0", |
110e4ec5 | 792 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 793 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 794 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 795 | .data.mux.function = "i2c0", |
2744e8af LW |
796 | }, |
797 | { | |
806d3143 | 798 | .dev_name = "foo-mmc.0", |
110e4ec5 | 799 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 800 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 801 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 802 | .data.mux.function = "mmc0", |
2744e8af LW |
803 | }, |
804 | }; | |
805 | ||
806 | The dev_name here matches to the unique device name that can be used to look | |
807 | up the device struct (just like with clockdev or regulators). The function name | |
808 | must match a function provided by the pinmux driver handling this pin range. | |
809 | ||
810 | As you can see we may have several pin controllers on the system and thus | |
811 | we need to specify which one of them that contain the functions we wish | |
9dfac4fd | 812 | to map. |
2744e8af LW |
813 | |
814 | You register this pinmux mapping to the pinmux subsystem by simply: | |
815 | ||
e93bcee0 | 816 | ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping)); |
2744e8af LW |
817 | |
818 | Since the above construct is pretty common there is a helper macro to make | |
51cd24ee | 819 | it even more compact which assumes you want to use pinctrl-foo and position |
2744e8af LW |
820 | 0 for mapping, for example: |
821 | ||
e93bcee0 | 822 | static struct pinctrl_map __initdata mapping[] = { |
1e2082b5 SW |
823 | PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"), |
824 | }; | |
825 | ||
826 | The mapping table may also contain pin configuration entries. It's common for | |
827 | each pin/group to have a number of configuration entries that affect it, so | |
828 | the table entries for configuration reference an array of config parameters | |
829 | and values. An example using the convenience macros is shown below: | |
830 | ||
831 | static unsigned long i2c_grp_configs[] = { | |
832 | FOO_PIN_DRIVEN, | |
833 | FOO_PIN_PULLUP, | |
834 | }; | |
835 | ||
836 | static unsigned long i2c_pin_configs[] = { | |
837 | FOO_OPEN_COLLECTOR, | |
838 | FOO_SLEW_RATE_SLOW, | |
839 | }; | |
840 | ||
841 | static struct pinctrl_map __initdata mapping[] = { | |
842 | PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"), | |
843 | PIN_MAP_MUX_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs), | |
844 | PIN_MAP_MUX_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs), | |
845 | PIN_MAP_MUX_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs), | |
846 | }; | |
847 | ||
848 | Finally, some devices expect the mapping table to contain certain specific | |
849 | named states. When running on hardware that doesn't need any pin controller | |
850 | configuration, the mapping table must still contain those named states, in | |
851 | order to explicitly indicate that the states were provided and intended to | |
852 | be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining | |
853 | a named state without causing any pin controller to be programmed: | |
854 | ||
855 | static struct pinctrl_map __initdata mapping[] = { | |
856 | PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT), | |
2744e8af LW |
857 | }; |
858 | ||
859 | ||
860 | Complex mappings | |
861 | ================ | |
862 | ||
863 | As it is possible to map a function to different groups of pins an optional | |
864 | .group can be specified like this: | |
865 | ||
866 | ... | |
867 | { | |
806d3143 | 868 | .dev_name = "foo-spi.0", |
2744e8af | 869 | .name = "spi0-pos-A", |
1e2082b5 | 870 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 871 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
872 | .function = "spi0", |
873 | .group = "spi0_0_grp", | |
2744e8af LW |
874 | }, |
875 | { | |
806d3143 | 876 | .dev_name = "foo-spi.0", |
2744e8af | 877 | .name = "spi0-pos-B", |
1e2082b5 | 878 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 879 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
880 | .function = "spi0", |
881 | .group = "spi0_1_grp", | |
2744e8af LW |
882 | }, |
883 | ... | |
884 | ||
885 | This example mapping is used to switch between two positions for spi0 at | |
886 | runtime, as described further below under the heading "Runtime pinmuxing". | |
887 | ||
6e5e959d SW |
888 | Further it is possible for one named state to affect the muxing of several |
889 | groups of pins, say for example in the mmc0 example above, where you can | |
2744e8af LW |
890 | additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all |
891 | three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the | |
892 | case), we define a mapping like this: | |
893 | ||
894 | ... | |
895 | { | |
806d3143 | 896 | .dev_name = "foo-mmc.0", |
f54367f9 | 897 | .name = "2bit" |
1e2082b5 | 898 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 899 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 900 | .function = "mmc0", |
336cdba0 | 901 | .group = "mmc0_1_grp", |
2744e8af LW |
902 | }, |
903 | { | |
806d3143 | 904 | .dev_name = "foo-mmc.0", |
f54367f9 | 905 | .name = "4bit" |
1e2082b5 | 906 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 907 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 908 | .function = "mmc0", |
336cdba0 | 909 | .group = "mmc0_1_grp", |
2744e8af LW |
910 | }, |
911 | { | |
806d3143 | 912 | .dev_name = "foo-mmc.0", |
f54367f9 | 913 | .name = "4bit" |
1e2082b5 | 914 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 915 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 916 | .function = "mmc0", |
336cdba0 | 917 | .group = "mmc0_2_grp", |
2744e8af LW |
918 | }, |
919 | { | |
806d3143 | 920 | .dev_name = "foo-mmc.0", |
f54367f9 | 921 | .name = "8bit" |
1e2082b5 | 922 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 923 | .ctrl_dev_name = "pinctrl-foo", |
6e5e959d | 924 | .function = "mmc0", |
336cdba0 | 925 | .group = "mmc0_1_grp", |
2744e8af LW |
926 | }, |
927 | { | |
806d3143 | 928 | .dev_name = "foo-mmc.0", |
f54367f9 | 929 | .name = "8bit" |
1e2082b5 | 930 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 931 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 932 | .function = "mmc0", |
336cdba0 | 933 | .group = "mmc0_2_grp", |
2744e8af LW |
934 | }, |
935 | { | |
806d3143 | 936 | .dev_name = "foo-mmc.0", |
f54367f9 | 937 | .name = "8bit" |
1e2082b5 | 938 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 939 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 940 | .function = "mmc0", |
336cdba0 | 941 | .group = "mmc0_3_grp", |
2744e8af LW |
942 | }, |
943 | ... | |
944 | ||
945 | The result of grabbing this mapping from the device with something like | |
946 | this (see next paragraph): | |
947 | ||
6d4ca1fb | 948 | p = devm_pinctrl_get(dev); |
6e5e959d SW |
949 | s = pinctrl_lookup_state(p, "8bit"); |
950 | ret = pinctrl_select_state(p, s); | |
951 | ||
952 | or more simply: | |
953 | ||
6d4ca1fb | 954 | p = devm_pinctrl_get_select(dev, "8bit"); |
2744e8af LW |
955 | |
956 | Will be that you activate all the three bottom records in the mapping at | |
6e5e959d | 957 | once. Since they share the same name, pin controller device, function and |
2744e8af LW |
958 | device, and since we allow multiple groups to match to a single device, they |
959 | all get selected, and they all get enabled and disable simultaneously by the | |
960 | pinmux core. | |
961 | ||
962 | ||
963 | Pinmux requests from drivers | |
964 | ============================ | |
965 | ||
e93bcee0 LW |
966 | Generally it is discouraged to let individual drivers get and enable pin |
967 | control. So if possible, handle the pin control in platform code or some other | |
968 | place where you have access to all the affected struct device * pointers. In | |
969 | some cases where a driver needs to e.g. switch between different mux mappings | |
970 | at runtime this is not possible. | |
2744e8af | 971 | |
e93bcee0 LW |
972 | A driver may request a certain control state to be activated, usually just the |
973 | default state like this: | |
2744e8af | 974 | |
28a8d14c | 975 | #include <linux/pinctrl/consumer.h> |
2744e8af LW |
976 | |
977 | struct foo_state { | |
e93bcee0 | 978 | struct pinctrl *p; |
6e5e959d | 979 | struct pinctrl_state *s; |
2744e8af LW |
980 | ... |
981 | }; | |
982 | ||
983 | foo_probe() | |
984 | { | |
6e5e959d SW |
985 | /* Allocate a state holder named "foo" etc */ |
986 | struct foo_state *foo = ...; | |
987 | ||
6d4ca1fb | 988 | foo->p = devm_pinctrl_get(&device); |
6e5e959d SW |
989 | if (IS_ERR(foo->p)) { |
990 | /* FIXME: clean up "foo" here */ | |
991 | return PTR_ERR(foo->p); | |
992 | } | |
2744e8af | 993 | |
6e5e959d SW |
994 | foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT); |
995 | if (IS_ERR(foo->s)) { | |
6e5e959d SW |
996 | /* FIXME: clean up "foo" here */ |
997 | return PTR_ERR(s); | |
998 | } | |
2744e8af | 999 | |
6e5e959d SW |
1000 | ret = pinctrl_select_state(foo->s); |
1001 | if (ret < 0) { | |
6e5e959d SW |
1002 | /* FIXME: clean up "foo" here */ |
1003 | return ret; | |
1004 | } | |
2744e8af LW |
1005 | } |
1006 | ||
6e5e959d | 1007 | This get/lookup/select/put sequence can just as well be handled by bus drivers |
2744e8af LW |
1008 | if you don't want each and every driver to handle it and you know the |
1009 | arrangement on your bus. | |
1010 | ||
6e5e959d SW |
1011 | The semantics of the pinctrl APIs are: |
1012 | ||
1013 | - pinctrl_get() is called in process context to obtain a handle to all pinctrl | |
1014 | information for a given client device. It will allocate a struct from the | |
1015 | kernel memory to hold the pinmux state. All mapping table parsing or similar | |
1016 | slow operations take place within this API. | |
2744e8af | 1017 | |
6d4ca1fb SW |
1018 | - devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put() |
1019 | to be called automatically on the retrieved pointer when the associated | |
1020 | device is removed. It is recommended to use this function over plain | |
1021 | pinctrl_get(). | |
1022 | ||
6e5e959d SW |
1023 | - pinctrl_lookup_state() is called in process context to obtain a handle to a |
1024 | specific state for a the client device. This operation may be slow too. | |
2744e8af | 1025 | |
6e5e959d SW |
1026 | - pinctrl_select_state() programs pin controller hardware according to the |
1027 | definition of the state as given by the mapping table. In theory this is a | |
1028 | fast-path operation, since it only involved blasting some register settings | |
1029 | into hardware. However, note that some pin controllers may have their | |
1030 | registers on a slow/IRQ-based bus, so client devices should not assume they | |
1031 | can call pinctrl_select_state() from non-blocking contexts. | |
2744e8af | 1032 | |
6e5e959d | 1033 | - pinctrl_put() frees all information associated with a pinctrl handle. |
2744e8af | 1034 | |
6d4ca1fb SW |
1035 | - devm_pinctrl_put() is a variant of pinctrl_put() that may be used to |
1036 | explicitly destroy a pinctrl object returned by devm_pinctrl_get(). | |
1037 | However, use of this function will be rare, due to the automatic cleanup | |
1038 | that will occur even without calling it. | |
1039 | ||
1040 | pinctrl_get() must be paired with a plain pinctrl_put(). | |
1041 | pinctrl_get() may not be paired with devm_pinctrl_put(). | |
1042 | devm_pinctrl_get() can optionally be paired with devm_pinctrl_put(). | |
1043 | devm_pinctrl_get() may not be paired with plain pinctrl_put(). | |
1044 | ||
e93bcee0 LW |
1045 | Usually the pin control core handled the get/put pair and call out to the |
1046 | device drivers bookkeeping operations, like checking available functions and | |
1047 | the associated pins, whereas the enable/disable pass on to the pin controller | |
2744e8af LW |
1048 | driver which takes care of activating and/or deactivating the mux setting by |
1049 | quickly poking some registers. | |
1050 | ||
6d4ca1fb SW |
1051 | The pins are allocated for your device when you issue the devm_pinctrl_get() |
1052 | call, after this you should be able to see this in the debugfs listing of all | |
1053 | pins. | |
2744e8af | 1054 | |
c05127c4 LW |
1055 | NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the |
1056 | requested pinctrl handles, for example if the pinctrl driver has not yet | |
1057 | registered. Thus make sure that the error path in your driver gracefully | |
1058 | cleans up and is ready to retry the probing later in the startup process. | |
1059 | ||
2744e8af | 1060 | |
e93bcee0 LW |
1061 | System pin control hogging |
1062 | ========================== | |
2744e8af | 1063 | |
1681f5ae | 1064 | Pin control map entries can be hogged by the core when the pin controller |
6e5e959d SW |
1065 | is registered. This means that the core will attempt to call pinctrl_get(), |
1066 | lookup_state() and select_state() on it immediately after the pin control | |
1067 | device has been registered. | |
2744e8af | 1068 | |
6e5e959d SW |
1069 | This occurs for mapping table entries where the client device name is equal |
1070 | to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT. | |
2744e8af LW |
1071 | |
1072 | { | |
806d3143 | 1073 | .dev_name = "pinctrl-foo", |
46919ae6 | 1074 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 1075 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1076 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1077 | .function = "power_func", |
2744e8af LW |
1078 | }, |
1079 | ||
1080 | Since it may be common to request the core to hog a few always-applicable | |
1081 | mux settings on the primary pin controller, there is a convenience macro for | |
1082 | this: | |
1083 | ||
1e2082b5 | 1084 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func") |
2744e8af LW |
1085 | |
1086 | This gives the exact same result as the above construction. | |
1087 | ||
1088 | ||
1089 | Runtime pinmuxing | |
1090 | ================= | |
1091 | ||
1092 | It is possible to mux a certain function in and out at runtime, say to move | |
1093 | an SPI port from one set of pins to another set of pins. Say for example for | |
1094 | spi0 in the example above, we expose two different groups of pins for the same | |
1095 | function, but with different named in the mapping as described under | |
6e5e959d SW |
1096 | "Advanced mapping" above. So that for an SPI device, we have two states named |
1097 | "pos-A" and "pos-B". | |
2744e8af LW |
1098 | |
1099 | This snippet first muxes the function in the pins defined by group A, enables | |
1100 | it, disables and releases it, and muxes it in on the pins defined by group B: | |
1101 | ||
28a8d14c LW |
1102 | #include <linux/pinctrl/consumer.h> |
1103 | ||
6d4ca1fb SW |
1104 | struct pinctrl *p; |
1105 | struct pinctrl_state *s1, *s2; | |
6e5e959d | 1106 | |
6d4ca1fb SW |
1107 | foo_probe() |
1108 | { | |
6e5e959d | 1109 | /* Setup */ |
6d4ca1fb | 1110 | p = devm_pinctrl_get(&device); |
6e5e959d SW |
1111 | if (IS_ERR(p)) |
1112 | ... | |
1113 | ||
1114 | s1 = pinctrl_lookup_state(foo->p, "pos-A"); | |
1115 | if (IS_ERR(s1)) | |
1116 | ... | |
1117 | ||
1118 | s2 = pinctrl_lookup_state(foo->p, "pos-B"); | |
1119 | if (IS_ERR(s2)) | |
1120 | ... | |
6d4ca1fb | 1121 | } |
2744e8af | 1122 | |
6d4ca1fb SW |
1123 | foo_switch() |
1124 | { | |
2744e8af | 1125 | /* Enable on position A */ |
6e5e959d SW |
1126 | ret = pinctrl_select_state(s1); |
1127 | if (ret < 0) | |
1128 | ... | |
2744e8af | 1129 | |
6e5e959d | 1130 | ... |
2744e8af LW |
1131 | |
1132 | /* Enable on position B */ | |
6e5e959d SW |
1133 | ret = pinctrl_select_state(s2); |
1134 | if (ret < 0) | |
1135 | ... | |
1136 | ||
2744e8af LW |
1137 | ... |
1138 | } | |
1139 | ||
1140 | The above has to be done from process context. |