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1 | Booting the Linux/ppc kernel without Open Firmware |
2 | -------------------------------------------------- | |
3 | ||
c125a183 DG |
4 | (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>, |
5 | IBM Corp. | |
6 | (c) 2005 Becky Bruce <becky.bruce at freescale.com>, | |
7 | Freescale Semiconductor, FSL SOC and 32-bit additions | |
28f9ec34 VW |
8 | (c) 2006 MontaVista Software, Inc. |
9 | Flash chip node definition | |
c125a183 | 10 | |
5e1e9ba6 SY |
11 | Table of Contents |
12 | ================= | |
13 | ||
14 | I - Introduction | |
15 | 1) Entry point for arch/powerpc | |
16 | 2) Board support | |
17 | ||
18 | II - The DT block format | |
19 | 1) Header | |
20 | 2) Device tree generalities | |
21 | 3) Device tree "structure" block | |
22 | 4) Device tree "strings" block | |
23 | ||
24 | III - Required content of the device tree | |
25 | 1) Note about cells and address representation | |
26 | 2) Note about "compatible" properties | |
27 | 3) Note about "name" properties | |
28 | 4) Note about node and property names and character set | |
29 | 5) Required nodes and properties | |
30 | a) The root node | |
31 | b) The /cpus node | |
32 | c) The /cpus/* nodes | |
33 | d) the /memory node(s) | |
34 | e) The /chosen node | |
35 | f) the /soc<SOCname> node | |
36 | ||
37 | IV - "dtc", the device tree compiler | |
38 | ||
39 | V - Recommendations for a bootloader | |
40 | ||
41 | VI - System-on-a-chip devices and nodes | |
42 | 1) Defining child nodes of an SOC | |
43 | 2) Representing devices without a current OF specification | |
44 | a) MDIO IO device | |
5e1e9ba6 | 45 | b) Gianfar-compatible ethernet nodes |
a4ecabab | 46 | c) PHY nodes |
5e1e9ba6 SY |
47 | d) Interrupt controllers |
48 | e) I2C | |
49 | f) Freescale SOC USB controllers | |
50 | g) Freescale SOC SEC Security Engines | |
51 | h) Board Control and Status (BCSR) | |
52 | i) Freescale QUICC Engine module (QE) | |
2099172d | 53 | j) CFI or JEDEC memory-mapped NOR flash |
3b824f85 | 54 | k) Global Utilities Block |
bc556ba9 TT |
55 | l) Freescale Communications Processor Module |
56 | m) Chipselect/Local Bus | |
57 | n) 4xx/Axon EMAC ethernet nodes | |
58 | o) Xilinx IP cores | |
c7d24a2d | 59 | p) Freescale Synchronous Serial Interface |
41abd68e | 60 | q) USB EHCI controllers |
a5edeccb | 61 | r) MDIO on GPIOs |
79c28acb | 62 | s) SPI busses |
5e1e9ba6 | 63 | |
f5412c49 DF |
64 | VII - Marvell Discovery mv64[345]6x System Controller chips |
65 | 1) The /system-controller node | |
66 | 2) Child nodes of /system-controller | |
67 | a) Marvell Discovery MDIO bus | |
68 | b) Marvell Discovery ethernet controller | |
69 | c) Marvell Discovery PHY nodes | |
70 | d) Marvell Discovery SDMA nodes | |
71 | e) Marvell Discovery BRG nodes | |
72 | f) Marvell Discovery CUNIT nodes | |
73 | g) Marvell Discovery MPSCROUTING nodes | |
74 | h) Marvell Discovery MPSCINTR nodes | |
75 | i) Marvell Discovery MPSC nodes | |
76 | j) Marvell Discovery Watch Dog Timer nodes | |
77 | k) Marvell Discovery I2C nodes | |
78 | l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes | |
79 | m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes | |
80 | n) Marvell Discovery GPP (General Purpose Pins) nodes | |
81 | o) Marvell Discovery PCI host bridge node | |
82 | p) Marvell Discovery CPU Error nodes | |
83 | q) Marvell Discovery SRAM Controller nodes | |
84 | r) Marvell Discovery PCI Error Handler nodes | |
85 | s) Marvell Discovery Memory Controller nodes | |
86 | ||
87 | VIII - Specifying interrupt information for devices | |
5e1e9ba6 SY |
88 | 1) interrupts property |
89 | 2) interrupt-parent property | |
90 | 3) OpenPIC Interrupt Controllers | |
91 | 4) ISA Interrupt Controllers | |
92 | ||
2dff4177 | 93 | IX - Specifying GPIO information for devices |
b7ce3415 AV |
94 | 1) gpios property |
95 | 2) gpio-controller nodes | |
96 | ||
2dff4177 SW |
97 | X - Specifying device power management information (sleep property) |
98 | ||
5e1e9ba6 SY |
99 | Appendix A - Sample SOC node for MPC8540 |
100 | ||
101 | ||
102 | Revision Information | |
103 | ==================== | |
104 | ||
c125a183 DG |
105 | May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet. |
106 | ||
107 | May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or | |
108 | clarifies the fact that a lot of things are | |
109 | optional, the kernel only requires a very | |
110 | small device tree, though it is encouraged | |
111 | to provide an as complete one as possible. | |
112 | ||
113 | May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM | |
114 | - Misc fixes | |
115 | - Define version 3 and new format version 16 | |
116 | for the DT block (version 16 needs kernel | |
117 | patches, will be fwd separately). | |
118 | String block now has a size, and full path | |
119 | is replaced by unit name for more | |
120 | compactness. | |
121 | linux,phandle is made optional, only nodes | |
122 | that are referenced by other nodes need it. | |
123 | "name" property is now automatically | |
124 | deduced from the unit name | |
125 | ||
126 | June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and | |
127 | OF_DT_END_NODE in structure definition. | |
128 | - Change version 16 format to always align | |
129 | property data to 4 bytes. Since tokens are | |
130 | already aligned, that means no specific | |
5d3f083d | 131 | required alignment between property size |
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132 | and property data. The old style variable |
133 | alignment would make it impossible to do | |
134 | "simple" insertion of properties using | |
5dd60166 | 135 | memmove (thanks Milton for |
c125a183 | 136 | noticing). Updated kernel patch as well |
5d3f083d | 137 | - Correct a few more alignment constraints |
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138 | - Add a chapter about the device-tree |
139 | compiler and the textural representation of | |
140 | the tree that can be "compiled" by dtc. | |
141 | ||
c125a183 DG |
142 | November 21, 2005: Rev 0.5 |
143 | - Additions/generalizations for 32-bit | |
144 | - Changed to reflect the new arch/powerpc | |
145 | structure | |
146 | - Added chapter VI | |
147 | ||
148 | ||
149 | ToDo: | |
150 | - Add some definitions of interrupt tree (simple/complex) | |
5dd60166 | 151 | - Add some definitions for PCI host bridges |
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152 | - Add some common address format examples |
153 | - Add definitions for standard properties and "compatible" | |
154 | names for cells that are not already defined by the existing | |
155 | OF spec. | |
156 | - Compare FSL SOC use of PCI to standard and make sure no new | |
157 | node definition required. | |
158 | - Add more information about node definitions for SOC devices | |
159 | that currently have no standard, like the FSL CPM. | |
160 | ||
161 | ||
162 | I - Introduction | |
163 | ================ | |
164 | ||
165 | During the recent development of the Linux/ppc64 kernel, and more | |
166 | specifically, the addition of new platform types outside of the old | |
167 | IBM pSeries/iSeries pair, it was decided to enforce some strict rules | |
168 | regarding the kernel entry and bootloader <-> kernel interfaces, in | |
169 | order to avoid the degeneration that had become the ppc32 kernel entry | |
170 | point and the way a new platform should be added to the kernel. The | |
171 | legacy iSeries platform breaks those rules as it predates this scheme, | |
172 | but no new board support will be accepted in the main tree that | |
173 | doesn't follows them properly. In addition, since the advent of the | |
174 | arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit | |
175 | platforms and 32-bit platforms which move into arch/powerpc will be | |
176 | required to use these rules as well. | |
177 | ||
178 | The main requirement that will be defined in more detail below is | |
179 | the presence of a device-tree whose format is defined after Open | |
180 | Firmware specification. However, in order to make life easier | |
181 | to embedded board vendors, the kernel doesn't require the device-tree | |
182 | to represent every device in the system and only requires some nodes | |
183 | and properties to be present. This will be described in detail in | |
184 | section III, but, for example, the kernel does not require you to | |
185 | create a node for every PCI device in the system. It is a requirement | |
186 | to have a node for PCI host bridges in order to provide interrupt | |
187 | routing informations and memory/IO ranges, among others. It is also | |
188 | recommended to define nodes for on chip devices and other busses that | |
189 | don't specifically fit in an existing OF specification. This creates a | |
190 | great flexibility in the way the kernel can then probe those and match | |
191 | drivers to device, without having to hard code all sorts of tables. It | |
192 | also makes it more flexible for board vendors to do minor hardware | |
193 | upgrades without significantly impacting the kernel code or cluttering | |
194 | it with special cases. | |
195 | ||
196 | ||
197 | 1) Entry point for arch/powerpc | |
198 | ------------------------------- | |
199 | ||
200 | There is one and one single entry point to the kernel, at the start | |
201 | of the kernel image. That entry point supports two calling | |
202 | conventions: | |
203 | ||
204 | a) Boot from Open Firmware. If your firmware is compatible | |
205 | with Open Firmware (IEEE 1275) or provides an OF compatible | |
206 | client interface API (support for "interpret" callback of | |
207 | forth words isn't required), you can enter the kernel with: | |
208 | ||
209 | r5 : OF callback pointer as defined by IEEE 1275 | |
5dd60166 | 210 | bindings to powerpc. Only the 32-bit client interface |
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211 | is currently supported |
212 | ||
213 | r3, r4 : address & length of an initrd if any or 0 | |
214 | ||
215 | The MMU is either on or off; the kernel will run the | |
216 | trampoline located in arch/powerpc/kernel/prom_init.c to | |
217 | extract the device-tree and other information from open | |
218 | firmware and build a flattened device-tree as described | |
219 | in b). prom_init() will then re-enter the kernel using | |
220 | the second method. This trampoline code runs in the | |
221 | context of the firmware, which is supposed to handle all | |
222 | exceptions during that time. | |
223 | ||
224 | b) Direct entry with a flattened device-tree block. This entry | |
225 | point is called by a) after the OF trampoline and can also be | |
226 | called directly by a bootloader that does not support the Open | |
227 | Firmware client interface. It is also used by "kexec" to | |
228 | implement "hot" booting of a new kernel from a previous | |
229 | running one. This method is what I will describe in more | |
230 | details in this document, as method a) is simply standard Open | |
231 | Firmware, and thus should be implemented according to the | |
232 | various standard documents defining it and its binding to the | |
233 | PowerPC platform. The entry point definition then becomes: | |
234 | ||
235 | r3 : physical pointer to the device-tree block | |
236 | (defined in chapter II) in RAM | |
237 | ||
238 | r4 : physical pointer to the kernel itself. This is | |
239 | used by the assembly code to properly disable the MMU | |
240 | in case you are entering the kernel with MMU enabled | |
241 | and a non-1:1 mapping. | |
242 | ||
2fe0ae78 | 243 | r5 : NULL (as to differentiate with method a) |
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244 | |
245 | Note about SMP entry: Either your firmware puts your other | |
246 | CPUs in some sleep loop or spin loop in ROM where you can get | |
247 | them out via a soft reset or some other means, in which case | |
248 | you don't need to care, or you'll have to enter the kernel | |
249 | with all CPUs. The way to do that with method b) will be | |
250 | described in a later revision of this document. | |
251 | ||
252 | ||
253 | 2) Board support | |
254 | ---------------- | |
255 | ||
256 | 64-bit kernels: | |
257 | ||
258 | Board supports (platforms) are not exclusive config options. An | |
259 | arbitrary set of board supports can be built in a single kernel | |
260 | image. The kernel will "know" what set of functions to use for a | |
261 | given platform based on the content of the device-tree. Thus, you | |
262 | should: | |
263 | ||
264 | a) add your platform support as a _boolean_ option in | |
265 | arch/powerpc/Kconfig, following the example of PPC_PSERIES, | |
266 | PPC_PMAC and PPC_MAPLE. The later is probably a good | |
267 | example of a board support to start from. | |
268 | ||
269 | b) create your main platform file as | |
270 | "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it | |
271 | to the Makefile under the condition of your CONFIG_ | |
272 | option. This file will define a structure of type "ppc_md" | |
273 | containing the various callbacks that the generic code will | |
274 | use to get to your platform specific code | |
275 | ||
276 | c) Add a reference to your "ppc_md" structure in the | |
277 | "machines" table in arch/powerpc/kernel/setup_64.c if you are | |
278 | a 64-bit platform. | |
279 | ||
280 | d) request and get assigned a platform number (see PLATFORM_* | |
b8b572e1 | 281 | constants in arch/powerpc/include/asm/processor.h |
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282 | |
283 | 32-bit embedded kernels: | |
284 | ||
285 | Currently, board support is essentially an exclusive config option. | |
286 | The kernel is configured for a single platform. Part of the reason | |
287 | for this is to keep kernels on embedded systems small and efficient; | |
288 | part of this is due to the fact the code is already that way. In the | |
289 | future, a kernel may support multiple platforms, but only if the | |
5dd60166 | 290 | platforms feature the same core architecture. A single kernel build |
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291 | cannot support both configurations with Book E and configurations |
292 | with classic Powerpc architectures. | |
293 | ||
294 | 32-bit embedded platforms that are moved into arch/powerpc using a | |
295 | flattened device tree should adopt the merged tree practice of | |
296 | setting ppc_md up dynamically, even though the kernel is currently | |
297 | built with support for only a single platform at a time. This allows | |
298 | unification of the setup code, and will make it easier to go to a | |
299 | multiple-platform-support model in the future. | |
300 | ||
301 | NOTE: I believe the above will be true once Ben's done with the merge | |
302 | of the boot sequences.... someone speak up if this is wrong! | |
303 | ||
304 | To add a 32-bit embedded platform support, follow the instructions | |
305 | for 64-bit platforms above, with the exception that the Kconfig | |
306 | option should be set up such that the kernel builds exclusively for | |
307 | the platform selected. The processor type for the platform should | |
308 | enable another config option to select the specific board | |
309 | supported. | |
310 | ||
5dd60166 | 311 | NOTE: If Ben doesn't merge the setup files, may need to change this to |
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312 | point to setup_32.c |
313 | ||
314 | ||
315 | I will describe later the boot process and various callbacks that | |
316 | your platform should implement. | |
317 | ||
318 | ||
319 | II - The DT block format | |
320 | ======================== | |
321 | ||
322 | ||
323 | This chapter defines the actual format of the flattened device-tree | |
324 | passed to the kernel. The actual content of it and kernel requirements | |
325 | are described later. You can find example of code manipulating that | |
326 | format in various places, including arch/powerpc/kernel/prom_init.c | |
327 | which will generate a flattened device-tree from the Open Firmware | |
328 | representation, or the fs2dt utility which is part of the kexec tools | |
329 | which will generate one from a filesystem representation. It is | |
330 | expected that a bootloader like uboot provides a bit more support, | |
331 | that will be discussed later as well. | |
332 | ||
333 | Note: The block has to be in main memory. It has to be accessible in | |
334 | both real mode and virtual mode with no mapping other than main | |
335 | memory. If you are writing a simple flash bootloader, it should copy | |
336 | the block to RAM before passing it to the kernel. | |
337 | ||
338 | ||
339 | 1) Header | |
340 | --------- | |
341 | ||
342 | The kernel is entered with r3 pointing to an area of memory that is | |
b8b572e1 | 343 | roughly described in arch/powerpc/include/asm/prom.h by the structure |
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344 | boot_param_header: |
345 | ||
346 | struct boot_param_header { | |
347 | u32 magic; /* magic word OF_DT_HEADER */ | |
348 | u32 totalsize; /* total size of DT block */ | |
349 | u32 off_dt_struct; /* offset to structure */ | |
350 | u32 off_dt_strings; /* offset to strings */ | |
351 | u32 off_mem_rsvmap; /* offset to memory reserve map | |
5dd60166 | 352 | */ |
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353 | u32 version; /* format version */ |
354 | u32 last_comp_version; /* last compatible version */ | |
355 | ||
356 | /* version 2 fields below */ | |
357 | u32 boot_cpuid_phys; /* Which physical CPU id we're | |
358 | booting on */ | |
359 | /* version 3 fields below */ | |
360 | u32 size_dt_strings; /* size of the strings block */ | |
0e0293c8 DG |
361 | |
362 | /* version 17 fields below */ | |
363 | u32 size_dt_struct; /* size of the DT structure block */ | |
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364 | }; |
365 | ||
366 | Along with the constants: | |
367 | ||
368 | /* Definitions used by the flattened device tree */ | |
369 | #define OF_DT_HEADER 0xd00dfeed /* 4: version, | |
370 | 4: total size */ | |
371 | #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name | |
5dd60166 | 372 | */ |
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373 | #define OF_DT_END_NODE 0x2 /* End node */ |
374 | #define OF_DT_PROP 0x3 /* Property: name off, | |
375 | size, content */ | |
376 | #define OF_DT_END 0x9 | |
377 | ||
378 | All values in this header are in big endian format, the various | |
379 | fields in this header are defined more precisely below. All | |
380 | "offset" values are in bytes from the start of the header; that is | |
381 | from the value of r3. | |
382 | ||
383 | - magic | |
384 | ||
385 | This is a magic value that "marks" the beginning of the | |
386 | device-tree block header. It contains the value 0xd00dfeed and is | |
387 | defined by the constant OF_DT_HEADER | |
388 | ||
389 | - totalsize | |
390 | ||
391 | This is the total size of the DT block including the header. The | |
392 | "DT" block should enclose all data structures defined in this | |
393 | chapter (who are pointed to by offsets in this header). That is, | |
394 | the device-tree structure, strings, and the memory reserve map. | |
395 | ||
396 | - off_dt_struct | |
397 | ||
398 | This is an offset from the beginning of the header to the start | |
399 | of the "structure" part the device tree. (see 2) device tree) | |
400 | ||
401 | - off_dt_strings | |
402 | ||
403 | This is an offset from the beginning of the header to the start | |
404 | of the "strings" part of the device-tree | |
405 | ||
406 | - off_mem_rsvmap | |
407 | ||
408 | This is an offset from the beginning of the header to the start | |
5dd60166 | 409 | of the reserved memory map. This map is a list of pairs of 64- |
c125a183 | 410 | bit integers. Each pair is a physical address and a size. The |
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411 | list is terminated by an entry of size 0. This map provides the |
412 | kernel with a list of physical memory areas that are "reserved" | |
413 | and thus not to be used for memory allocations, especially during | |
414 | early initialization. The kernel needs to allocate memory during | |
415 | boot for things like un-flattening the device-tree, allocating an | |
416 | MMU hash table, etc... Those allocations must be done in such a | |
417 | way to avoid overriding critical things like, on Open Firmware | |
418 | capable machines, the RTAS instance, or on some pSeries, the TCE | |
419 | tables used for the iommu. Typically, the reserve map should | |
420 | contain _at least_ this DT block itself (header,total_size). If | |
421 | you are passing an initrd to the kernel, you should reserve it as | |
422 | well. You do not need to reserve the kernel image itself. The map | |
5dd60166 | 423 | should be 64-bit aligned. |
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424 | |
425 | - version | |
426 | ||
427 | This is the version of this structure. Version 1 stops | |
428 | here. Version 2 adds an additional field boot_cpuid_phys. | |
429 | Version 3 adds the size of the strings block, allowing the kernel | |
430 | to reallocate it easily at boot and free up the unused flattened | |
431 | structure after expansion. Version 16 introduces a new more | |
432 | "compact" format for the tree itself that is however not backward | |
0e0293c8 DG |
433 | compatible. Version 17 adds an additional field, size_dt_struct, |
434 | allowing it to be reallocated or moved more easily (this is | |
435 | particularly useful for bootloaders which need to make | |
436 | adjustments to a device tree based on probed information). You | |
437 | should always generate a structure of the highest version defined | |
438 | at the time of your implementation. Currently that is version 17, | |
439 | unless you explicitly aim at being backward compatible. | |
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440 | |
441 | - last_comp_version | |
442 | ||
443 | Last compatible version. This indicates down to what version of | |
444 | the DT block you are backward compatible. For example, version 2 | |
445 | is backward compatible with version 1 (that is, a kernel build | |
446 | for version 1 will be able to boot with a version 2 format). You | |
447 | should put a 1 in this field if you generate a device tree of | |
0e0293c8 | 448 | version 1 to 3, or 16 if you generate a tree of version 16 or 17 |
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449 | using the new unit name format. |
450 | ||
451 | - boot_cpuid_phys | |
452 | ||
453 | This field only exist on version 2 headers. It indicate which | |
454 | physical CPU ID is calling the kernel entry point. This is used, | |
455 | among others, by kexec. If you are on an SMP system, this value | |
456 | should match the content of the "reg" property of the CPU node in | |
457 | the device-tree corresponding to the CPU calling the kernel entry | |
458 | point (see further chapters for more informations on the required | |
459 | device-tree contents) | |
460 | ||
0e0293c8 DG |
461 | - size_dt_strings |
462 | ||
463 | This field only exists on version 3 and later headers. It | |
464 | gives the size of the "strings" section of the device tree (which | |
465 | starts at the offset given by off_dt_strings). | |
466 | ||
467 | - size_dt_struct | |
468 | ||
469 | This field only exists on version 17 and later headers. It gives | |
470 | the size of the "structure" section of the device tree (which | |
471 | starts at the offset given by off_dt_struct). | |
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472 | |
473 | So the typical layout of a DT block (though the various parts don't | |
474 | need to be in that order) looks like this (addresses go from top to | |
475 | bottom): | |
476 | ||
477 | ||
478 | ------------------------------ | |
479 | r3 -> | struct boot_param_header | | |
480 | ------------------------------ | |
481 | | (alignment gap) (*) | | |
482 | ------------------------------ | |
483 | | memory reserve map | | |
484 | ------------------------------ | |
485 | | (alignment gap) | | |
486 | ------------------------------ | |
487 | | | | |
488 | | device-tree structure | | |
489 | | | | |
490 | ------------------------------ | |
491 | | (alignment gap) | | |
492 | ------------------------------ | |
493 | | | | |
494 | | device-tree strings | | |
495 | | | | |
496 | -----> ------------------------------ | |
497 | | | |
498 | | | |
499 | --- (r3 + totalsize) | |
500 | ||
501 | (*) The alignment gaps are not necessarily present; their presence | |
502 | and size are dependent on the various alignment requirements of | |
503 | the individual data blocks. | |
504 | ||
505 | ||
506 | 2) Device tree generalities | |
507 | --------------------------- | |
508 | ||
509 | This device-tree itself is separated in two different blocks, a | |
510 | structure block and a strings block. Both need to be aligned to a 4 | |
511 | byte boundary. | |
512 | ||
513 | First, let's quickly describe the device-tree concept before detailing | |
514 | the storage format. This chapter does _not_ describe the detail of the | |
515 | required types of nodes & properties for the kernel, this is done | |
516 | later in chapter III. | |
517 | ||
518 | The device-tree layout is strongly inherited from the definition of | |
519 | the Open Firmware IEEE 1275 device-tree. It's basically a tree of | |
520 | nodes, each node having two or more named properties. A property can | |
521 | have a value or not. | |
522 | ||
523 | It is a tree, so each node has one and only one parent except for the | |
524 | root node who has no parent. | |
525 | ||
526 | A node has 2 names. The actual node name is generally contained in a | |
527 | property of type "name" in the node property list whose value is a | |
528 | zero terminated string and is mandatory for version 1 to 3 of the | |
0e0293c8 | 529 | format definition (as it is in Open Firmware). Version 16 makes it |
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530 | optional as it can generate it from the unit name defined below. |
531 | ||
2fe0ae78 | 532 | There is also a "unit name" that is used to differentiate nodes with |
c125a183 | 533 | the same name at the same level, it is usually made of the node |
2fe0ae78 | 534 | names, the "@" sign, and a "unit address", which definition is |
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535 | specific to the bus type the node sits on. |
536 | ||
537 | The unit name doesn't exist as a property per-se but is included in | |
538 | the device-tree structure. It is typically used to represent "path" in | |
539 | the device-tree. More details about the actual format of these will be | |
540 | below. | |
541 | ||
542 | The kernel powerpc generic code does not make any formal use of the | |
543 | unit address (though some board support code may do) so the only real | |
544 | requirement here for the unit address is to ensure uniqueness of | |
545 | the node unit name at a given level of the tree. Nodes with no notion | |
546 | of address and no possible sibling of the same name (like /memory or | |
547 | /cpus) may omit the unit address in the context of this specification, | |
548 | or use the "@0" default unit address. The unit name is used to define | |
549 | a node "full path", which is the concatenation of all parent node | |
550 | unit names separated with "/". | |
551 | ||
552 | The root node doesn't have a defined name, and isn't required to have | |
553 | a name property either if you are using version 3 or earlier of the | |
554 | format. It also has no unit address (no @ symbol followed by a unit | |
555 | address). The root node unit name is thus an empty string. The full | |
556 | path to the root node is "/". | |
557 | ||
558 | Every node which actually represents an actual device (that is, a node | |
559 | which isn't only a virtual "container" for more nodes, like "/cpus" | |
560 | is) is also required to have a "device_type" property indicating the | |
561 | type of node . | |
562 | ||
563 | Finally, every node that can be referenced from a property in another | |
564 | node is required to have a "linux,phandle" property. Real open | |
565 | firmware implementations provide a unique "phandle" value for every | |
566 | node that the "prom_init()" trampoline code turns into | |
567 | "linux,phandle" properties. However, this is made optional if the | |
568 | flattened device tree is used directly. An example of a node | |
569 | referencing another node via "phandle" is when laying out the | |
570 | interrupt tree which will be described in a further version of this | |
571 | document. | |
572 | ||
5dd60166 | 573 | This "linux, phandle" property is a 32-bit value that uniquely |
c125a183 DG |
574 | identifies a node. You are free to use whatever values or system of |
575 | values, internal pointers, or whatever to generate these, the only | |
576 | requirement is that every node for which you provide that property has | |
577 | a unique value for it. | |
578 | ||
579 | Here is an example of a simple device-tree. In this example, an "o" | |
580 | designates a node followed by the node unit name. Properties are | |
581 | presented with their name followed by their content. "content" | |
582 | represents an ASCII string (zero terminated) value, while <content> | |
5dd60166 | 583 | represents a 32-bit hexadecimal value. The various nodes in this |
c125a183 DG |
584 | example will be discussed in a later chapter. At this point, it is |
585 | only meant to give you a idea of what a device-tree looks like. I have | |
586 | purposefully kept the "name" and "linux,phandle" properties which | |
587 | aren't necessary in order to give you a better idea of what the tree | |
588 | looks like in practice. | |
589 | ||
590 | / o device-tree | |
591 | |- name = "device-tree" | |
592 | |- model = "MyBoardName" | |
593 | |- compatible = "MyBoardFamilyName" | |
594 | |- #address-cells = <2> | |
595 | |- #size-cells = <2> | |
596 | |- linux,phandle = <0> | |
597 | | | |
598 | o cpus | |
599 | | | - name = "cpus" | |
600 | | | - linux,phandle = <1> | |
601 | | | - #address-cells = <1> | |
602 | | | - #size-cells = <0> | |
603 | | | | |
604 | | o PowerPC,970@0 | |
605 | | |- name = "PowerPC,970" | |
606 | | |- device_type = "cpu" | |
607 | | |- reg = <0> | |
608 | | |- clock-frequency = <5f5e1000> | |
32aed2a5 | 609 | | |- 64-bit |
c125a183 DG |
610 | | |- linux,phandle = <2> |
611 | | | |
612 | o memory@0 | |
613 | | |- name = "memory" | |
614 | | |- device_type = "memory" | |
615 | | |- reg = <00000000 00000000 00000000 20000000> | |
616 | | |- linux,phandle = <3> | |
617 | | | |
618 | o chosen | |
619 | |- name = "chosen" | |
620 | |- bootargs = "root=/dev/sda2" | |
c125a183 DG |
621 | |- linux,phandle = <4> |
622 | ||
623 | This tree is almost a minimal tree. It pretty much contains the | |
624 | minimal set of required nodes and properties to boot a linux kernel; | |
625 | that is, some basic model informations at the root, the CPUs, and the | |
626 | physical memory layout. It also includes misc information passed | |
627 | through /chosen, like in this example, the platform type (mandatory) | |
628 | and the kernel command line arguments (optional). | |
629 | ||
32aed2a5 | 630 | The /cpus/PowerPC,970@0/64-bit property is an example of a |
c125a183 DG |
631 | property without a value. All other properties have a value. The |
632 | significance of the #address-cells and #size-cells properties will be | |
633 | explained in chapter IV which defines precisely the required nodes and | |
634 | properties and their content. | |
635 | ||
636 | ||
637 | 3) Device tree "structure" block | |
638 | ||
639 | The structure of the device tree is a linearized tree structure. The | |
640 | "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE" | |
641 | ends that node definition. Child nodes are simply defined before | |
642 | "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32 | |
643 | bit value. The tree has to be "finished" with a OF_DT_END token | |
644 | ||
645 | Here's the basic structure of a single node: | |
646 | ||
647 | * token OF_DT_BEGIN_NODE (that is 0x00000001) | |
648 | * for version 1 to 3, this is the node full path as a zero | |
649 | terminated string, starting with "/". For version 16 and later, | |
650 | this is the node unit name only (or an empty string for the | |
651 | root node) | |
652 | * [align gap to next 4 bytes boundary] | |
653 | * for each property: | |
654 | * token OF_DT_PROP (that is 0x00000003) | |
5dd60166 DP |
655 | * 32-bit value of property value size in bytes (or 0 if no |
656 | value) | |
657 | * 32-bit value of offset in string block of property name | |
c125a183 DG |
658 | * property value data if any |
659 | * [align gap to next 4 bytes boundary] | |
660 | * [child nodes if any] | |
661 | * token OF_DT_END_NODE (that is 0x00000002) | |
662 | ||
5dd60166 | 663 | So the node content can be summarized as a start token, a full path, |
53cb4726 | 664 | a list of properties, a list of child nodes, and an end token. Every |
c125a183 DG |
665 | child node is a full node structure itself as defined above. |
666 | ||
eff2ebd2 DG |
667 | NOTE: The above definition requires that all property definitions for |
668 | a particular node MUST precede any subnode definitions for that node. | |
669 | Although the structure would not be ambiguous if properties and | |
670 | subnodes were intermingled, the kernel parser requires that the | |
671 | properties come first (up until at least 2.6.22). Any tools | |
672 | manipulating a flattened tree must take care to preserve this | |
673 | constraint. | |
674 | ||
53cb4726 | 675 | 4) Device tree "strings" block |
c125a183 DG |
676 | |
677 | In order to save space, property names, which are generally redundant, | |
678 | are stored separately in the "strings" block. This block is simply the | |
679 | whole bunch of zero terminated strings for all property names | |
680 | concatenated together. The device-tree property definitions in the | |
681 | structure block will contain offset values from the beginning of the | |
682 | strings block. | |
683 | ||
684 | ||
685 | III - Required content of the device tree | |
686 | ========================================= | |
687 | ||
688 | WARNING: All "linux,*" properties defined in this document apply only | |
689 | to a flattened device-tree. If your platform uses a real | |
690 | implementation of Open Firmware or an implementation compatible with | |
691 | the Open Firmware client interface, those properties will be created | |
692 | by the trampoline code in the kernel's prom_init() file. For example, | |
693 | that's where you'll have to add code to detect your board model and | |
a2ffd275 | 694 | set the platform number. However, when using the flattened device-tree |
c125a183 DG |
695 | entry point, there is no prom_init() pass, and thus you have to |
696 | provide those properties yourself. | |
697 | ||
698 | ||
699 | 1) Note about cells and address representation | |
700 | ---------------------------------------------- | |
701 | ||
702 | The general rule is documented in the various Open Firmware | |
5dd60166 | 703 | documentations. If you choose to describe a bus with the device-tree |
c125a183 DG |
704 | and there exist an OF bus binding, then you should follow the |
705 | specification. However, the kernel does not require every single | |
706 | device or bus to be described by the device tree. | |
707 | ||
708 | In general, the format of an address for a device is defined by the | |
709 | parent bus type, based on the #address-cells and #size-cells | |
5b14e5f9 | 710 | properties. Note that the parent's parent definitions of #address-cells |
d9195881 | 711 | and #size-cells are not inherited so every node with children must specify |
5b14e5f9 MG |
712 | them. The kernel requires the root node to have those properties defining |
713 | addresses format for devices directly mapped on the processor bus. | |
c125a183 DG |
714 | |
715 | Those 2 properties define 'cells' for representing an address and a | |
5dd60166 | 716 | size. A "cell" is a 32-bit number. For example, if both contain 2 |
c125a183 | 717 | like the example tree given above, then an address and a size are both |
5dd60166 | 718 | composed of 2 cells, and each is a 64-bit number (cells are |
c125a183 DG |
719 | concatenated and expected to be in big endian format). Another example |
720 | is the way Apple firmware defines them, with 2 cells for an address | |
721 | and one cell for a size. Most 32-bit implementations should define | |
722 | #address-cells and #size-cells to 1, which represents a 32-bit value. | |
723 | Some 32-bit processors allow for physical addresses greater than 32 | |
724 | bits; these processors should define #address-cells as 2. | |
725 | ||
726 | "reg" properties are always a tuple of the type "address size" where | |
727 | the number of cells of address and size is specified by the bus | |
728 | #address-cells and #size-cells. When a bus supports various address | |
729 | spaces and other flags relative to a given address allocation (like | |
730 | prefetchable, etc...) those flags are usually added to the top level | |
731 | bits of the physical address. For example, a PCI physical address is | |
732 | made of 3 cells, the bottom two containing the actual address itself | |
733 | while the top cell contains address space indication, flags, and pci | |
734 | bus & device numbers. | |
735 | ||
736 | For busses that support dynamic allocation, it's the accepted practice | |
737 | to then not provide the address in "reg" (keep it 0) though while | |
738 | providing a flag indicating the address is dynamically allocated, and | |
739 | then, to provide a separate "assigned-addresses" property that | |
740 | contains the fully allocated addresses. See the PCI OF bindings for | |
741 | details. | |
742 | ||
743 | In general, a simple bus with no address space bits and no dynamic | |
744 | allocation is preferred if it reflects your hardware, as the existing | |
745 | kernel address parsing functions will work out of the box. If you | |
746 | define a bus type with a more complex address format, including things | |
747 | like address space bits, you'll have to add a bus translator to the | |
748 | prom_parse.c file of the recent kernels for your bus type. | |
749 | ||
e1fd1865 SN |
750 | The "reg" property only defines addresses and sizes (if #size-cells is |
751 | non-0) within a given bus. In order to translate addresses upward | |
5dd60166 | 752 | (that is into parent bus addresses, and possibly into CPU physical |
c125a183 DG |
753 | addresses), all busses must contain a "ranges" property. If the |
754 | "ranges" property is missing at a given level, it's assumed that | |
e1fd1865 SN |
755 | translation isn't possible, i.e., the registers are not visible on the |
756 | parent bus. The format of the "ranges" property for a bus is a list | |
757 | of: | |
c125a183 DG |
758 | |
759 | bus address, parent bus address, size | |
760 | ||
761 | "bus address" is in the format of the bus this bus node is defining, | |
762 | that is, for a PCI bridge, it would be a PCI address. Thus, (bus | |
763 | address, size) defines a range of addresses for child devices. "parent | |
764 | bus address" is in the format of the parent bus of this bus. For | |
765 | example, for a PCI host controller, that would be a CPU address. For a | |
766 | PCI<->ISA bridge, that would be a PCI address. It defines the base | |
767 | address in the parent bus where the beginning of that range is mapped. | |
768 | ||
5dd60166 | 769 | For a new 64-bit powerpc board, I recommend either the 2/2 format or |
c125a183 | 770 | Apple's 2/1 format which is slightly more compact since sizes usually |
5dd60166 | 771 | fit in a single 32-bit word. New 32-bit powerpc boards should use a |
c125a183 DG |
772 | 1/1 format, unless the processor supports physical addresses greater |
773 | than 32-bits, in which case a 2/1 format is recommended. | |
774 | ||
e1fd1865 SN |
775 | Alternatively, the "ranges" property may be empty, indicating that the |
776 | registers are visible on the parent bus using an identity mapping | |
777 | translation. In other words, the parent bus address space is the same | |
778 | as the child bus address space. | |
c125a183 DG |
779 | |
780 | 2) Note about "compatible" properties | |
781 | ------------------------------------- | |
782 | ||
783 | These properties are optional, but recommended in devices and the root | |
784 | node. The format of a "compatible" property is a list of concatenated | |
785 | zero terminated strings. They allow a device to express its | |
786 | compatibility with a family of similar devices, in some cases, | |
787 | allowing a single driver to match against several devices regardless | |
788 | of their actual names. | |
789 | ||
790 | 3) Note about "name" properties | |
791 | ------------------------------- | |
792 | ||
793 | While earlier users of Open Firmware like OldWorld macintoshes tended | |
794 | to use the actual device name for the "name" property, it's nowadays | |
795 | considered a good practice to use a name that is closer to the device | |
796 | class (often equal to device_type). For example, nowadays, ethernet | |
797 | controllers are named "ethernet", an additional "model" property | |
798 | defining precisely the chip type/model, and "compatible" property | |
799 | defining the family in case a single driver can driver more than one | |
800 | of these chips. However, the kernel doesn't generally put any | |
801 | restriction on the "name" property; it is simply considered good | |
802 | practice to follow the standard and its evolutions as closely as | |
803 | possible. | |
804 | ||
805 | Note also that the new format version 16 makes the "name" property | |
806 | optional. If it's absent for a node, then the node's unit name is then | |
807 | used to reconstruct the name. That is, the part of the unit name | |
808 | before the "@" sign is used (or the entire unit name if no "@" sign | |
809 | is present). | |
810 | ||
811 | 4) Note about node and property names and character set | |
812 | ------------------------------------------------------- | |
813 | ||
a2ffd275 | 814 | While open firmware provides more flexible usage of 8859-1, this |
c125a183 DG |
815 | specification enforces more strict rules. Nodes and properties should |
816 | be comprised only of ASCII characters 'a' to 'z', '0' to | |
817 | '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally | |
818 | allow uppercase characters 'A' to 'Z' (property names should be | |
819 | lowercase. The fact that vendors like Apple don't respect this rule is | |
820 | irrelevant here). Additionally, node and property names should always | |
821 | begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node | |
822 | names). | |
823 | ||
824 | The maximum number of characters for both nodes and property names | |
825 | is 31. In the case of node names, this is only the leftmost part of | |
826 | a unit name (the pure "name" property), it doesn't include the unit | |
827 | address which can extend beyond that limit. | |
828 | ||
829 | ||
830 | 5) Required nodes and properties | |
831 | -------------------------------- | |
832 | These are all that are currently required. However, it is strongly | |
833 | recommended that you expose PCI host bridges as documented in the | |
834 | PCI binding to open firmware, and your interrupt tree as documented | |
835 | in OF interrupt tree specification. | |
836 | ||
837 | a) The root node | |
838 | ||
839 | The root node requires some properties to be present: | |
840 | ||
841 | - model : this is your board name/model | |
842 | - #address-cells : address representation for "root" devices | |
843 | - #size-cells: the size representation for "root" devices | |
e8222502 BH |
844 | - device_type : This property shouldn't be necessary. However, if |
845 | you decide to create a device_type for your root node, make sure it | |
846 | is _not_ "chrp" unless your platform is a pSeries or PAPR compliant | |
847 | one for 64-bit, or a CHRP-type machine for 32-bit as this will | |
848 | matched by the kernel this way. | |
c125a183 DG |
849 | |
850 | Additionally, some recommended properties are: | |
851 | ||
852 | - compatible : the board "family" generally finds its way here, | |
853 | for example, if you have 2 board models with a similar layout, | |
854 | that typically get driven by the same platform code in the | |
855 | kernel, you would use a different "model" property but put a | |
856 | value in "compatible". The kernel doesn't directly use that | |
143a42d1 | 857 | value but it is generally useful. |
c125a183 DG |
858 | |
859 | The root node is also generally where you add additional properties | |
860 | specific to your board like the serial number if any, that sort of | |
6c28f2c0 | 861 | thing. It is recommended that if you add any "custom" property whose |
c125a183 DG |
862 | name may clash with standard defined ones, you prefix them with your |
863 | vendor name and a comma. | |
864 | ||
865 | b) The /cpus node | |
866 | ||
867 | This node is the parent of all individual CPU nodes. It doesn't | |
868 | have any specific requirements, though it's generally good practice | |
869 | to have at least: | |
870 | ||
871 | #address-cells = <00000001> | |
872 | #size-cells = <00000000> | |
873 | ||
874 | This defines that the "address" for a CPU is a single cell, and has | |
875 | no meaningful size. This is not necessary but the kernel will assume | |
876 | that format when reading the "reg" properties of a CPU node, see | |
877 | below | |
878 | ||
879 | c) The /cpus/* nodes | |
880 | ||
881 | So under /cpus, you are supposed to create a node for every CPU on | |
882 | the machine. There is no specific restriction on the name of the | |
883 | CPU, though It's common practice to call it PowerPC,<name>. For | |
884 | example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX. | |
885 | ||
886 | Required properties: | |
887 | ||
888 | - device_type : has to be "cpu" | |
5dd60166 | 889 | - reg : This is the physical CPU number, it's a single 32-bit cell |
c125a183 DG |
890 | and is also used as-is as the unit number for constructing the |
891 | unit name in the full path. For example, with 2 CPUs, you would | |
892 | have the full path: | |
893 | /cpus/PowerPC,970FX@0 | |
894 | /cpus/PowerPC,970FX@1 | |
895 | (unit addresses do not require leading zeroes) | |
20474abd BH |
896 | - d-cache-block-size : one cell, L1 data cache block size in bytes (*) |
897 | - i-cache-block-size : one cell, L1 instruction cache block size in | |
c125a183 DG |
898 | bytes |
899 | - d-cache-size : one cell, size of L1 data cache in bytes | |
900 | - i-cache-size : one cell, size of L1 instruction cache in bytes | |
c125a183 | 901 | |
20474abd BH |
902 | (*) The cache "block" size is the size on which the cache management |
903 | instructions operate. Historically, this document used the cache | |
904 | "line" size here which is incorrect. The kernel will prefer the cache | |
905 | block size and will fallback to cache line size for backward | |
906 | compatibility. | |
907 | ||
c125a183 DG |
908 | Recommended properties: |
909 | ||
910 | - timebase-frequency : a cell indicating the frequency of the | |
911 | timebase in Hz. This is not directly used by the generic code, | |
912 | but you are welcome to copy/paste the pSeries code for setting | |
913 | the kernel timebase/decrementer calibration based on this | |
914 | value. | |
915 | - clock-frequency : a cell indicating the CPU core clock frequency | |
5dd60166 | 916 | in Hz. A new property will be defined for 64-bit values, but if |
c125a183 DG |
917 | your frequency is < 4Ghz, one cell is enough. Here as well as |
918 | for the above, the common code doesn't use that property, but | |
919 | you are welcome to re-use the pSeries or Maple one. A future | |
920 | kernel version might provide a common function for this. | |
20474abd BH |
921 | - d-cache-line-size : one cell, L1 data cache line size in bytes |
922 | if different from the block size | |
923 | - i-cache-line-size : one cell, L1 instruction cache line size in | |
924 | bytes if different from the block size | |
c125a183 DG |
925 | |
926 | You are welcome to add any property you find relevant to your board, | |
927 | like some information about the mechanism used to soft-reset the | |
928 | CPUs. For example, Apple puts the GPIO number for CPU soft reset | |
929 | lines in there as a "soft-reset" property since they start secondary | |
930 | CPUs by soft-resetting them. | |
931 | ||
932 | ||
933 | d) the /memory node(s) | |
934 | ||
935 | To define the physical memory layout of your board, you should | |
936 | create one or more memory node(s). You can either create a single | |
937 | node with all memory ranges in its reg property, or you can create | |
938 | several nodes, as you wish. The unit address (@ part) used for the | |
939 | full path is the address of the first range of memory defined by a | |
940 | given node. If you use a single memory node, this will typically be | |
941 | @0. | |
942 | ||
943 | Required properties: | |
944 | ||
945 | - device_type : has to be "memory" | |
946 | - reg : This property contains all the physical memory ranges of | |
947 | your board. It's a list of addresses/sizes concatenated | |
948 | together, with the number of cells of each defined by the | |
949 | #address-cells and #size-cells of the root node. For example, | |
6c28f2c0 | 950 | with both of these properties being 2 like in the example given |
c125a183 DG |
951 | earlier, a 970 based machine with 6Gb of RAM could typically |
952 | have a "reg" property here that looks like: | |
953 | ||
954 | 00000000 00000000 00000000 80000000 | |
955 | 00000001 00000000 00000001 00000000 | |
956 | ||
957 | That is a range starting at 0 of 0x80000000 bytes and a range | |
958 | starting at 0x100000000 and of 0x100000000 bytes. You can see | |
959 | that there is no memory covering the IO hole between 2Gb and | |
960 | 4Gb. Some vendors prefer splitting those ranges into smaller | |
961 | segments, but the kernel doesn't care. | |
962 | ||
963 | e) The /chosen node | |
964 | ||
965 | This node is a bit "special". Normally, that's where open firmware | |
966 | puts some variable environment information, like the arguments, or | |
d1bff9ed | 967 | the default input/output devices. |
c125a183 DG |
968 | |
969 | This specification makes a few of these mandatory, but also defines | |
970 | some linux-specific properties that would be normally constructed by | |
971 | the prom_init() trampoline when booting with an OF client interface, | |
972 | but that you have to provide yourself when using the flattened format. | |
973 | ||
c125a183 DG |
974 | Recommended properties: |
975 | ||
976 | - bootargs : This zero-terminated string is passed as the kernel | |
977 | command line | |
978 | - linux,stdout-path : This is the full path to your standard | |
979 | console device if any. Typically, if you have serial devices on | |
980 | your board, you may want to put the full path to the one set as | |
981 | the default console in the firmware here, for the kernel to pick | |
5d3f083d | 982 | it up as its own default console. If you look at the function |
c125a183 DG |
983 | set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see |
984 | that the kernel tries to find out the default console and has | |
985 | knowledge of various types like 8250 serial ports. You may want | |
986 | to extend this function to add your own. | |
c125a183 DG |
987 | |
988 | Note that u-boot creates and fills in the chosen node for platforms | |
989 | that use it. | |
990 | ||
d1bff9ed SY |
991 | (Note: a practice that is now obsolete was to include a property |
992 | under /chosen called interrupt-controller which had a phandle value | |
993 | that pointed to the main interrupt controller) | |
994 | ||
c125a183 DG |
995 | f) the /soc<SOCname> node |
996 | ||
997 | This node is used to represent a system-on-a-chip (SOC) and must be | |
998 | present if the processor is a SOC. The top-level soc node contains | |
999 | information that is global to all devices on the SOC. The node name | |
1000 | should contain a unit address for the SOC, which is the base address | |
1001 | of the memory-mapped register set for the SOC. The name of an soc | |
1002 | node should start with "soc", and the remainder of the name should | |
1003 | represent the part number for the soc. For example, the MPC8540's | |
1004 | soc node would be called "soc8540". | |
1005 | ||
1006 | Required properties: | |
1007 | ||
1008 | - device_type : Should be "soc" | |
1009 | - ranges : Should be defined as specified in 1) to describe the | |
1010 | translation of SOC addresses for memory mapped SOC registers. | |
7d4b95ae BB |
1011 | - bus-frequency: Contains the bus frequency for the SOC node. |
1012 | Typically, the value of this field is filled in by the boot | |
1013 | loader. | |
1014 | ||
c125a183 DG |
1015 | |
1016 | Recommended properties: | |
1017 | ||
1018 | - reg : This property defines the address and size of the | |
1019 | memory-mapped registers that are used for the SOC node itself. | |
1020 | It does not include the child device registers - these will be | |
1021 | defined inside each child node. The address specified in the | |
1022 | "reg" property should match the unit address of the SOC node. | |
1023 | - #address-cells : Address representation for "soc" devices. The | |
1024 | format of this field may vary depending on whether or not the | |
1025 | device registers are memory mapped. For memory mapped | |
1026 | registers, this field represents the number of cells needed to | |
1027 | represent the address of the registers. For SOCs that do not | |
1028 | use MMIO, a special address format should be defined that | |
1029 | contains enough cells to represent the required information. | |
1030 | See 1) above for more details on defining #address-cells. | |
1031 | - #size-cells : Size representation for "soc" devices | |
1032 | - #interrupt-cells : Defines the width of cells used to represent | |
1033 | interrupts. Typically this value is <2>, which includes a | |
1034 | 32-bit number that represents the interrupt number, and a | |
1035 | 32-bit number that represents the interrupt sense and level. | |
1036 | This field is only needed if the SOC contains an interrupt | |
1037 | controller. | |
1038 | ||
1039 | The SOC node may contain child nodes for each SOC device that the | |
1040 | platform uses. Nodes should not be created for devices which exist | |
1041 | on the SOC but are not used by a particular platform. See chapter VI | |
5dd60166 | 1042 | for more information on how to specify devices that are part of a SOC. |
c125a183 DG |
1043 | |
1044 | Example SOC node for the MPC8540: | |
1045 | ||
1046 | soc8540@e0000000 { | |
1047 | #address-cells = <1>; | |
1048 | #size-cells = <1>; | |
1049 | #interrupt-cells = <2>; | |
1050 | device_type = "soc"; | |
1051 | ranges = <00000000 e0000000 00100000> | |
1052 | reg = <e0000000 00003000>; | |
7d4b95ae | 1053 | bus-frequency = <0>; |
c125a183 DG |
1054 | } |
1055 | ||
1056 | ||
1057 | ||
1058 | IV - "dtc", the device tree compiler | |
1059 | ==================================== | |
1060 | ||
1061 | ||
1062 | dtc source code can be found at | |
1063 | <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz> | |
1064 | ||
1065 | WARNING: This version is still in early development stage; the | |
1066 | resulting device-tree "blobs" have not yet been validated with the | |
1067 | kernel. The current generated bloc lacks a useful reserve map (it will | |
1068 | be fixed to generate an empty one, it's up to the bootloader to fill | |
1069 | it up) among others. The error handling needs work, bugs are lurking, | |
1070 | etc... | |
1071 | ||
1072 | dtc basically takes a device-tree in a given format and outputs a | |
1073 | device-tree in another format. The currently supported formats are: | |
1074 | ||
1075 | Input formats: | |
1076 | ------------- | |
1077 | ||
1078 | - "dtb": "blob" format, that is a flattened device-tree block | |
1079 | with | |
1080 | header all in a binary blob. | |
1081 | - "dts": "source" format. This is a text file containing a | |
1082 | "source" for a device-tree. The format is defined later in this | |
1083 | chapter. | |
1084 | - "fs" format. This is a representation equivalent to the | |
1085 | output of /proc/device-tree, that is nodes are directories and | |
1086 | properties are files | |
1087 | ||
1088 | Output formats: | |
1089 | --------------- | |
1090 | ||
1091 | - "dtb": "blob" format | |
1092 | - "dts": "source" format | |
1093 | - "asm": assembly language file. This is a file that can be | |
1094 | sourced by gas to generate a device-tree "blob". That file can | |
1095 | then simply be added to your Makefile. Additionally, the | |
6c28f2c0 | 1096 | assembly file exports some symbols that can be used. |
c125a183 DG |
1097 | |
1098 | ||
1099 | The syntax of the dtc tool is | |
1100 | ||
1101 | dtc [-I <input-format>] [-O <output-format>] | |
1102 | [-o output-filename] [-V output_version] input_filename | |
1103 | ||
1104 | ||
5dd60166 | 1105 | The "output_version" defines what version of the "blob" format will be |
c125a183 DG |
1106 | generated. Supported versions are 1,2,3 and 16. The default is |
1107 | currently version 3 but that may change in the future to version 16. | |
1108 | ||
1109 | Additionally, dtc performs various sanity checks on the tree, like the | |
6c28f2c0 | 1110 | uniqueness of linux, phandle properties, validity of strings, etc... |
c125a183 DG |
1111 | |
1112 | The format of the .dts "source" file is "C" like, supports C and C++ | |
6c28f2c0 | 1113 | style comments. |
c125a183 DG |
1114 | |
1115 | / { | |
1116 | } | |
1117 | ||
1118 | The above is the "device-tree" definition. It's the only statement | |
1119 | supported currently at the toplevel. | |
1120 | ||
1121 | / { | |
1122 | property1 = "string_value"; /* define a property containing a 0 | |
1123 | * terminated string | |
1124 | */ | |
1125 | ||
1126 | property2 = <1234abcd>; /* define a property containing a | |
5dd60166 | 1127 | * numerical 32-bit value (hexadecimal) |
c125a183 DG |
1128 | */ |
1129 | ||
1130 | property3 = <12345678 12345678 deadbeef>; | |
1131 | /* define a property containing 3 | |
5dd60166 | 1132 | * numerical 32-bit values (cells) in |
c125a183 DG |
1133 | * hexadecimal |
1134 | */ | |
1135 | property4 = [0a 0b 0c 0d de ea ad be ef]; | |
1136 | /* define a property whose content is | |
1137 | * an arbitrary array of bytes | |
1138 | */ | |
1139 | ||
1140 | childnode@addresss { /* define a child node named "childnode" | |
1141 | * whose unit name is "childnode at | |
1142 | * address" | |
1143 | */ | |
1144 | ||
1145 | childprop = "hello\n"; /* define a property "childprop" of | |
1146 | * childnode (in this case, a string) | |
1147 | */ | |
1148 | }; | |
1149 | }; | |
1150 | ||
1151 | Nodes can contain other nodes etc... thus defining the hierarchical | |
1152 | structure of the tree. | |
1153 | ||
1154 | Strings support common escape sequences from C: "\n", "\t", "\r", | |
1155 | "\(octal value)", "\x(hex value)". | |
1156 | ||
1157 | It is also suggested that you pipe your source file through cpp (gcc | |
1158 | preprocessor) so you can use #include's, #define for constants, etc... | |
1159 | ||
1160 | Finally, various options are planned but not yet implemented, like | |
1161 | automatic generation of phandles, labels (exported to the asm file so | |
1162 | you can point to a property content and change it easily from whatever | |
1163 | you link the device-tree with), label or path instead of numeric value | |
1164 | in some cells to "point" to a node (replaced by a phandle at compile | |
1165 | time), export of reserve map address to the asm file, ability to | |
1166 | specify reserve map content at compile time, etc... | |
1167 | ||
1168 | We may provide a .h include file with common definitions of that | |
1169 | proves useful for some properties (like building PCI properties or | |
1170 | interrupt maps) though it may be better to add a notion of struct | |
1171 | definitions to the compiler... | |
1172 | ||
1173 | ||
1174 | V - Recommendations for a bootloader | |
1175 | ==================================== | |
1176 | ||
1177 | ||
1178 | Here are some various ideas/recommendations that have been proposed | |
1179 | while all this has been defined and implemented. | |
1180 | ||
1181 | - The bootloader may want to be able to use the device-tree itself | |
1182 | and may want to manipulate it (to add/edit some properties, | |
1183 | like physical memory size or kernel arguments). At this point, 2 | |
1184 | choices can be made. Either the bootloader works directly on the | |
1185 | flattened format, or the bootloader has its own internal tree | |
1186 | representation with pointers (similar to the kernel one) and | |
1187 | re-flattens the tree when booting the kernel. The former is a bit | |
1188 | more difficult to edit/modify, the later requires probably a bit | |
1189 | more code to handle the tree structure. Note that the structure | |
1190 | format has been designed so it's relatively easy to "insert" | |
1191 | properties or nodes or delete them by just memmoving things | |
1192 | around. It contains no internal offsets or pointers for this | |
1193 | purpose. | |
1194 | ||
d6bc8ac9 | 1195 | - An example of code for iterating nodes & retrieving properties |
c125a183 DG |
1196 | directly from the flattened tree format can be found in the kernel |
1197 | file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function, | |
d6bc8ac9 | 1198 | its usage in early_init_devtree(), and the corresponding various |
c125a183 DG |
1199 | early_init_dt_scan_*() callbacks. That code can be re-used in a |
1200 | GPL bootloader, and as the author of that code, I would be happy | |
5dd60166 | 1201 | to discuss possible free licensing to any vendor who wishes to |
c125a183 DG |
1202 | integrate all or part of this code into a non-GPL bootloader. |
1203 | ||
1204 | ||
1205 | ||
1206 | VI - System-on-a-chip devices and nodes | |
1207 | ======================================= | |
1208 | ||
1209 | Many companies are now starting to develop system-on-a-chip | |
5dd60166 | 1210 | processors, where the processor core (CPU) and many peripheral devices |
c125a183 DG |
1211 | exist on a single piece of silicon. For these SOCs, an SOC node |
1212 | should be used that defines child nodes for the devices that make | |
1213 | up the SOC. While platforms are not required to use this model in | |
1214 | order to boot the kernel, it is highly encouraged that all SOC | |
1215 | implementations define as complete a flat-device-tree as possible to | |
1216 | describe the devices on the SOC. This will allow for the | |
1217 | genericization of much of the kernel code. | |
1218 | ||
1219 | ||
1220 | 1) Defining child nodes of an SOC | |
1221 | --------------------------------- | |
1222 | ||
1223 | Each device that is part of an SOC may have its own node entry inside | |
1224 | the SOC node. For each device that is included in the SOC, the unit | |
1225 | address property represents the address offset for this device's | |
1226 | memory-mapped registers in the parent's address space. The parent's | |
1227 | address space is defined by the "ranges" property in the top-level soc | |
1228 | node. The "reg" property for each node that exists directly under the | |
1229 | SOC node should contain the address mapping from the child address space | |
1230 | to the parent SOC address space and the size of the device's | |
1231 | memory-mapped register file. | |
1232 | ||
1233 | For many devices that may exist inside an SOC, there are predefined | |
1234 | specifications for the format of the device tree node. All SOC child | |
1235 | nodes should follow these specifications, except where noted in this | |
1236 | document. | |
1237 | ||
1238 | See appendix A for an example partial SOC node definition for the | |
1239 | MPC8540. | |
1240 | ||
1241 | ||
27565903 | 1242 | 2) Representing devices without a current OF specification |
c125a183 DG |
1243 | ---------------------------------------------------------- |
1244 | ||
1245 | Currently, there are many devices on SOCs that do not have a standard | |
1246 | representation pre-defined as part of the open firmware | |
1247 | specifications, mainly because the boards that contain these SOCs are | |
1248 | not currently booted using open firmware. This section contains | |
1249 | descriptions for the SOC devices for which new nodes have been | |
1250 | defined; this list will expand as more and more SOC-containing | |
1251 | platforms are moved over to use the flattened-device-tree model. | |
1252 | ||
d0fc2eaa | 1253 | a) PHY nodes |
c125a183 DG |
1254 | |
1255 | Required properties: | |
1256 | ||
1257 | - device_type : Should be "ethernet-phy" | |
1258 | - interrupts : <a b> where a is the interrupt number and b is a | |
1259 | field that represents an encoding of the sense and level | |
1260 | information for the interrupt. This should be encoded based on | |
1261 | the information in section 2) depending on the type of interrupt | |
1262 | controller you have. | |
1263 | - interrupt-parent : the phandle for the interrupt controller that | |
1264 | services interrupts for this device. | |
1265 | - reg : The ID number for the phy, usually a small integer | |
1266 | - linux,phandle : phandle for this node; likely referenced by an | |
1267 | ethernet controller node. | |
1268 | ||
1269 | ||
1270 | Example: | |
1271 | ||
1272 | ethernet-phy@0 { | |
1273 | linux,phandle = <2452000> | |
1274 | interrupt-parent = <40000>; | |
1275 | interrupts = <35 1>; | |
1276 | reg = <0>; | |
1277 | device_type = "ethernet-phy"; | |
1278 | }; | |
1279 | ||
1280 | ||
d0fc2eaa | 1281 | b) Interrupt controllers |
c125a183 DG |
1282 | |
1283 | Some SOC devices contain interrupt controllers that are different | |
1284 | from the standard Open PIC specification. The SOC device nodes for | |
1285 | these types of controllers should be specified just like a standard | |
1286 | OpenPIC controller. Sense and level information should be encoded | |
1287 | as specified in section 2) of this chapter for each device that | |
1288 | specifies an interrupt. | |
1289 | ||
1290 | Example : | |
1291 | ||
1292 | pic@40000 { | |
1293 | linux,phandle = <40000>; | |
c125a183 DG |
1294 | interrupt-controller; |
1295 | #address-cells = <0>; | |
1296 | reg = <40000 40000>; | |
c125a183 DG |
1297 | compatible = "chrp,open-pic"; |
1298 | device_type = "open-pic"; | |
c125a183 DG |
1299 | }; |
1300 | ||
d0fc2eaa | 1301 | c) CFI or JEDEC memory-mapped NOR flash |
28f9ec34 VW |
1302 | |
1303 | Flash chips (Memory Technology Devices) are often used for solid state | |
1304 | file systems on embedded devices. | |
1305 | ||
2099172d DG |
1306 | - compatible : should contain the specific model of flash chip(s) |
1307 | used, if known, followed by either "cfi-flash" or "jedec-flash" | |
1308 | - reg : Address range of the flash chip | |
1309 | - bank-width : Width (in bytes) of the flash bank. Equal to the | |
1310 | device width times the number of interleaved chips. | |
1311 | - device-width : (optional) Width of a single flash chip. If | |
1312 | omitted, assumed to be equal to 'bank-width'. | |
1313 | - #address-cells, #size-cells : Must be present if the flash has | |
1314 | sub-nodes representing partitions (see below). In this case | |
1315 | both #address-cells and #size-cells must be equal to 1. | |
1316 | ||
1317 | For JEDEC compatible devices, the following additional properties | |
1318 | are defined: | |
1319 | ||
1320 | - vendor-id : Contains the flash chip's vendor id (1 byte). | |
1321 | - device-id : Contains the flash chip's device id (1 byte). | |
1322 | ||
1323 | In addition to the information on the flash bank itself, the | |
1324 | device tree may optionally contain additional information | |
1325 | describing partitions of the flash address space. This can be | |
1326 | used on platforms which have strong conventions about which | |
1327 | portions of the flash are used for what purposes, but which don't | |
1328 | use an on-flash partition table such as RedBoot. | |
1329 | ||
1330 | Each partition is represented as a sub-node of the flash device. | |
1331 | Each node's name represents the name of the corresponding | |
1332 | partition of the flash device. | |
1333 | ||
1334 | Flash partitions | |
1335 | - reg : The partition's offset and size within the flash bank. | |
1336 | - label : (optional) The label / name for this flash partition. | |
1337 | If omitted, the label is taken from the node name (excluding | |
1338 | the unit address). | |
1339 | - read-only : (optional) This parameter, if present, is a hint to | |
1340 | Linux that this flash partition should only be mounted | |
1341 | read-only. This is usually used for flash partitions | |
1342 | containing early-boot firmware images or data which should not | |
1343 | be clobbered. | |
28f9ec34 | 1344 | |
2099172d | 1345 | Example: |
28f9ec34 | 1346 | |
2099172d DG |
1347 | flash@ff000000 { |
1348 | compatible = "amd,am29lv128ml", "cfi-flash"; | |
1349 | reg = <ff000000 01000000>; | |
1350 | bank-width = <4>; | |
1351 | device-width = <1>; | |
1352 | #address-cells = <1>; | |
1353 | #size-cells = <1>; | |
1354 | fs@0 { | |
1355 | label = "fs"; | |
1356 | reg = <0 f80000>; | |
1357 | }; | |
1358 | firmware@f80000 { | |
1359 | label ="firmware"; | |
1360 | reg = <f80000 80000>; | |
1361 | read-only; | |
1362 | }; | |
1363 | }; | |
28f9ec34 | 1364 | |
d0fc2eaa | 1365 | d) 4xx/Axon EMAC ethernet nodes |
1d3bb996 DG |
1366 | |
1367 | The EMAC ethernet controller in IBM and AMCC 4xx chips, and also | |
1368 | the Axon bridge. To operate this needs to interact with a ths | |
1369 | special McMAL DMA controller, and sometimes an RGMII or ZMII | |
1370 | interface. In addition to the nodes and properties described | |
1371 | below, the node for the OPB bus on which the EMAC sits must have a | |
1372 | correct clock-frequency property. | |
1373 | ||
1374 | i) The EMAC node itself | |
1375 | ||
1376 | Required properties: | |
1377 | - device_type : "network" | |
1378 | ||
1379 | - compatible : compatible list, contains 2 entries, first is | |
1380 | "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, | |
1381 | 405gp, Axon) and second is either "ibm,emac" or | |
1382 | "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", | |
1383 | "ibm,emac4" | |
1384 | - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> | |
1385 | - interrupt-parent : optional, if needed for interrupt mapping | |
1386 | - reg : <registers mapping> | |
1387 | - local-mac-address : 6 bytes, MAC address | |
1388 | - mal-device : phandle of the associated McMAL node | |
1389 | - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated | |
1390 | with this EMAC | |
1391 | - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated | |
1392 | with this EMAC | |
1393 | - cell-index : 1 cell, hardware index of the EMAC cell on a given | |
1394 | ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on | |
1395 | each Axon chip) | |
1396 | - max-frame-size : 1 cell, maximum frame size supported in bytes | |
1397 | - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec | |
1398 | operations. | |
1399 | For Axon, 2048 | |
1400 | - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec | |
1401 | operations. | |
1402 | For Axon, 2048. | |
1403 | - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate | |
1404 | thresholds). | |
1405 | For Axon, 0x00000010 | |
1406 | - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) | |
1407 | in bytes. | |
1408 | For Axon, 0x00000100 (I think ...) | |
1409 | - phy-mode : string, mode of operations of the PHY interface. | |
1410 | Supported values are: "mii", "rmii", "smii", "rgmii", | |
1411 | "tbi", "gmii", rtbi", "sgmii". | |
1412 | For Axon on CAB, it is "rgmii" | |
1413 | - mdio-device : 1 cell, required iff using shared MDIO registers | |
1414 | (440EP). phandle of the EMAC to use to drive the | |
1415 | MDIO lines for the PHY used by this EMAC. | |
1416 | - zmii-device : 1 cell, required iff connected to a ZMII. phandle of | |
1417 | the ZMII device node | |
1418 | - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII | |
1419 | channel or 0xffffffff if ZMII is only used for MDIO. | |
1420 | - rgmii-device : 1 cell, required iff connected to an RGMII. phandle | |
1421 | of the RGMII device node. | |
1422 | For Axon: phandle of plb5/plb4/opb/rgmii | |
1423 | - rgmii-channel : 1 cell, required iff connected to an RGMII. Which | |
1424 | RGMII channel is used by this EMAC. | |
1425 | Fox Axon: present, whatever value is appropriate for each | |
1426 | EMAC, that is the content of the current (bogus) "phy-port" | |
1427 | property. | |
1428 | ||
1d3bb996 DG |
1429 | Optional properties: |
1430 | - phy-address : 1 cell, optional, MDIO address of the PHY. If absent, | |
1431 | a search is performed. | |
1432 | - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY | |
1433 | for, used if phy-address is absent. bit 0x00000001 is | |
1434 | MDIO address 0. | |
1435 | For Axon it can be absent, thouugh my current driver | |
1436 | doesn't handle phy-address yet so for now, keep | |
1437 | 0x00ffffff in it. | |
1438 | - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec | |
1439 | operations (if absent the value is the same as | |
1440 | rx-fifo-size). For Axon, either absent or 2048. | |
1441 | - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec | |
1442 | operations (if absent the value is the same as | |
1443 | tx-fifo-size). For Axon, either absent or 2048. | |
1444 | - tah-device : 1 cell, optional. If connected to a TAH engine for | |
1445 | offload, phandle of the TAH device node. | |
1446 | - tah-channel : 1 cell, optional. If appropriate, channel used on the | |
1447 | TAH engine. | |
1448 | ||
1449 | Example: | |
1450 | ||
1451 | EMAC0: ethernet@40000800 { | |
1d3bb996 DG |
1452 | device_type = "network"; |
1453 | compatible = "ibm,emac-440gp", "ibm,emac"; | |
1454 | interrupt-parent = <&UIC1>; | |
1455 | interrupts = <1c 4 1d 4>; | |
1456 | reg = <40000800 70>; | |
1457 | local-mac-address = [00 04 AC E3 1B 1E]; | |
1458 | mal-device = <&MAL0>; | |
1459 | mal-tx-channel = <0 1>; | |
1460 | mal-rx-channel = <0>; | |
1461 | cell-index = <0>; | |
1462 | max-frame-size = <5dc>; | |
1463 | rx-fifo-size = <1000>; | |
1464 | tx-fifo-size = <800>; | |
1465 | phy-mode = "rmii"; | |
1466 | phy-map = <00000001>; | |
1467 | zmii-device = <&ZMII0>; | |
1468 | zmii-channel = <0>; | |
1469 | }; | |
1470 | ||
1471 | ii) McMAL node | |
1472 | ||
1473 | Required properties: | |
1474 | - device_type : "dma-controller" | |
1475 | - compatible : compatible list, containing 2 entries, first is | |
1476 | "ibm,mcmal-CHIP" where CHIP is the host ASIC (like | |
1477 | emac) and the second is either "ibm,mcmal" or | |
1478 | "ibm,mcmal2". | |
1479 | For Axon, "ibm,mcmal-axon","ibm,mcmal2" | |
1480 | - interrupts : <interrupt mapping for the MAL interrupts sources: | |
1481 | 5 sources: tx_eob, rx_eob, serr, txde, rxde>. | |
1482 | For Axon: This is _different_ from the current | |
1483 | firmware. We use the "delayed" interrupts for txeob | |
1484 | and rxeob. Thus we end up with mapping those 5 MPIC | |
1485 | interrupts, all level positive sensitive: 10, 11, 32, | |
1486 | 33, 34 (in decimal) | |
1487 | - dcr-reg : < DCR registers range > | |
1488 | - dcr-parent : if needed for dcr-reg | |
1489 | - num-tx-chans : 1 cell, number of Tx channels | |
1490 | - num-rx-chans : 1 cell, number of Rx channels | |
1491 | ||
1492 | iii) ZMII node | |
1493 | ||
1494 | Required properties: | |
1495 | - compatible : compatible list, containing 2 entries, first is | |
1496 | "ibm,zmii-CHIP" where CHIP is the host ASIC (like | |
1497 | EMAC) and the second is "ibm,zmii". | |
1498 | For Axon, there is no ZMII node. | |
1499 | - reg : <registers mapping> | |
1500 | ||
1501 | iv) RGMII node | |
1502 | ||
1503 | Required properties: | |
1504 | - compatible : compatible list, containing 2 entries, first is | |
1505 | "ibm,rgmii-CHIP" where CHIP is the host ASIC (like | |
1506 | EMAC) and the second is "ibm,rgmii". | |
1507 | For Axon, "ibm,rgmii-axon","ibm,rgmii" | |
1508 | - reg : <registers mapping> | |
1509 | - revision : as provided by the RGMII new version register if | |
1510 | available. | |
1511 | For Axon: 0x0000012a | |
1512 | ||
d0fc2eaa | 1513 | e) Xilinx IP cores |
7ae0fa49 GL |
1514 | |
1515 | The Xilinx EDK toolchain ships with a set of IP cores (devices) for use | |
1516 | in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range | |
1517 | of standard device types (network, serial, etc.) and miscellanious | |
1518 | devices (gpio, LCD, spi, etc). Also, since these devices are | |
1519 | implemented within the fpga fabric every instance of the device can be | |
1520 | synthesised with different options that change the behaviour. | |
1521 | ||
1522 | Each IP-core has a set of parameters which the FPGA designer can use to | |
1523 | control how the core is synthesized. Historically, the EDK tool would | |
1524 | extract the device parameters relevant to device drivers and copy them | |
1525 | into an 'xparameters.h' in the form of #define symbols. This tells the | |
1526 | device drivers how the IP cores are configured, but it requres the kernel | |
1527 | to be recompiled every time the FPGA bitstream is resynthesized. | |
1528 | ||
1529 | The new approach is to export the parameters into the device tree and | |
1530 | generate a new device tree each time the FPGA bitstream changes. The | |
1531 | parameters which used to be exported as #defines will now become | |
1532 | properties of the device node. In general, device nodes for IP-cores | |
1533 | will take the following form: | |
1534 | ||
ab99eee8 | 1535 | (name): (generic-name)@(base-address) { |
7ae0fa49 GL |
1536 | compatible = "xlnx,(ip-core-name)-(HW_VER)" |
1537 | [, (list of compatible devices), ...]; | |
1538 | reg = <(baseaddr) (size)>; | |
1539 | interrupt-parent = <&interrupt-controller-phandle>; | |
1540 | interrupts = < ... >; | |
1541 | xlnx,(parameter1) = "(string-value)"; | |
1542 | xlnx,(parameter2) = <(int-value)>; | |
1543 | }; | |
1544 | ||
ab99eee8 SN |
1545 | (generic-name): an open firmware-style name that describes the |
1546 | generic class of device. Preferably, this is one word, such | |
1547 | as 'serial' or 'ethernet'. | |
7ae0fa49 GL |
1548 | (ip-core-name): the name of the ip block (given after the BEGIN |
1549 | directive in system.mhs). Should be in lowercase | |
1550 | and all underscores '_' converted to dashes '-'. | |
1551 | (name): is derived from the "PARAMETER INSTANCE" value. | |
1552 | (parameter#): C_* parameters from system.mhs. The C_ prefix is | |
1553 | dropped from the parameter name, the name is converted | |
1554 | to lowercase and all underscore '_' characters are | |
1555 | converted to dashes '-'. | |
ab99eee8 | 1556 | (baseaddr): the baseaddr parameter value (often named C_BASEADDR). |
7ae0fa49 | 1557 | (HW_VER): from the HW_VER parameter. |
ab99eee8 | 1558 | (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). |
7ae0fa49 GL |
1559 | |
1560 | Typically, the compatible list will include the exact IP core version | |
1561 | followed by an older IP core version which implements the same | |
1562 | interface or any other device with the same interface. | |
1563 | ||
1564 | 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. | |
1565 | ||
1566 | For example, the following block from system.mhs: | |
1567 | ||
1568 | BEGIN opb_uartlite | |
1569 | PARAMETER INSTANCE = opb_uartlite_0 | |
1570 | PARAMETER HW_VER = 1.00.b | |
1571 | PARAMETER C_BAUDRATE = 115200 | |
1572 | PARAMETER C_DATA_BITS = 8 | |
1573 | PARAMETER C_ODD_PARITY = 0 | |
1574 | PARAMETER C_USE_PARITY = 0 | |
1575 | PARAMETER C_CLK_FREQ = 50000000 | |
1576 | PARAMETER C_BASEADDR = 0xEC100000 | |
1577 | PARAMETER C_HIGHADDR = 0xEC10FFFF | |
1578 | BUS_INTERFACE SOPB = opb_7 | |
1579 | PORT OPB_Clk = CLK_50MHz | |
1580 | PORT Interrupt = opb_uartlite_0_Interrupt | |
1581 | PORT RX = opb_uartlite_0_RX | |
1582 | PORT TX = opb_uartlite_0_TX | |
1583 | PORT OPB_Rst = sys_bus_reset_0 | |
1584 | END | |
1585 | ||
1586 | becomes the following device tree node: | |
1587 | ||
ab99eee8 | 1588 | opb_uartlite_0: serial@ec100000 { |
7ae0fa49 GL |
1589 | device_type = "serial"; |
1590 | compatible = "xlnx,opb-uartlite-1.00.b"; | |
1591 | reg = <ec100000 10000>; | |
ab99eee8 | 1592 | interrupt-parent = <&opb_intc_0>; |
7ae0fa49 GL |
1593 | interrupts = <1 0>; // got this from the opb_intc parameters |
1594 | current-speed = <d#115200>; // standard serial device prop | |
1595 | clock-frequency = <d#50000000>; // standard serial device prop | |
1596 | xlnx,data-bits = <8>; | |
1597 | xlnx,odd-parity = <0>; | |
1598 | xlnx,use-parity = <0>; | |
1599 | }; | |
1600 | ||
ab99eee8 SN |
1601 | Some IP cores actually implement 2 or more logical devices. In |
1602 | this case, the device should still describe the whole IP core with | |
1603 | a single node and add a child node for each logical device. The | |
1604 | ranges property can be used to translate from parent IP-core to the | |
1605 | registers of each device. In addition, the parent node should be | |
1606 | compatible with the bus type 'xlnx,compound', and should contain | |
1607 | #address-cells and #size-cells, as with any other bus. (Note: this | |
1608 | makes the assumption that both logical devices have the same bus | |
1609 | binding. If this is not true, then separate nodes should be used | |
1610 | for each logical device). The 'cell-index' property can be used to | |
1611 | enumerate logical devices within an IP core. For example, the | |
1612 | following is the system.mhs entry for the dual ps2 controller found | |
1613 | on the ml403 reference design. | |
7ae0fa49 GL |
1614 | |
1615 | BEGIN opb_ps2_dual_ref | |
1616 | PARAMETER INSTANCE = opb_ps2_dual_ref_0 | |
1617 | PARAMETER HW_VER = 1.00.a | |
1618 | PARAMETER C_BASEADDR = 0xA9000000 | |
1619 | PARAMETER C_HIGHADDR = 0xA9001FFF | |
1620 | BUS_INTERFACE SOPB = opb_v20_0 | |
1621 | PORT Sys_Intr1 = ps2_1_intr | |
1622 | PORT Sys_Intr2 = ps2_2_intr | |
1623 | PORT Clkin1 = ps2_clk_rx_1 | |
1624 | PORT Clkin2 = ps2_clk_rx_2 | |
1625 | PORT Clkpd1 = ps2_clk_tx_1 | |
1626 | PORT Clkpd2 = ps2_clk_tx_2 | |
1627 | PORT Rx1 = ps2_d_rx_1 | |
1628 | PORT Rx2 = ps2_d_rx_2 | |
1629 | PORT Txpd1 = ps2_d_tx_1 | |
1630 | PORT Txpd2 = ps2_d_tx_2 | |
1631 | END | |
1632 | ||
1633 | It would result in the following device tree nodes: | |
1634 | ||
ab99eee8 SN |
1635 | opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 { |
1636 | #address-cells = <1>; | |
1637 | #size-cells = <1>; | |
1638 | compatible = "xlnx,compound"; | |
7ae0fa49 GL |
1639 | ranges = <0 a9000000 2000>; |
1640 | // If this device had extra parameters, then they would | |
1641 | // go here. | |
1642 | ps2@0 { | |
1643 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | |
1644 | reg = <0 40>; | |
ab99eee8 | 1645 | interrupt-parent = <&opb_intc_0>; |
7ae0fa49 GL |
1646 | interrupts = <3 0>; |
1647 | cell-index = <0>; | |
1648 | }; | |
1649 | ps2@1000 { | |
1650 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | |
1651 | reg = <1000 40>; | |
ab99eee8 | 1652 | interrupt-parent = <&opb_intc_0>; |
7ae0fa49 GL |
1653 | interrupts = <3 0>; |
1654 | cell-index = <0>; | |
1655 | }; | |
1656 | }; | |
1657 | ||
1658 | Also, the system.mhs file defines bus attachments from the processor | |
1659 | to the devices. The device tree structure should reflect the bus | |
1660 | attachments. Again an example; this system.mhs fragment: | |
1661 | ||
1662 | BEGIN ppc405_virtex4 | |
1663 | PARAMETER INSTANCE = ppc405_0 | |
1664 | PARAMETER HW_VER = 1.01.a | |
1665 | BUS_INTERFACE DPLB = plb_v34_0 | |
1666 | BUS_INTERFACE IPLB = plb_v34_0 | |
1667 | END | |
1668 | ||
1669 | BEGIN opb_intc | |
1670 | PARAMETER INSTANCE = opb_intc_0 | |
1671 | PARAMETER HW_VER = 1.00.c | |
1672 | PARAMETER C_BASEADDR = 0xD1000FC0 | |
1673 | PARAMETER C_HIGHADDR = 0xD1000FDF | |
1674 | BUS_INTERFACE SOPB = opb_v20_0 | |
1675 | END | |
1676 | ||
1677 | BEGIN opb_uart16550 | |
1678 | PARAMETER INSTANCE = opb_uart16550_0 | |
1679 | PARAMETER HW_VER = 1.00.d | |
1680 | PARAMETER C_BASEADDR = 0xa0000000 | |
1681 | PARAMETER C_HIGHADDR = 0xa0001FFF | |
1682 | BUS_INTERFACE SOPB = opb_v20_0 | |
1683 | END | |
1684 | ||
1685 | BEGIN plb_v34 | |
1686 | PARAMETER INSTANCE = plb_v34_0 | |
1687 | PARAMETER HW_VER = 1.02.a | |
1688 | END | |
1689 | ||
1690 | BEGIN plb_bram_if_cntlr | |
1691 | PARAMETER INSTANCE = plb_bram_if_cntlr_0 | |
1692 | PARAMETER HW_VER = 1.00.b | |
1693 | PARAMETER C_BASEADDR = 0xFFFF0000 | |
1694 | PARAMETER C_HIGHADDR = 0xFFFFFFFF | |
1695 | BUS_INTERFACE SPLB = plb_v34_0 | |
1696 | END | |
1697 | ||
1698 | BEGIN plb2opb_bridge | |
1699 | PARAMETER INSTANCE = plb2opb_bridge_0 | |
1700 | PARAMETER HW_VER = 1.01.a | |
1701 | PARAMETER C_RNG0_BASEADDR = 0x20000000 | |
1702 | PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF | |
1703 | PARAMETER C_RNG1_BASEADDR = 0x60000000 | |
1704 | PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF | |
1705 | PARAMETER C_RNG2_BASEADDR = 0x80000000 | |
1706 | PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF | |
1707 | PARAMETER C_RNG3_BASEADDR = 0xC0000000 | |
1708 | PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF | |
1709 | BUS_INTERFACE SPLB = plb_v34_0 | |
1710 | BUS_INTERFACE MOPB = opb_v20_0 | |
1711 | END | |
1712 | ||
1713 | Gives this device tree (some properties removed for clarity): | |
1714 | ||
ab99eee8 | 1715 | plb@0 { |
7ae0fa49 GL |
1716 | #address-cells = <1>; |
1717 | #size-cells = <1>; | |
ab99eee8 | 1718 | compatible = "xlnx,plb-v34-1.02.a"; |
7ae0fa49 GL |
1719 | device_type = "ibm,plb"; |
1720 | ranges; // 1:1 translation | |
1721 | ||
ab99eee8 | 1722 | plb_bram_if_cntrl_0: bram@ffff0000 { |
7ae0fa49 GL |
1723 | reg = <ffff0000 10000>; |
1724 | } | |
1725 | ||
ab99eee8 | 1726 | opb@20000000 { |
7ae0fa49 GL |
1727 | #address-cells = <1>; |
1728 | #size-cells = <1>; | |
1729 | ranges = <20000000 20000000 20000000 | |
1730 | 60000000 60000000 20000000 | |
1731 | 80000000 80000000 40000000 | |
1732 | c0000000 c0000000 20000000>; | |
1733 | ||
ab99eee8 | 1734 | opb_uart16550_0: serial@a0000000 { |
7ae0fa49 GL |
1735 | reg = <a00000000 2000>; |
1736 | }; | |
1737 | ||
ab99eee8 | 1738 | opb_intc_0: interrupt-controller@d1000fc0 { |
7ae0fa49 GL |
1739 | reg = <d1000fc0 20>; |
1740 | }; | |
1741 | }; | |
1742 | }; | |
1743 | ||
1744 | That covers the general approach to binding xilinx IP cores into the | |
1745 | device tree. The following are bindings for specific devices: | |
1746 | ||
1747 | i) Xilinx ML300 Framebuffer | |
1748 | ||
1749 | Simple framebuffer device from the ML300 reference design (also on the | |
1750 | ML403 reference design as well as others). | |
1751 | ||
1752 | Optional properties: | |
1753 | - resolution = <xres yres> : pixel resolution of framebuffer. Some | |
1754 | implementations use a different resolution. | |
1755 | Default is <d#640 d#480> | |
1756 | - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. | |
1757 | Default is <d#1024 d#480>. | |
1758 | - rotate-display (empty) : rotate display 180 degrees. | |
1759 | ||
1760 | ii) Xilinx SystemACE | |
1761 | ||
1762 | The Xilinx SystemACE device is used to program FPGAs from an FPGA | |
1763 | bitstream stored on a CF card. It can also be used as a generic CF | |
1764 | interface device. | |
1765 | ||
1766 | Optional properties: | |
1767 | - 8-bit (empty) : Set this property for SystemACE in 8 bit mode | |
1768 | ||
1769 | iii) Xilinx EMAC and Xilinx TEMAC | |
1770 | ||
1771 | Xilinx Ethernet devices. In addition to general xilinx properties | |
1772 | listed above, nodes for these devices should include a phy-handle | |
1773 | property, and may include other common network device properties | |
1774 | like local-mac-address. | |
1775 | ||
1776 | iv) Xilinx Uartlite | |
1777 | ||
1778 | Xilinx uartlite devices are simple fixed speed serial ports. | |
1779 | ||
d9195881 | 1780 | Required properties: |
7ae0fa49 GL |
1781 | - current-speed : Baud rate of uartlite |
1782 | ||
ef66a9d2 SN |
1783 | v) Xilinx hwicap |
1784 | ||
1785 | Xilinx hwicap devices provide access to the configuration logic | |
1786 | of the FPGA through the Internal Configuration Access Port | |
1787 | (ICAP). The ICAP enables partial reconfiguration of the FPGA, | |
1788 | readback of the configuration information, and some control over | |
1789 | 'warm boots' of the FPGA fabric. | |
1790 | ||
1791 | Required properties: | |
1792 | - xlnx,family : The family of the FPGA, necessary since the | |
1793 | capabilities of the underlying ICAP hardware | |
1794 | differ between different families. May be | |
1795 | 'virtex2p', 'virtex4', or 'virtex5'. | |
1796 | ||
b912b5e2 JL |
1797 | vi) Xilinx Uart 16550 |
1798 | ||
1799 | Xilinx UART 16550 devices are very similar to the NS16550 but with | |
1800 | different register spacing and an offset from the base address. | |
1801 | ||
d9195881 | 1802 | Required properties: |
b912b5e2 JL |
1803 | - clock-frequency : Frequency of the clock input |
1804 | - reg-offset : A value of 3 is required | |
1805 | - reg-shift : A value of 2 is required | |
1806 | ||
d0fc2eaa | 1807 | f) USB EHCI controllers |
41abd68e VB |
1808 | |
1809 | Required properties: | |
1810 | - compatible : should be "usb-ehci". | |
1811 | - reg : should contain at least address and length of the standard EHCI | |
1812 | register set for the device. Optional platform-dependent registers | |
1813 | (debug-port or other) can be also specified here, but only after | |
1814 | definition of standard EHCI registers. | |
1815 | - interrupts : one EHCI interrupt should be described here. | |
1816 | If device registers are implemented in big endian mode, the device | |
1817 | node should have "big-endian-regs" property. | |
1818 | If controller implementation operates with big endian descriptors, | |
1819 | "big-endian-desc" property should be specified. | |
1820 | If both big endian registers and descriptors are used by the controller | |
1821 | implementation, "big-endian" property can be specified instead of having | |
1822 | both "big-endian-regs" and "big-endian-desc". | |
1823 | ||
1824 | Example (Sequoia 440EPx): | |
1825 | ehci@e0000300 { | |
1826 | compatible = "ibm,usb-ehci-440epx", "usb-ehci"; | |
1827 | interrupt-parent = <&UIC0>; | |
1828 | interrupts = <1a 4>; | |
1829 | reg = <0 e0000300 90 0 e0000390 70>; | |
1830 | big-endian; | |
1831 | }; | |
1832 | ||
9b53a9e2 YS |
1833 | r) Freescale Display Interface Unit |
1834 | ||
1835 | The Freescale DIU is a LCD controller, with proper hardware, it can also | |
1836 | drive DVI monitors. | |
1837 | ||
1838 | Required properties: | |
1839 | - compatible : should be "fsl-diu". | |
1840 | - reg : should contain at least address and length of the DIU register | |
1841 | set. | |
1842 | - Interrupts : one DIU interrupt should be describe here. | |
1843 | ||
1844 | Example (MPC8610HPCD) | |
1845 | display@2c000 { | |
1846 | compatible = "fsl,diu"; | |
1847 | reg = <0x2c000 100>; | |
1848 | interrupts = <72 2>; | |
1849 | interrupt-parent = <&mpic>; | |
1850 | }; | |
1851 | ||
1852 | s) Freescale on board FPGA | |
1853 | ||
1854 | This is the memory-mapped registers for on board FPGA. | |
1855 | ||
1856 | Required properities: | |
1857 | - compatible : should be "fsl,fpga-pixis". | |
1858 | - reg : should contain the address and the lenght of the FPPGA register | |
1859 | set. | |
1860 | ||
1861 | Example (MPC8610HPCD) | |
1862 | board-control@e8000000 { | |
1863 | compatible = "fsl,fpga-pixis"; | |
1864 | reg = <0xe8000000 32>; | |
1865 | }; | |
41abd68e | 1866 | |
a5edeccb LP |
1867 | r) MDIO on GPIOs |
1868 | ||
1869 | Currently defined compatibles: | |
1870 | - virtual,gpio-mdio | |
1871 | ||
1872 | MDC and MDIO lines connected to GPIO controllers are listed in the | |
1873 | gpios property as described in section VIII.1 in the following order: | |
1874 | ||
1875 | MDC, MDIO. | |
1876 | ||
1877 | Example: | |
1878 | ||
1879 | mdio { | |
1880 | compatible = "virtual,mdio-gpio"; | |
1881 | #address-cells = <1>; | |
1882 | #size-cells = <0>; | |
1883 | gpios = <&qe_pio_a 11 | |
1884 | &qe_pio_c 6>; | |
1885 | }; | |
1886 | ||
79c28acb GL |
1887 | s) SPI (Serial Peripheral Interface) busses |
1888 | ||
1889 | SPI busses can be described with a node for the SPI master device | |
1890 | and a set of child nodes for each SPI slave on the bus. For this | |
1891 | discussion, it is assumed that the system's SPI controller is in | |
1892 | SPI master mode. This binding does not describe SPI controllers | |
1893 | in slave mode. | |
1894 | ||
1895 | The SPI master node requires the following properties: | |
1896 | - #address-cells - number of cells required to define a chip select | |
1897 | address on the SPI bus. | |
1898 | - #size-cells - should be zero. | |
1899 | - compatible - name of SPI bus controller following generic names | |
1900 | recommended practice. | |
1901 | No other properties are required in the SPI bus node. It is assumed | |
1902 | that a driver for an SPI bus device will understand that it is an SPI bus. | |
1903 | However, the binding does not attempt to define the specific method for | |
1904 | assigning chip select numbers. Since SPI chip select configuration is | |
1905 | flexible and non-standardized, it is left out of this binding with the | |
1906 | assumption that board specific platform code will be used to manage | |
1907 | chip selects. Individual drivers can define additional properties to | |
1908 | support describing the chip select layout. | |
1909 | ||
1910 | SPI slave nodes must be children of the SPI master node and can | |
1911 | contain the following properties. | |
1912 | - reg - (required) chip select address of device. | |
1913 | - compatible - (required) name of SPI device following generic names | |
1914 | recommended practice | |
1915 | - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz | |
1916 | - spi-cpol - (optional) Empty property indicating device requires | |
1917 | inverse clock polarity (CPOL) mode | |
1918 | - spi-cpha - (optional) Empty property indicating device requires | |
1919 | shifted clock phase (CPHA) mode | |
1920 | ||
1921 | SPI example for an MPC5200 SPI bus: | |
1922 | spi@f00 { | |
1923 | #address-cells = <1>; | |
1924 | #size-cells = <0>; | |
1925 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | |
1926 | reg = <0xf00 0x20>; | |
1927 | interrupts = <2 13 0 2 14 0>; | |
1928 | interrupt-parent = <&mpc5200_pic>; | |
1929 | ||
1930 | ethernet-switch@0 { | |
1931 | compatible = "micrel,ks8995m"; | |
1932 | spi-max-frequency = <1000000>; | |
1933 | reg = <0>; | |
1934 | }; | |
1935 | ||
1936 | codec@1 { | |
1937 | compatible = "ti,tlv320aic26"; | |
1938 | spi-max-frequency = <100000>; | |
1939 | reg = <1>; | |
1940 | }; | |
1941 | }; | |
1942 | ||
f5412c49 DF |
1943 | VII - Marvell Discovery mv64[345]6x System Controller chips |
1944 | =========================================================== | |
c125a183 | 1945 | |
f5412c49 DF |
1946 | The Marvell mv64[345]60 series of system controller chips contain |
1947 | many of the peripherals needed to implement a complete computer | |
1948 | system. In this section, we define device tree nodes to describe | |
1949 | the system controller chip itself and each of the peripherals | |
1950 | which it contains. Compatible string values for each node are | |
1951 | prefixed with the string "marvell,", for Marvell Technology Group Ltd. | |
1952 | ||
1953 | 1) The /system-controller node | |
1954 | ||
1955 | This node is used to represent the system-controller and must be | |
d9195881 | 1956 | present when the system uses a system controller chip. The top-level |
f5412c49 DF |
1957 | system-controller node contains information that is global to all |
1958 | devices within the system controller chip. The node name begins | |
1959 | with "system-controller" followed by the unit address, which is | |
1960 | the base address of the memory-mapped register set for the system | |
1961 | controller chip. | |
1962 | ||
1963 | Required properties: | |
1964 | ||
1965 | - ranges : Describes the translation of system controller addresses | |
1966 | for memory mapped registers. | |
1967 | - clock-frequency: Contains the main clock frequency for the system | |
1968 | controller chip. | |
1969 | - reg : This property defines the address and size of the | |
1970 | memory-mapped registers contained within the system controller | |
1971 | chip. The address specified in the "reg" property should match | |
1972 | the unit address of the system-controller node. | |
1973 | - #address-cells : Address representation for system controller | |
1974 | devices. This field represents the number of cells needed to | |
1975 | represent the address of the memory-mapped registers of devices | |
1976 | within the system controller chip. | |
1977 | - #size-cells : Size representation for for the memory-mapped | |
1978 | registers within the system controller chip. | |
1979 | - #interrupt-cells : Defines the width of cells used to represent | |
1980 | interrupts. | |
1981 | ||
1982 | Optional properties: | |
1983 | ||
1984 | - model : The specific model of the system controller chip. Such | |
1985 | as, "mv64360", "mv64460", or "mv64560". | |
1986 | - compatible : A string identifying the compatibility identifiers | |
1987 | of the system controller chip. | |
1988 | ||
1989 | The system-controller node contains child nodes for each system | |
1990 | controller device that the platform uses. Nodes should not be created | |
1991 | for devices which exist on the system controller chip but are not used | |
1992 | ||
1993 | Example Marvell Discovery mv64360 system-controller node: | |
1994 | ||
1995 | system-controller@f1000000 { /* Marvell Discovery mv64360 */ | |
1996 | #address-cells = <1>; | |
1997 | #size-cells = <1>; | |
1998 | model = "mv64360"; /* Default */ | |
1999 | compatible = "marvell,mv64360"; | |
2000 | clock-frequency = <133333333>; | |
2001 | reg = <0xf1000000 0x10000>; | |
2002 | virtual-reg = <0xf1000000>; | |
2003 | ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ | |
2004 | 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ | |
2005 | 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ | |
2006 | 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ | |
2007 | 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ | |
2008 | ||
2009 | [ child node definitions... ] | |
2010 | } | |
2011 | ||
2012 | 2) Child nodes of /system-controller | |
2013 | ||
2014 | a) Marvell Discovery MDIO bus | |
2015 | ||
2016 | The MDIO is a bus to which the PHY devices are connected. For each | |
2017 | device that exists on this bus, a child node should be created. See | |
2018 | the definition of the PHY node below for an example of how to define | |
2019 | a PHY. | |
2020 | ||
2021 | Required properties: | |
2022 | - #address-cells : Should be <1> | |
2023 | - #size-cells : Should be <0> | |
2024 | - device_type : Should be "mdio" | |
2025 | - compatible : Should be "marvell,mv64360-mdio" | |
2026 | ||
2027 | Example: | |
2028 | ||
2029 | mdio { | |
2030 | #address-cells = <1>; | |
2031 | #size-cells = <0>; | |
2032 | device_type = "mdio"; | |
2033 | compatible = "marvell,mv64360-mdio"; | |
2034 | ||
2035 | ethernet-phy@0 { | |
2036 | ...... | |
2037 | }; | |
2038 | }; | |
2039 | ||
2040 | ||
2041 | b) Marvell Discovery ethernet controller | |
2042 | ||
2043 | The Discover ethernet controller is described with two levels | |
2044 | of nodes. The first level describes an ethernet silicon block | |
2045 | and the second level describes up to 3 ethernet nodes within | |
2046 | that block. The reason for the multiple levels is that the | |
2047 | registers for the node are interleaved within a single set | |
2048 | of registers. The "ethernet-block" level describes the | |
2049 | shared register set, and the "ethernet" nodes describe ethernet | |
2050 | port-specific properties. | |
2051 | ||
2052 | Ethernet block node | |
2053 | ||
2054 | Required properties: | |
2055 | - #address-cells : <1> | |
2056 | - #size-cells : <0> | |
2057 | - compatible : "marvell,mv64360-eth-block" | |
2058 | - reg : Offset and length of the register set for this block | |
2059 | ||
2060 | Example Discovery Ethernet block node: | |
2061 | ethernet-block@2000 { | |
2062 | #address-cells = <1>; | |
2063 | #size-cells = <0>; | |
2064 | compatible = "marvell,mv64360-eth-block"; | |
2065 | reg = <0x2000 0x2000>; | |
2066 | ethernet@0 { | |
2067 | ....... | |
2068 | }; | |
2069 | }; | |
2070 | ||
2071 | Ethernet port node | |
2072 | ||
2073 | Required properties: | |
2074 | - device_type : Should be "network". | |
2075 | - compatible : Should be "marvell,mv64360-eth". | |
2076 | - reg : Should be <0>, <1>, or <2>, according to which registers | |
2077 | within the silicon block the device uses. | |
2078 | - interrupts : <a> where a is the interrupt number for the port. | |
2079 | - interrupt-parent : the phandle for the interrupt controller | |
2080 | that services interrupts for this device. | |
2081 | - phy : the phandle for the PHY connected to this ethernet | |
2082 | controller. | |
2083 | - local-mac-address : 6 bytes, MAC address | |
2084 | ||
2085 | Example Discovery Ethernet port node: | |
2086 | ethernet@0 { | |
2087 | device_type = "network"; | |
2088 | compatible = "marvell,mv64360-eth"; | |
2089 | reg = <0>; | |
2090 | interrupts = <32>; | |
2091 | interrupt-parent = <&PIC>; | |
2092 | phy = <&PHY0>; | |
2093 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
2094 | }; | |
2095 | ||
2096 | ||
2097 | ||
2098 | c) Marvell Discovery PHY nodes | |
2099 | ||
2100 | Required properties: | |
2101 | - device_type : Should be "ethernet-phy" | |
2102 | - interrupts : <a> where a is the interrupt number for this phy. | |
2103 | - interrupt-parent : the phandle for the interrupt controller that | |
2104 | services interrupts for this device. | |
2105 | - reg : The ID number for the phy, usually a small integer | |
2106 | ||
2107 | Example Discovery PHY node: | |
2108 | ethernet-phy@1 { | |
2109 | device_type = "ethernet-phy"; | |
2110 | compatible = "broadcom,bcm5421"; | |
2111 | interrupts = <76>; /* GPP 12 */ | |
2112 | interrupt-parent = <&PIC>; | |
2113 | reg = <1>; | |
2114 | }; | |
2115 | ||
2116 | ||
2117 | d) Marvell Discovery SDMA nodes | |
2118 | ||
2119 | Represent DMA hardware associated with the MPSC (multiprotocol | |
2120 | serial controllers). | |
2121 | ||
2122 | Required properties: | |
2123 | - compatible : "marvell,mv64360-sdma" | |
2124 | - reg : Offset and length of the register set for this device | |
2125 | - interrupts : <a> where a is the interrupt number for the DMA | |
2126 | device. | |
2127 | - interrupt-parent : the phandle for the interrupt controller | |
2128 | that services interrupts for this device. | |
2129 | ||
2130 | Example Discovery SDMA node: | |
2131 | sdma@4000 { | |
2132 | compatible = "marvell,mv64360-sdma"; | |
2133 | reg = <0x4000 0xc18>; | |
2134 | virtual-reg = <0xf1004000>; | |
2135 | interrupts = <36>; | |
2136 | interrupt-parent = <&PIC>; | |
2137 | }; | |
2138 | ||
2139 | ||
2140 | e) Marvell Discovery BRG nodes | |
2141 | ||
2142 | Represent baud rate generator hardware associated with the MPSC | |
2143 | (multiprotocol serial controllers). | |
2144 | ||
2145 | Required properties: | |
2146 | - compatible : "marvell,mv64360-brg" | |
2147 | - reg : Offset and length of the register set for this device | |
2148 | - clock-src : A value from 0 to 15 which selects the clock | |
2149 | source for the baud rate generator. This value corresponds | |
2150 | to the CLKS value in the BRGx configuration register. See | |
2151 | the mv64x60 User's Manual. | |
2152 | - clock-frequence : The frequency (in Hz) of the baud rate | |
2153 | generator's input clock. | |
2154 | - current-speed : The current speed setting (presumably by | |
2155 | firmware) of the baud rate generator. | |
2156 | ||
2157 | Example Discovery BRG node: | |
2158 | brg@b200 { | |
2159 | compatible = "marvell,mv64360-brg"; | |
2160 | reg = <0xb200 0x8>; | |
2161 | clock-src = <8>; | |
2162 | clock-frequency = <133333333>; | |
2163 | current-speed = <9600>; | |
2164 | }; | |
2165 | ||
2166 | ||
2167 | f) Marvell Discovery CUNIT nodes | |
2168 | ||
2169 | Represent the Serial Communications Unit device hardware. | |
2170 | ||
2171 | Required properties: | |
2172 | - reg : Offset and length of the register set for this device | |
2173 | ||
2174 | Example Discovery CUNIT node: | |
2175 | cunit@f200 { | |
2176 | reg = <0xf200 0x200>; | |
2177 | }; | |
2178 | ||
2179 | ||
2180 | g) Marvell Discovery MPSCROUTING nodes | |
2181 | ||
2182 | Represent the Discovery's MPSC routing hardware | |
2183 | ||
2184 | Required properties: | |
2185 | - reg : Offset and length of the register set for this device | |
2186 | ||
2187 | Example Discovery CUNIT node: | |
2188 | mpscrouting@b500 { | |
2189 | reg = <0xb400 0xc>; | |
2190 | }; | |
2191 | ||
2192 | ||
2193 | h) Marvell Discovery MPSCINTR nodes | |
2194 | ||
2195 | Represent the Discovery's MPSC DMA interrupt hardware registers | |
2196 | (SDMA cause and mask registers). | |
2197 | ||
2198 | Required properties: | |
2199 | - reg : Offset and length of the register set for this device | |
2200 | ||
2201 | Example Discovery MPSCINTR node: | |
2202 | mpsintr@b800 { | |
2203 | reg = <0xb800 0x100>; | |
2204 | }; | |
2205 | ||
2206 | ||
2207 | i) Marvell Discovery MPSC nodes | |
2208 | ||
2209 | Represent the Discovery's MPSC (Multiprotocol Serial Controller) | |
2210 | serial port. | |
2211 | ||
2212 | Required properties: | |
2213 | - device_type : "serial" | |
2214 | - compatible : "marvell,mv64360-mpsc" | |
2215 | - reg : Offset and length of the register set for this device | |
2216 | - sdma : the phandle for the SDMA node used by this port | |
2217 | - brg : the phandle for the BRG node used by this port | |
2218 | - cunit : the phandle for the CUNIT node used by this port | |
2219 | - mpscrouting : the phandle for the MPSCROUTING node used by this port | |
2220 | - mpscintr : the phandle for the MPSCINTR node used by this port | |
2221 | - cell-index : the hardware index of this cell in the MPSC core | |
2222 | - max_idle : value needed for MPSC CHR3 (Maximum Frame Length) | |
2223 | register | |
2224 | - interrupts : <a> where a is the interrupt number for the MPSC. | |
2225 | - interrupt-parent : the phandle for the interrupt controller | |
2226 | that services interrupts for this device. | |
2227 | ||
2228 | Example Discovery MPSCINTR node: | |
2229 | mpsc@8000 { | |
2230 | device_type = "serial"; | |
2231 | compatible = "marvell,mv64360-mpsc"; | |
2232 | reg = <0x8000 0x38>; | |
2233 | virtual-reg = <0xf1008000>; | |
2234 | sdma = <&SDMA0>; | |
2235 | brg = <&BRG0>; | |
2236 | cunit = <&CUNIT>; | |
2237 | mpscrouting = <&MPSCROUTING>; | |
2238 | mpscintr = <&MPSCINTR>; | |
2239 | cell-index = <0>; | |
2240 | max_idle = <40>; | |
2241 | interrupts = <40>; | |
2242 | interrupt-parent = <&PIC>; | |
2243 | }; | |
2244 | ||
2245 | ||
2246 | j) Marvell Discovery Watch Dog Timer nodes | |
2247 | ||
2248 | Represent the Discovery's watchdog timer hardware | |
2249 | ||
2250 | Required properties: | |
2251 | - compatible : "marvell,mv64360-wdt" | |
2252 | - reg : Offset and length of the register set for this device | |
2253 | ||
2254 | Example Discovery Watch Dog Timer node: | |
2255 | wdt@b410 { | |
2256 | compatible = "marvell,mv64360-wdt"; | |
2257 | reg = <0xb410 0x8>; | |
2258 | }; | |
2259 | ||
2260 | ||
2261 | k) Marvell Discovery I2C nodes | |
2262 | ||
2263 | Represent the Discovery's I2C hardware | |
2264 | ||
2265 | Required properties: | |
2266 | - device_type : "i2c" | |
2267 | - compatible : "marvell,mv64360-i2c" | |
2268 | - reg : Offset and length of the register set for this device | |
2269 | - interrupts : <a> where a is the interrupt number for the I2C. | |
2270 | - interrupt-parent : the phandle for the interrupt controller | |
2271 | that services interrupts for this device. | |
2272 | ||
2273 | Example Discovery I2C node: | |
2274 | compatible = "marvell,mv64360-i2c"; | |
2275 | reg = <0xc000 0x20>; | |
2276 | virtual-reg = <0xf100c000>; | |
2277 | interrupts = <37>; | |
2278 | interrupt-parent = <&PIC>; | |
2279 | }; | |
2280 | ||
2281 | ||
2282 | l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes | |
2283 | ||
2284 | Represent the Discovery's PIC hardware | |
2285 | ||
2286 | Required properties: | |
2287 | - #interrupt-cells : <1> | |
2288 | - #address-cells : <0> | |
2289 | - compatible : "marvell,mv64360-pic" | |
2290 | - reg : Offset and length of the register set for this device | |
2291 | - interrupt-controller | |
2292 | ||
2293 | Example Discovery PIC node: | |
2294 | pic { | |
2295 | #interrupt-cells = <1>; | |
2296 | #address-cells = <0>; | |
2297 | compatible = "marvell,mv64360-pic"; | |
2298 | reg = <0x0 0x88>; | |
2299 | interrupt-controller; | |
2300 | }; | |
2301 | ||
2302 | ||
2303 | m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes | |
2304 | ||
2305 | Represent the Discovery's MPP hardware | |
2306 | ||
2307 | Required properties: | |
2308 | - compatible : "marvell,mv64360-mpp" | |
2309 | - reg : Offset and length of the register set for this device | |
2310 | ||
2311 | Example Discovery MPP node: | |
2312 | mpp@f000 { | |
2313 | compatible = "marvell,mv64360-mpp"; | |
2314 | reg = <0xf000 0x10>; | |
2315 | }; | |
2316 | ||
2317 | ||
2318 | n) Marvell Discovery GPP (General Purpose Pins) nodes | |
2319 | ||
2320 | Represent the Discovery's GPP hardware | |
2321 | ||
2322 | Required properties: | |
2323 | - compatible : "marvell,mv64360-gpp" | |
2324 | - reg : Offset and length of the register set for this device | |
2325 | ||
2326 | Example Discovery GPP node: | |
2327 | gpp@f000 { | |
2328 | compatible = "marvell,mv64360-gpp"; | |
2329 | reg = <0xf100 0x20>; | |
2330 | }; | |
2331 | ||
2332 | ||
2333 | o) Marvell Discovery PCI host bridge node | |
2334 | ||
2335 | Represents the Discovery's PCI host bridge device. The properties | |
2336 | for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE | |
2337 | 1275-1994. A typical value for the compatible property is | |
2338 | "marvell,mv64360-pci". | |
2339 | ||
2340 | Example Discovery PCI host bridge node | |
2341 | pci@80000000 { | |
2342 | #address-cells = <3>; | |
2343 | #size-cells = <2>; | |
2344 | #interrupt-cells = <1>; | |
2345 | device_type = "pci"; | |
2346 | compatible = "marvell,mv64360-pci"; | |
2347 | reg = <0xcf8 0x8>; | |
2348 | ranges = <0x01000000 0x0 0x0 | |
2349 | 0x88000000 0x0 0x01000000 | |
2350 | 0x02000000 0x0 0x80000000 | |
2351 | 0x80000000 0x0 0x08000000>; | |
2352 | bus-range = <0 255>; | |
2353 | clock-frequency = <66000000>; | |
2354 | interrupt-parent = <&PIC>; | |
2355 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
2356 | interrupt-map = < | |
2357 | /* IDSEL 0x0a */ | |
2358 | 0x5000 0 0 1 &PIC 80 | |
2359 | 0x5000 0 0 2 &PIC 81 | |
2360 | 0x5000 0 0 3 &PIC 91 | |
2361 | 0x5000 0 0 4 &PIC 93 | |
2362 | ||
2363 | /* IDSEL 0x0b */ | |
2364 | 0x5800 0 0 1 &PIC 91 | |
2365 | 0x5800 0 0 2 &PIC 93 | |
2366 | 0x5800 0 0 3 &PIC 80 | |
2367 | 0x5800 0 0 4 &PIC 81 | |
2368 | ||
2369 | /* IDSEL 0x0c */ | |
2370 | 0x6000 0 0 1 &PIC 91 | |
2371 | 0x6000 0 0 2 &PIC 93 | |
2372 | 0x6000 0 0 3 &PIC 80 | |
2373 | 0x6000 0 0 4 &PIC 81 | |
2374 | ||
2375 | /* IDSEL 0x0d */ | |
2376 | 0x6800 0 0 1 &PIC 93 | |
2377 | 0x6800 0 0 2 &PIC 80 | |
2378 | 0x6800 0 0 3 &PIC 81 | |
2379 | 0x6800 0 0 4 &PIC 91 | |
2380 | >; | |
2381 | }; | |
2382 | ||
2383 | ||
2384 | p) Marvell Discovery CPU Error nodes | |
2385 | ||
2386 | Represent the Discovery's CPU error handler device. | |
2387 | ||
2388 | Required properties: | |
2389 | - compatible : "marvell,mv64360-cpu-error" | |
2390 | - reg : Offset and length of the register set for this device | |
2391 | - interrupts : the interrupt number for this device | |
2392 | - interrupt-parent : the phandle for the interrupt controller | |
2393 | that services interrupts for this device. | |
2394 | ||
2395 | Example Discovery CPU Error node: | |
2396 | cpu-error@0070 { | |
2397 | compatible = "marvell,mv64360-cpu-error"; | |
2398 | reg = <0x70 0x10 0x128 0x28>; | |
2399 | interrupts = <3>; | |
2400 | interrupt-parent = <&PIC>; | |
2401 | }; | |
2402 | ||
2403 | ||
2404 | q) Marvell Discovery SRAM Controller nodes | |
2405 | ||
2406 | Represent the Discovery's SRAM controller device. | |
2407 | ||
2408 | Required properties: | |
2409 | - compatible : "marvell,mv64360-sram-ctrl" | |
2410 | - reg : Offset and length of the register set for this device | |
2411 | - interrupts : the interrupt number for this device | |
2412 | - interrupt-parent : the phandle for the interrupt controller | |
2413 | that services interrupts for this device. | |
2414 | ||
2415 | Example Discovery SRAM Controller node: | |
2416 | sram-ctrl@0380 { | |
2417 | compatible = "marvell,mv64360-sram-ctrl"; | |
2418 | reg = <0x380 0x80>; | |
2419 | interrupts = <13>; | |
2420 | interrupt-parent = <&PIC>; | |
2421 | }; | |
2422 | ||
2423 | ||
2424 | r) Marvell Discovery PCI Error Handler nodes | |
2425 | ||
2426 | Represent the Discovery's PCI error handler device. | |
2427 | ||
2428 | Required properties: | |
2429 | - compatible : "marvell,mv64360-pci-error" | |
2430 | - reg : Offset and length of the register set for this device | |
2431 | - interrupts : the interrupt number for this device | |
2432 | - interrupt-parent : the phandle for the interrupt controller | |
2433 | that services interrupts for this device. | |
2434 | ||
2435 | Example Discovery PCI Error Handler node: | |
2436 | pci-error@1d40 { | |
2437 | compatible = "marvell,mv64360-pci-error"; | |
2438 | reg = <0x1d40 0x40 0xc28 0x4>; | |
2439 | interrupts = <12>; | |
2440 | interrupt-parent = <&PIC>; | |
2441 | }; | |
2442 | ||
2443 | ||
2444 | s) Marvell Discovery Memory Controller nodes | |
2445 | ||
2446 | Represent the Discovery's memory controller device. | |
2447 | ||
2448 | Required properties: | |
2449 | - compatible : "marvell,mv64360-mem-ctrl" | |
2450 | - reg : Offset and length of the register set for this device | |
2451 | - interrupts : the interrupt number for this device | |
2452 | - interrupt-parent : the phandle for the interrupt controller | |
2453 | that services interrupts for this device. | |
2454 | ||
2455 | Example Discovery Memory Controller node: | |
2456 | mem-ctrl@1400 { | |
2457 | compatible = "marvell,mv64360-mem-ctrl"; | |
2458 | reg = <0x1400 0x60>; | |
2459 | interrupts = <17>; | |
2460 | interrupt-parent = <&PIC>; | |
2461 | }; | |
2462 | ||
2463 | ||
2464 | VIII - Specifying interrupt information for devices | |
27565903 SY |
2465 | =================================================== |
2466 | ||
2467 | The device tree represents the busses and devices of a hardware | |
2468 | system in a form similar to the physical bus topology of the | |
2469 | hardware. | |
2470 | ||
2471 | In addition, a logical 'interrupt tree' exists which represents the | |
2472 | hierarchy and routing of interrupts in the hardware. | |
2473 | ||
2474 | The interrupt tree model is fully described in the | |
2475 | document "Open Firmware Recommended Practice: Interrupt | |
2476 | Mapping Version 0.9". The document is available at: | |
2477 | <http://playground.sun.com/1275/practice>. | |
2478 | ||
2479 | 1) interrupts property | |
2480 | ---------------------- | |
2481 | ||
2482 | Devices that generate interrupts to a single interrupt controller | |
2483 | should use the conventional OF representation described in the | |
2484 | OF interrupt mapping documentation. | |
2485 | ||
2486 | Each device which generates interrupts must have an 'interrupt' | |
2487 | property. The interrupt property value is an arbitrary number of | |
2488 | of 'interrupt specifier' values which describe the interrupt or | |
2489 | interrupts for the device. | |
2490 | ||
2491 | The encoding of an interrupt specifier is determined by the | |
2492 | interrupt domain in which the device is located in the | |
2493 | interrupt tree. The root of an interrupt domain specifies in | |
2494 | its #interrupt-cells property the number of 32-bit cells | |
2495 | required to encode an interrupt specifier. See the OF interrupt | |
2496 | mapping documentation for a detailed description of domains. | |
2497 | ||
2498 | For example, the binding for the OpenPIC interrupt controller | |
2499 | specifies an #interrupt-cells value of 2 to encode the interrupt | |
2500 | number and level/sense information. All interrupt children in an | |
2501 | OpenPIC interrupt domain use 2 cells per interrupt in their interrupts | |
2502 | property. | |
2503 | ||
2504 | The PCI bus binding specifies a #interrupt-cell value of 1 to encode | |
2505 | which interrupt pin (INTA,INTB,INTC,INTD) is used. | |
2506 | ||
2507 | 2) interrupt-parent property | |
2508 | ---------------------------- | |
2509 | ||
2510 | The interrupt-parent property is specified to define an explicit | |
2511 | link between a device node and its interrupt parent in | |
2512 | the interrupt tree. The value of interrupt-parent is the | |
2513 | phandle of the parent node. | |
2514 | ||
2515 | If the interrupt-parent property is not defined for a node, it's | |
2516 | interrupt parent is assumed to be an ancestor in the node's | |
2517 | _device tree_ hierarchy. | |
2518 | ||
2519 | 3) OpenPIC Interrupt Controllers | |
2520 | -------------------------------- | |
2521 | ||
2522 | OpenPIC interrupt controllers require 2 cells to encode | |
2523 | interrupt information. The first cell defines the interrupt | |
2524 | number. The second cell defines the sense and level | |
2525 | information. | |
2526 | ||
2527 | Sense and level information should be encoded as follows: | |
2528 | ||
2529 | 0 = low to high edge sensitive type enabled | |
2530 | 1 = active low level sensitive type enabled | |
2531 | 2 = active high level sensitive type enabled | |
2532 | 3 = high to low edge sensitive type enabled | |
2533 | ||
2534 | 4) ISA Interrupt Controllers | |
2535 | ---------------------------- | |
2536 | ||
2537 | ISA PIC interrupt controllers require 2 cells to encode | |
2538 | interrupt information. The first cell defines the interrupt | |
2539 | number. The second cell defines the sense and level | |
2540 | information. | |
2541 | ||
2542 | ISA PIC interrupt controllers should adhere to the ISA PIC | |
2543 | encodings listed below: | |
2544 | ||
2545 | 0 = active low level sensitive type enabled | |
2546 | 1 = active high level sensitive type enabled | |
2547 | 2 = high to low edge sensitive type enabled | |
2548 | 3 = low to high edge sensitive type enabled | |
2549 | ||
2dff4177 SW |
2550 | IX - Specifying GPIO information for devices |
2551 | ============================================ | |
b7ce3415 AV |
2552 | |
2553 | 1) gpios property | |
2554 | ----------------- | |
2555 | ||
2556 | Nodes that makes use of GPIOs should define them using `gpios' property, | |
2557 | format of which is: <&gpio-controller1-phandle gpio1-specifier | |
2558 | &gpio-controller2-phandle gpio2-specifier | |
2559 | 0 /* holes are permitted, means no GPIO 3 */ | |
2560 | &gpio-controller4-phandle gpio4-specifier | |
2561 | ...>; | |
2562 | ||
2563 | Note that gpio-specifier length is controller dependent. | |
2564 | ||
2565 | gpio-specifier may encode: bank, pin position inside the bank, | |
2566 | whether pin is open-drain and whether pin is logically inverted. | |
2567 | ||
2568 | Example of the node using GPIOs: | |
2569 | ||
2570 | node { | |
2571 | gpios = <&qe_pio_e 18 0>; | |
2572 | }; | |
2573 | ||
2574 | In this example gpio-specifier is "18 0" and encodes GPIO pin number, | |
2575 | and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller. | |
2576 | ||
2577 | 2) gpio-controller nodes | |
2578 | ------------------------ | |
2579 | ||
2580 | Every GPIO controller node must have #gpio-cells property defined, | |
2581 | this information will be used to translate gpio-specifiers. | |
2582 | ||
2583 | Example of two SOC GPIO banks defined as gpio-controller nodes: | |
2584 | ||
2585 | qe_pio_a: gpio-controller@1400 { | |
2586 | #gpio-cells = <2>; | |
2587 | compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; | |
2588 | reg = <0x1400 0x18>; | |
2589 | gpio-controller; | |
2590 | }; | |
2591 | ||
2592 | qe_pio_e: gpio-controller@1460 { | |
2593 | #gpio-cells = <2>; | |
2594 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; | |
2595 | reg = <0x1460 0x18>; | |
2596 | gpio-controller; | |
2597 | }; | |
c125a183 | 2598 | |
2dff4177 SW |
2599 | X - Specifying Device Power Management Information (sleep property) |
2600 | =================================================================== | |
2601 | ||
2602 | Devices on SOCs often have mechanisms for placing devices into low-power | |
2603 | states that are decoupled from the devices' own register blocks. Sometimes, | |
2604 | this information is more complicated than a cell-index property can | |
2605 | reasonably describe. Thus, each device controlled in such a manner | |
2606 | may contain a "sleep" property which describes these connections. | |
2607 | ||
2608 | The sleep property consists of one or more sleep resources, each of | |
2609 | which consists of a phandle to a sleep controller, followed by a | |
2610 | controller-specific sleep specifier of zero or more cells. | |
2611 | ||
2612 | The semantics of what type of low power modes are possible are defined | |
2613 | by the sleep controller. Some examples of the types of low power modes | |
2614 | that may be supported are: | |
2615 | ||
2616 | - Dynamic: The device may be disabled or enabled at any time. | |
2617 | - System Suspend: The device may request to be disabled or remain | |
2618 | awake during system suspend, but will not be disabled until then. | |
2619 | - Permanent: The device is disabled permanently (until the next hard | |
2620 | reset). | |
2621 | ||
2622 | Some devices may share a clock domain with each other, such that they should | |
2623 | only be suspended when none of the devices are in use. Where reasonable, | |
2624 | such nodes should be placed on a virtual bus, where the bus has the sleep | |
2625 | property. If the clock domain is shared among devices that cannot be | |
2626 | reasonably grouped in this manner, then create a virtual sleep controller | |
2627 | (similar to an interrupt nexus, except that defining a standardized | |
2628 | sleep-map should wait until its necessity is demonstrated). | |
2629 | ||
c125a183 DG |
2630 | Appendix A - Sample SOC node for MPC8540 |
2631 | ======================================== | |
2632 | ||
7e72063c | 2633 | soc@e0000000 { |
c125a183 DG |
2634 | #address-cells = <1>; |
2635 | #size-cells = <1>; | |
7e72063c | 2636 | compatible = "fsl,mpc8540-ccsr", "simple-bus"; |
c125a183 | 2637 | device_type = "soc"; |
7e72063c | 2638 | ranges = <0x00000000 0xe0000000 0x00100000> |
7d4b95ae | 2639 | bus-frequency = <0>; |
7e72063c | 2640 | interrupt-parent = <&pic>; |
c125a183 | 2641 | |
c125a183 | 2642 | ethernet@24000 { |
2dff4177 SW |
2643 | #address-cells = <1>; |
2644 | #size-cells = <1>; | |
c125a183 DG |
2645 | device_type = "network"; |
2646 | model = "TSEC"; | |
2dff4177 | 2647 | compatible = "gianfar", "simple-bus"; |
7e72063c SW |
2648 | reg = <0x24000 0x1000>; |
2649 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | |
2650 | interrupts = <29 2 30 2 34 2>; | |
2651 | phy-handle = <&phy0>; | |
2dff4177 SW |
2652 | sleep = <&pmc 00000080>; |
2653 | ranges; | |
2654 | ||
2655 | mdio@24520 { | |
7e72063c | 2656 | reg = <0x24520 0x20>; |
2dff4177 SW |
2657 | compatible = "fsl,gianfar-mdio"; |
2658 | ||
7e72063c SW |
2659 | phy0: ethernet-phy@0 { |
2660 | interrupts = <5 1>; | |
2dff4177 SW |
2661 | reg = <0>; |
2662 | device_type = "ethernet-phy"; | |
2663 | }; | |
2664 | ||
7e72063c SW |
2665 | phy1: ethernet-phy@1 { |
2666 | interrupts = <5 1>; | |
2dff4177 SW |
2667 | reg = <1>; |
2668 | device_type = "ethernet-phy"; | |
2669 | }; | |
2670 | ||
7e72063c SW |
2671 | phy3: ethernet-phy@3 { |
2672 | interrupts = <7 1>; | |
2dff4177 SW |
2673 | reg = <3>; |
2674 | device_type = "ethernet-phy"; | |
2675 | }; | |
2676 | }; | |
c125a183 DG |
2677 | }; |
2678 | ||
2679 | ethernet@25000 { | |
c125a183 DG |
2680 | device_type = "network"; |
2681 | model = "TSEC"; | |
2682 | compatible = "gianfar"; | |
7e72063c SW |
2683 | reg = <0x25000 0x1000>; |
2684 | local-mac-address = [ 00 E0 0C 00 73 01 ]; | |
2685 | interrupts = <13 2 14 2 18 2>; | |
2686 | phy-handle = <&phy1>; | |
2dff4177 | 2687 | sleep = <&pmc 00000040>; |
c125a183 DG |
2688 | }; |
2689 | ||
2690 | ethernet@26000 { | |
c125a183 DG |
2691 | device_type = "network"; |
2692 | model = "FEC"; | |
2693 | compatible = "gianfar"; | |
7e72063c SW |
2694 | reg = <0x26000 0x1000>; |
2695 | local-mac-address = [ 00 E0 0C 00 73 02 ]; | |
2696 | interrupts = <41 2>; | |
2697 | phy-handle = <&phy3>; | |
2dff4177 | 2698 | sleep = <&pmc 00000020>; |
c125a183 DG |
2699 | }; |
2700 | ||
2701 | serial@4500 { | |
2dff4177 SW |
2702 | #address-cells = <1>; |
2703 | #size-cells = <1>; | |
2704 | compatible = "fsl,mpc8540-duart", "simple-bus"; | |
2705 | sleep = <&pmc 00000002>; | |
2706 | ranges; | |
2707 | ||
2708 | serial@4500 { | |
2709 | device_type = "serial"; | |
2710 | compatible = "ns16550"; | |
7e72063c | 2711 | reg = <0x4500 0x100>; |
2dff4177 | 2712 | clock-frequency = <0>; |
7e72063c | 2713 | interrupts = <42 2>; |
2dff4177 SW |
2714 | }; |
2715 | ||
2716 | serial@4600 { | |
2717 | device_type = "serial"; | |
2718 | compatible = "ns16550"; | |
7e72063c | 2719 | reg = <0x4600 0x100>; |
2dff4177 | 2720 | clock-frequency = <0>; |
7e72063c | 2721 | interrupts = <42 2>; |
2dff4177 | 2722 | }; |
c125a183 DG |
2723 | }; |
2724 | ||
7e72063c | 2725 | pic: pic@40000 { |
c125a183 DG |
2726 | interrupt-controller; |
2727 | #address-cells = <0>; | |
7e72063c SW |
2728 | #interrupt-cells = <2>; |
2729 | reg = <0x40000 0x40000>; | |
c125a183 DG |
2730 | compatible = "chrp,open-pic"; |
2731 | device_type = "open-pic"; | |
c125a183 DG |
2732 | }; |
2733 | ||
2734 | i2c@3000 { | |
7e72063c SW |
2735 | interrupts = <43 2>; |
2736 | reg = <0x3000 0x100>; | |
c125a183 DG |
2737 | compatible = "fsl-i2c"; |
2738 | dfsrr; | |
2dff4177 | 2739 | sleep = <&pmc 00000004>; |
c125a183 DG |
2740 | }; |
2741 | ||
2dff4177 SW |
2742 | pmc: power@e0070 { |
2743 | compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc"; | |
7e72063c | 2744 | reg = <0xe0070 0x20>; |
2dff4177 | 2745 | }; |
c125a183 | 2746 | }; |