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12458ea0 AG |
1 | PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator) |
2 | ||
3 | Device nodes needed for operation of the ppc440spe-adma driver | |
4 | are specified hereby. These are I2O/DMA, DMA and XOR nodes | |
5 | for DMA engines and Memory Queue Module node. The latter is used | |
6 | by ADMA driver for configuration of RAID-6 H/W capabilities of | |
7 | the PPC440SPe. In addition to the nodes and properties described | |
8 | below, the ranges property of PLB node must specify ranges for | |
9 | DMA devices. | |
10 | ||
11 | i) The I2O node | |
12 | ||
13 | Required properties: | |
14 | ||
15 | - compatible : "ibm,i2o-440spe"; | |
16 | - reg : <registers mapping> | |
17 | - dcr-reg : <DCR registers range> | |
18 | ||
19 | Example: | |
20 | ||
21 | I2O: i2o@400100000 { | |
22 | compatible = "ibm,i2o-440spe"; | |
23 | reg = <0x00000004 0x00100000 0x100>; | |
24 | dcr-reg = <0x060 0x020>; | |
25 | }; | |
26 | ||
27 | ||
28 | ii) The DMA node | |
29 | ||
30 | Required properties: | |
31 | ||
32 | - compatible : "ibm,dma-440spe"; | |
33 | - cell-index : 1 cell, hardware index of the DMA engine | |
34 | (typically 0x0 and 0x1 for DMA0 and DMA1) | |
35 | - reg : <registers mapping> | |
36 | - dcr-reg : <DCR registers range> | |
37 | - interrupts : <interrupt mapping for DMA0/1 interrupts sources: | |
38 | 2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0) | |
39 | and DMA Error IRQ (on UIC1). The latter is common | |
40 | for both DMA engines>. | |
41 | - interrupt-parent : needed for interrupt mapping | |
42 | ||
43 | Example: | |
44 | ||
45 | DMA0: dma0@400100100 { | |
46 | compatible = "ibm,dma-440spe"; | |
47 | cell-index = <0>; | |
48 | reg = <0x00000004 0x00100100 0x100>; | |
49 | dcr-reg = <0x060 0x020>; | |
50 | interrupt-parent = <&DMA0>; | |
51 | interrupts = <0 1>; | |
52 | #interrupt-cells = <1>; | |
53 | #address-cells = <0>; | |
54 | #size-cells = <0>; | |
55 | interrupt-map = < | |
56 | 0 &UIC0 0x14 4 | |
57 | 1 &UIC1 0x16 4>; | |
58 | }; | |
59 | ||
60 | ||
61 | iii) XOR Accelerator node | |
62 | ||
63 | Required properties: | |
64 | ||
65 | - compatible : "amcc,xor-accelerator"; | |
66 | - reg : <registers mapping> | |
67 | - interrupts : <interrupt mapping for XOR interrupt source> | |
68 | - interrupt-parent : for interrupt mapping | |
69 | ||
70 | Example: | |
71 | ||
72 | xor-accel@400200000 { | |
73 | compatible = "amcc,xor-accelerator"; | |
74 | reg = <0x00000004 0x00200000 0x400>; | |
75 | interrupt-parent = <&UIC1>; | |
76 | interrupts = <0x1f 4>; | |
77 | }; | |
78 | ||
79 | ||
80 | iv) Memory Queue Module node | |
81 | ||
82 | Required properties: | |
83 | ||
84 | - compatible : "ibm,mq-440spe"; | |
85 | - dcr-reg : <DCR registers range> | |
86 | ||
87 | Example: | |
88 | ||
89 | MQ0: mq { | |
90 | compatible = "ibm,mq-440spe"; | |
91 | dcr-reg = <0x040 0x020>; | |
92 | }; | |
93 |