[deliverable/linux.git] / arch / alpha / include / asm / pci.h

#ifndef __ALPHA_PCI_H
#define __ALPHA_PCI_H

#ifdef __KERNEL__

#include <linux/spinlock.h>
#include <linux/dma-mapping.h>
#include <asm/scatterlist.h>
#include <asm/machvec.h>
#include <asm-generic/pci-bridge.h>

/*
 * The following structure is used to manage multiple PCI busses.
 */

struct pci_dev;
struct pci_bus;
struct resource;
struct pci_iommu_arena;
struct page;

/* A controller.  Used to manage multiple PCI busses.  */

struct pci_controller {
	struct pci_controller *next;
        struct pci_bus *bus;
	struct resource *io_space;
	struct resource *mem_space;

	/* The following are for reporting to userland.  The invariant is
	   that if we report a BWX-capable dense memory, we do not report
	   a sparse memory at all, even if it exists.  */
	unsigned long sparse_mem_base;
	unsigned long dense_mem_base;
	unsigned long sparse_io_base;
	unsigned long dense_io_base;

	/* This one's for the kernel only.  It's in KSEG somewhere.  */
	unsigned long config_space_base;

	unsigned int index;
	/* For compatibility with current (as of July 2003) pciutils
	   and XFree86. Eventually will be removed. */
	unsigned int need_domain_info;

	struct pci_iommu_arena *sg_pci;
	struct pci_iommu_arena *sg_isa;

	void *sysdata;
};

/* Override the logic in pci_scan_bus for skipping already-configured
   bus numbers.  */

#define pcibios_assign_all_busses()	1

#define PCIBIOS_MIN_IO		alpha_mv.min_io_address
#define PCIBIOS_MIN_MEM		alpha_mv.min_mem_address

extern void pcibios_set_master(struct pci_dev *dev);

/* IOMMU controls.  */

/* The PCI address space does not equal the physical memory address space.
   The networking and block device layers use this boolean for bounce buffer
   decisions.  */
#define PCI_DMA_BUS_IS_PHYS  0

#ifdef CONFIG_PCI

/* implement the pci_ DMA API in terms of the generic device dma_ one */
#include <asm-generic/pci-dma-compat.h>

static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	unsigned long cacheline_size;
	u8 byte;

	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	if (byte == 0)
		cacheline_size = 1024;
	else
		cacheline_size = (int) byte * 4;

	*strat = PCI_DMA_BURST_BOUNDARY;
	*strategy_parameter = cacheline_size;
}
#endif

/* TODO: integrate with include/asm-generic/pci.h ? */
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	return channel ? 15 : 14;
}

#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index

static inline int pci_proc_domain(struct pci_bus *bus)
{
	struct pci_controller *hose = bus->sysdata;
	return hose->need_domain_info;
}

#endif /* __KERNEL__ */

/* Values for the `which' argument to sys_pciconfig_iobase.  */
#define IOBASE_HOSE		0
#define IOBASE_SPARSE_MEM	1
#define IOBASE_DENSE_MEM	2
#define IOBASE_SPARSE_IO	3
#define IOBASE_DENSE_IO		4
#define IOBASE_ROOT_BUS		5
#define IOBASE_FROM_HOSE	0x10000

extern struct pci_dev *isa_bridge;

extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
			   size_t count);
extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
			    size_t count);
extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
				      struct vm_area_struct *vma,
				      enum pci_mmap_state mmap_state);
extern void pci_adjust_legacy_attr(struct pci_bus *bus,
				   enum pci_mmap_state mmap_type);
#define HAVE_PCI_LEGACY	1

extern int pci_create_resource_files(struct pci_dev *dev);
extern void pci_remove_resource_files(struct pci_dev *dev);

#endif /* __ALPHA_PCI_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ALPHA_PCI_H
	2	#define __ALPHA_PCI_H
	3
	4	#ifdef __KERNEL__
	5
	6	#include <linux/spinlock.h>
7c53664d	7	#include <linux/dma-mapping.h>
1da177e4 LT	8	#include <asm/scatterlist.h>
1da177e4 LT	9	#include <asm/machvec.h>
151d16d5	10	#include <asm-generic/pci-bridge.h>
1da177e4 LT	11
	12	/*
	13	* The following structure is used to manage multiple PCI busses.
	14	*/
	15
	16	struct pci_dev;
	17	struct pci_bus;
	18	struct resource;
	19	struct pci_iommu_arena;
	20	struct page;
	21
	22	/* A controller. Used to manage multiple PCI busses. */
	23
	24	struct pci_controller {
	25	struct pci_controller *next;
	26	struct pci_bus *bus;
	27	struct resource *io_space;
	28	struct resource *mem_space;
	29
	30	/* The following are for reporting to userland. The invariant is
	31	that if we report a BWX-capable dense memory, we do not report
	32	a sparse memory at all, even if it exists. */
	33	unsigned long sparse_mem_base;
	34	unsigned long dense_mem_base;
	35	unsigned long sparse_io_base;
	36	unsigned long dense_io_base;
	37
	38	/* This one's for the kernel only. It's in KSEG somewhere. */
	39	unsigned long config_space_base;
	40
	41	unsigned int index;
	42	/* For compatibility with current (as of July 2003) pciutils
	43	and XFree86. Eventually will be removed. */
	44	unsigned int need_domain_info;
	45
	46	struct pci_iommu_arena *sg_pci;
	47	struct pci_iommu_arena *sg_isa;
	48
	49	void *sysdata;
	50	};
	51
	52	/* Override the logic in pci_scan_bus for skipping already-configured
	53	bus numbers. */
	54
	55	#define pcibios_assign_all_busses() 1
1da177e4 LT	56
	57	#define PCIBIOS_MIN_IO alpha_mv.min_io_address
	58	#define PCIBIOS_MIN_MEM alpha_mv.min_mem_address
	59
	60	extern void pcibios_set_master(struct pci_dev *dev);
	61
1da177e4 LT	62	/* IOMMU controls. */
	63
	64	/* The PCI address space does not equal the physical memory address space.
	65	The networking and block device layers use this boolean for bounce buffer
	66	decisions. */
	67	#define PCI_DMA_BUS_IS_PHYS 0
	68
c186caca	69	#ifdef CONFIG_PCI
1da177e4	70
c186caca FT	71	/* implement the pci_ DMA API in terms of the generic device dma_ one */
c186caca FT	72	#include <asm-generic/pci-dma-compat.h>
1da177e4	73
e24c2d96 DM	74	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	75	enum pci_dma_burst_strategy *strat,
	76	unsigned long *strategy_parameter)
	77	{
	78	unsigned long cacheline_size;
	79	u8 byte;
	80
	81	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	82	if (byte == 0)
	83	cacheline_size = 1024;
	84	else
	85	cacheline_size = (int) byte * 4;
	86
	87	*strat = PCI_DMA_BURST_BOUNDARY;
	88	*strategy_parameter = cacheline_size;
	89	}
bb4a61b6	90	#endif
e24c2d96	91
1da177e4 LT	92	/* TODO: integrate with include/asm-generic/pci.h ? */
	93	static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
	94	{
	95	return channel ? 15 : 14;
	96	}
	97
1da177e4 LT	98	#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
	99
	100	static inline int pci_proc_domain(struct pci_bus *bus)
	101	{
	102	struct pci_controller *hose = bus->sysdata;
	103	return hose->need_domain_info;
	104	}
	105
1da177e4 LT	106	#endif /* __KERNEL__ */
	107
	108	/* Values for the `which' argument to sys_pciconfig_iobase. */
	109	#define IOBASE_HOSE 0
	110	#define IOBASE_SPARSE_MEM 1
	111	#define IOBASE_DENSE_MEM 2
	112	#define IOBASE_SPARSE_IO 3
	113	#define IOBASE_DENSE_IO 4
	114	#define IOBASE_ROOT_BUS 5
	115	#define IOBASE_FROM_HOSE 0x10000
	116
8255cf35 AB	117	extern struct pci_dev *isa_bridge;
8255cf35 AB	118
10a0ef39 IK	119	extern int pci_legacy_read(struct pci_bus bus, loff_t port, u32 val,
	120	size_t count);
	121	extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
	122	size_t count);
	123	extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
	124	struct vm_area_struct *vma,
	125	enum pci_mmap_state mmap_state);
	126	extern void pci_adjust_legacy_attr(struct pci_bus *bus,
	127	enum pci_mmap_state mmap_type);
	128	#define HAVE_PCI_LEGACY 1
	129
	130	extern int pci_create_resource_files(struct pci_dev *dev);
	131	extern void pci_remove_resource_files(struct pci_dev *dev);
	132
1da177e4	133	#endif /* __ALPHA_PCI_H */