Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Alpha specific irq code. | |
3 | */ | |
4 | ||
1da177e4 LT |
5 | #include <linux/init.h> |
6 | #include <linux/sched.h> | |
7 | #include <linux/irq.h> | |
8 | #include <linux/kernel_stat.h> | |
cff52daf | 9 | #include <linux/module.h> |
1da177e4 LT |
10 | |
11 | #include <asm/machvec.h> | |
12 | #include <asm/dma.h> | |
13 | ||
14 | #include "proto.h" | |
15 | #include "irq_impl.h" | |
16 | ||
17 | /* Hack minimum IPL during interrupt processing for broken hardware. */ | |
18 | #ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK | |
19 | int __min_ipl; | |
cff52daf | 20 | EXPORT_SYMBOL(__min_ipl); |
1da177e4 LT |
21 | #endif |
22 | ||
23 | /* | |
24 | * Performance counter hook. A module can override this to | |
25 | * do something useful. | |
26 | */ | |
27 | static void | |
28 | dummy_perf(unsigned long vector, struct pt_regs *regs) | |
29 | { | |
30 | irq_err_count++; | |
31 | printk(KERN_CRIT "Performance counter interrupt!\n"); | |
32 | } | |
33 | ||
34 | void (*perf_irq)(unsigned long, struct pt_regs *) = dummy_perf; | |
cff52daf | 35 | EXPORT_SYMBOL(perf_irq); |
1da177e4 LT |
36 | |
37 | /* | |
38 | * The main interrupt entry point. | |
39 | */ | |
40 | ||
41 | asmlinkage void | |
42 | do_entInt(unsigned long type, unsigned long vector, | |
43 | unsigned long la_ptr, struct pt_regs *regs) | |
44 | { | |
7ca56053 | 45 | struct pt_regs *old_regs; |
1da177e4 LT |
46 | switch (type) { |
47 | case 0: | |
48 | #ifdef CONFIG_SMP | |
49 | handle_ipi(regs); | |
50 | return; | |
51 | #else | |
52 | irq_err_count++; | |
53 | printk(KERN_CRIT "Interprocessor interrupt? " | |
54 | "You must be kidding!\n"); | |
55 | #endif | |
56 | break; | |
57 | case 1: | |
3dbb8c62 | 58 | old_regs = set_irq_regs(regs); |
1da177e4 LT |
59 | #ifdef CONFIG_SMP |
60 | { | |
61 | long cpu; | |
4a89a04f IK |
62 | |
63 | local_irq_disable(); | |
1da177e4 LT |
64 | smp_percpu_timer_interrupt(regs); |
65 | cpu = smp_processor_id(); | |
66 | if (cpu != boot_cpuid) { | |
0b0f0b1c | 67 | kstat_incr_irqs_this_cpu(RTC_IRQ, irq_to_desc(RTC_IRQ)); |
1da177e4 | 68 | } else { |
3dbb8c62 | 69 | handle_irq(RTC_IRQ); |
1da177e4 LT |
70 | } |
71 | } | |
72 | #else | |
3dbb8c62 | 73 | handle_irq(RTC_IRQ); |
1da177e4 | 74 | #endif |
3dbb8c62 | 75 | set_irq_regs(old_regs); |
1da177e4 LT |
76 | return; |
77 | case 2: | |
4fa1970a AV |
78 | old_regs = set_irq_regs(regs); |
79 | alpha_mv.machine_check(vector, la_ptr); | |
80 | set_irq_regs(old_regs); | |
1da177e4 LT |
81 | return; |
82 | case 3: | |
7ca56053 AV |
83 | old_regs = set_irq_regs(regs); |
84 | alpha_mv.device_interrupt(vector); | |
85 | set_irq_regs(old_regs); | |
1da177e4 LT |
86 | return; |
87 | case 4: | |
88 | perf_irq(la_ptr, regs); | |
89 | return; | |
90 | default: | |
91 | printk(KERN_CRIT "Hardware intr %ld %lx? Huh?\n", | |
92 | type, vector); | |
93 | } | |
94 | printk(KERN_CRIT "PC = %016lx PS=%04lx\n", regs->pc, regs->ps); | |
95 | } | |
96 | ||
97 | void __init | |
98 | common_init_isa_dma(void) | |
99 | { | |
100 | outb(0, DMA1_RESET_REG); | |
101 | outb(0, DMA2_RESET_REG); | |
102 | outb(0, DMA1_CLR_MASK_REG); | |
103 | outb(0, DMA2_CLR_MASK_REG); | |
104 | } | |
105 | ||
106 | void __init | |
107 | init_IRQ(void) | |
108 | { | |
109 | /* Just in case the platform init_irq() causes interrupts/mchecks | |
110 | (as is the case with RAWHIDE, at least). */ | |
111 | wrent(entInt, 0); | |
112 | ||
113 | alpha_mv.init_irq(); | |
114 | } | |
115 | ||
116 | /* | |
117 | * machine error checks | |
118 | */ | |
119 | #define MCHK_K_TPERR 0x0080 | |
120 | #define MCHK_K_TCPERR 0x0082 | |
121 | #define MCHK_K_HERR 0x0084 | |
122 | #define MCHK_K_ECC_C 0x0086 | |
123 | #define MCHK_K_ECC_NC 0x0088 | |
124 | #define MCHK_K_OS_BUGCHECK 0x008A | |
125 | #define MCHK_K_PAL_BUGCHECK 0x0090 | |
126 | ||
127 | #ifndef CONFIG_SMP | |
128 | struct mcheck_info __mcheck_info; | |
129 | #endif | |
130 | ||
131 | void | |
132 | process_mcheck_info(unsigned long vector, unsigned long la_ptr, | |
4fa1970a | 133 | const char *machine, int expected) |
1da177e4 LT |
134 | { |
135 | struct el_common *mchk_header; | |
136 | const char *reason; | |
137 | ||
138 | /* | |
139 | * See if the machine check is due to a badaddr() and if so, | |
140 | * ignore it. | |
141 | */ | |
142 | ||
143 | #ifdef CONFIG_VERBOSE_MCHECK | |
144 | if (alpha_verbose_mcheck > 1) { | |
145 | printk(KERN_CRIT "%s machine check %s\n", machine, | |
146 | expected ? "expected." : "NOT expected!!!"); | |
147 | } | |
148 | #endif | |
149 | ||
150 | if (expected) { | |
151 | int cpu = smp_processor_id(); | |
152 | mcheck_expected(cpu) = 0; | |
153 | mcheck_taken(cpu) = 1; | |
154 | return; | |
155 | } | |
156 | ||
157 | mchk_header = (struct el_common *)la_ptr; | |
158 | ||
159 | printk(KERN_CRIT "%s machine check: vector=0x%lx pc=0x%lx code=0x%x\n", | |
4fa1970a | 160 | machine, vector, get_irq_regs()->pc, mchk_header->code); |
1da177e4 LT |
161 | |
162 | switch (mchk_header->code) { | |
163 | /* Machine check reasons. Defined according to PALcode sources. */ | |
164 | case 0x80: reason = "tag parity error"; break; | |
165 | case 0x82: reason = "tag control parity error"; break; | |
166 | case 0x84: reason = "generic hard error"; break; | |
167 | case 0x86: reason = "correctable ECC error"; break; | |
168 | case 0x88: reason = "uncorrectable ECC error"; break; | |
169 | case 0x8A: reason = "OS-specific PAL bugcheck"; break; | |
170 | case 0x90: reason = "callsys in kernel mode"; break; | |
171 | case 0x96: reason = "i-cache read retryable error"; break; | |
172 | case 0x98: reason = "processor detected hard error"; break; | |
173 | ||
174 | /* System specific (these are for Alcor, at least): */ | |
175 | case 0x202: reason = "system detected hard error"; break; | |
176 | case 0x203: reason = "system detected uncorrectable ECC error"; break; | |
177 | case 0x204: reason = "SIO SERR occurred on PCI bus"; break; | |
178 | case 0x205: reason = "parity error detected by core logic"; break; | |
179 | case 0x206: reason = "SIO IOCHK occurred on ISA bus"; break; | |
180 | case 0x207: reason = "non-existent memory error"; break; | |
181 | case 0x208: reason = "MCHK_K_DCSR"; break; | |
182 | case 0x209: reason = "PCI SERR detected"; break; | |
183 | case 0x20b: reason = "PCI data parity error detected"; break; | |
184 | case 0x20d: reason = "PCI address parity error detected"; break; | |
185 | case 0x20f: reason = "PCI master abort error"; break; | |
186 | case 0x211: reason = "PCI target abort error"; break; | |
187 | case 0x213: reason = "scatter/gather PTE invalid error"; break; | |
188 | case 0x215: reason = "flash ROM write error"; break; | |
189 | case 0x217: reason = "IOA timeout detected"; break; | |
190 | case 0x219: reason = "IOCHK#, EISA add-in board parity or other catastrophic error"; break; | |
191 | case 0x21b: reason = "EISA fail-safe timer timeout"; break; | |
192 | case 0x21d: reason = "EISA bus time-out"; break; | |
193 | case 0x21f: reason = "EISA software generated NMI"; break; | |
194 | case 0x221: reason = "unexpected ev5 IRQ[3] interrupt"; break; | |
195 | default: reason = "unknown"; break; | |
196 | } | |
197 | ||
198 | printk(KERN_CRIT "machine check type: %s%s\n", | |
199 | reason, mchk_header->retry ? " (retryable)" : ""); | |
200 | ||
4fa1970a | 201 | dik_show_regs(get_irq_regs(), NULL); |
1da177e4 LT |
202 | |
203 | #ifdef CONFIG_VERBOSE_MCHECK | |
204 | if (alpha_verbose_mcheck > 1) { | |
205 | /* Dump the logout area to give all info. */ | |
206 | unsigned long *ptr = (unsigned long *)la_ptr; | |
207 | long i; | |
208 | for (i = 0; i < mchk_header->size / sizeof(long); i += 2) { | |
209 | printk(KERN_CRIT " +%8lx %016lx %016lx\n", | |
210 | i*sizeof(long), ptr[i], ptr[i+1]); | |
211 | } | |
212 | } | |
213 | #endif /* CONFIG_VERBOSE_MCHECK */ | |
214 | } | |
215 | ||
216 | /* | |
217 | * The special RTC interrupt type. The interrupt itself was | |
218 | * processed by PALcode, and comes in via entInt vector 1. | |
219 | */ | |
220 | ||
221 | static void rtc_enable_disable(unsigned int irq) { } | |
222 | static unsigned int rtc_startup(unsigned int irq) { return 0; } | |
223 | ||
224 | struct irqaction timer_irqaction = { | |
225 | .handler = timer_interrupt, | |
d18ecedc | 226 | .flags = IRQF_DISABLED, |
1da177e4 LT |
227 | .name = "timer", |
228 | }; | |
229 | ||
44377f62 | 230 | static struct irq_chip rtc_irq_type = { |
1da177e4 LT |
231 | .typename = "RTC", |
232 | .startup = rtc_startup, | |
233 | .shutdown = rtc_enable_disable, | |
234 | .enable = rtc_enable_disable, | |
235 | .disable = rtc_enable_disable, | |
236 | .ack = rtc_enable_disable, | |
237 | .end = rtc_enable_disable, | |
238 | }; | |
239 | ||
240 | void __init | |
241 | init_rtc_irq(void) | |
242 | { | |
243 | irq_desc[RTC_IRQ].status = IRQ_DISABLED; | |
d1bef4ed | 244 | irq_desc[RTC_IRQ].chip = &rtc_irq_type; |
1da177e4 LT |
245 | setup_irq(RTC_IRQ, &timer_irqaction); |
246 | } | |
247 | ||
248 | /* Dummy irqactions. */ | |
249 | struct irqaction isa_cascade_irqaction = { | |
250 | .handler = no_action, | |
251 | .name = "isa-cascade" | |
252 | }; | |
253 | ||
254 | struct irqaction timer_cascade_irqaction = { | |
255 | .handler = no_action, | |
256 | .name = "timer-cascade" | |
257 | }; | |
258 | ||
259 | struct irqaction halt_switch_irqaction = { | |
260 | .handler = no_action, | |
261 | .name = "halt-switch" | |
262 | }; |