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1da177e4 LT |
1 | /* |
2 | * linux/arch/alpha/kernel/sys_cabriolet.c | |
3 | * | |
4 | * Copyright (C) 1995 David A Rusling | |
5 | * Copyright (C) 1996 Jay A Estabrook | |
6 | * Copyright (C) 1998, 1999, 2000 Richard Henderson | |
7 | * | |
8 | * Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164, | |
9 | * PC164 and LX164. | |
10 | */ | |
11 | ||
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/types.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/bitops.h> | |
19 | ||
20 | #include <asm/ptrace.h> | |
1da177e4 LT |
21 | #include <asm/dma.h> |
22 | #include <asm/irq.h> | |
23 | #include <asm/mmu_context.h> | |
24 | #include <asm/io.h> | |
25 | #include <asm/pgtable.h> | |
26 | #include <asm/core_apecs.h> | |
27 | #include <asm/core_cia.h> | |
28 | #include <asm/core_lca.h> | |
29 | #include <asm/tlbflush.h> | |
30 | ||
31 | #include "proto.h" | |
32 | #include "irq_impl.h" | |
33 | #include "pci_impl.h" | |
34 | #include "machvec_impl.h" | |
59b25ed9 | 35 | #include "pc873xx.h" |
1da177e4 LT |
36 | |
37 | /* Note mask bit is true for DISABLED irqs. */ | |
38 | static unsigned long cached_irq_mask = ~0UL; | |
39 | ||
40 | static inline void | |
41 | cabriolet_update_irq_hw(unsigned int irq, unsigned long mask) | |
42 | { | |
43 | int ofs = (irq - 16) / 8; | |
44 | outb(mask >> (16 + ofs * 8), 0x804 + ofs); | |
45 | } | |
46 | ||
47 | static inline void | |
118b4691 | 48 | cabriolet_enable_irq(struct irq_data *d) |
1da177e4 | 49 | { |
118b4691 | 50 | cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); |
1da177e4 LT |
51 | } |
52 | ||
53 | static void | |
118b4691 | 54 | cabriolet_disable_irq(struct irq_data *d) |
1da177e4 | 55 | { |
118b4691 | 56 | cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); |
1da177e4 LT |
57 | } |
58 | ||
44377f62 | 59 | static struct irq_chip cabriolet_irq_type = { |
8ab1221c | 60 | .name = "CABRIOLET", |
118b4691 TG |
61 | .irq_unmask = cabriolet_enable_irq, |
62 | .irq_mask = cabriolet_disable_irq, | |
63 | .irq_mask_ack = cabriolet_disable_irq, | |
1da177e4 LT |
64 | }; |
65 | ||
66 | static void | |
7ca56053 | 67 | cabriolet_device_interrupt(unsigned long v) |
1da177e4 LT |
68 | { |
69 | unsigned long pld; | |
70 | unsigned int i; | |
71 | ||
72 | /* Read the interrupt summary registers */ | |
73 | pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16); | |
74 | ||
75 | /* | |
76 | * Now for every possible bit set, work through them and call | |
77 | * the appropriate interrupt handler. | |
78 | */ | |
79 | while (pld) { | |
80 | i = ffz(~pld); | |
81 | pld &= pld - 1; /* clear least bit set */ | |
82 | if (i == 4) { | |
7ca56053 | 83 | isa_device_interrupt(v); |
1da177e4 | 84 | } else { |
3dbb8c62 | 85 | handle_irq(16 + i); |
1da177e4 LT |
86 | } |
87 | } | |
88 | } | |
89 | ||
90 | static void __init | |
7ca56053 | 91 | common_init_irq(void (*srm_dev_int)(unsigned long v)) |
1da177e4 LT |
92 | { |
93 | init_i8259a_irqs(); | |
94 | ||
95 | if (alpha_using_srm) { | |
96 | alpha_mv.device_interrupt = srm_dev_int; | |
97 | init_srm_irqs(35, 0); | |
98 | } | |
99 | else { | |
100 | long i; | |
101 | ||
102 | outb(0xff, 0x804); | |
103 | outb(0xff, 0x805); | |
104 | outb(0xff, 0x806); | |
105 | ||
106 | for (i = 16; i < 35; ++i) { | |
a9eb076b TG |
107 | irq_set_chip_and_handler(i, &cabriolet_irq_type, |
108 | handle_level_irq); | |
118b4691 | 109 | irq_set_status_flags(i, IRQ_LEVEL); |
1da177e4 LT |
110 | } |
111 | } | |
112 | ||
113 | common_init_isa_dma(); | |
114 | setup_irq(16+4, &isa_cascade_irqaction); | |
115 | } | |
116 | ||
117 | #ifndef CONFIG_ALPHA_PC164 | |
118 | static void __init | |
119 | cabriolet_init_irq(void) | |
120 | { | |
121 | common_init_irq(srm_device_interrupt); | |
122 | } | |
123 | #endif | |
124 | ||
125 | #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164) | |
126 | /* In theory, the PC164 has the same interrupt hardware as the other | |
127 | Cabriolet based systems. However, something got screwed up late | |
128 | in the development cycle which broke the interrupt masking hardware. | |
129 | Repeat, it is not possible to mask and ack interrupts. At all. | |
130 | ||
131 | In an attempt to work around this, while processing interrupts, | |
132 | we do not allow the IPL to drop below what it is currently. This | |
133 | prevents the possibility of recursion. | |
134 | ||
135 | ??? Another option might be to force all PCI devices to use edge | |
136 | triggered rather than level triggered interrupts. That might be | |
137 | too invasive though. */ | |
138 | ||
139 | static void | |
7ca56053 | 140 | pc164_srm_device_interrupt(unsigned long v) |
1da177e4 LT |
141 | { |
142 | __min_ipl = getipl(); | |
7ca56053 | 143 | srm_device_interrupt(v); |
1da177e4 LT |
144 | __min_ipl = 0; |
145 | } | |
146 | ||
147 | static void | |
7ca56053 | 148 | pc164_device_interrupt(unsigned long v) |
1da177e4 LT |
149 | { |
150 | __min_ipl = getipl(); | |
7ca56053 | 151 | cabriolet_device_interrupt(v); |
1da177e4 LT |
152 | __min_ipl = 0; |
153 | } | |
154 | ||
155 | static void __init | |
156 | pc164_init_irq(void) | |
157 | { | |
158 | common_init_irq(pc164_srm_device_interrupt); | |
159 | } | |
160 | #endif | |
161 | ||
162 | /* | |
163 | * The EB66+ is very similar to the EB66 except that it does not have | |
164 | * the on-board NCR and Tulip chips. In the code below, I have used | |
165 | * slot number to refer to the id select line and *not* the slot | |
166 | * number used in the EB66+ documentation. However, in the table, | |
167 | * I've given the slot number, the id select line and the Jxx number | |
168 | * that's printed on the board. The interrupt pins from the PCI slots | |
169 | * are wired into 3 interrupt summary registers at 0x804, 0x805 and | |
170 | * 0x806 ISA. | |
171 | * | |
172 | * In the table, -1 means don't assign an IRQ number. This is usually | |
173 | * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip. | |
174 | */ | |
175 | ||
176 | static inline int __init | |
d5341942 | 177 | eb66p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 LT |
178 | { |
179 | static char irq_tab[5][5] __initdata = { | |
180 | /*INT INTA INTB INTC INTD */ | |
181 | {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */ | |
182 | {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */ | |
183 | { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ | |
184 | {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */ | |
185 | {16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */ | |
186 | }; | |
187 | const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5; | |
188 | return COMMON_TABLE_LOOKUP; | |
189 | } | |
190 | ||
191 | ||
192 | /* | |
193 | * The AlphaPC64 is very similar to the EB66+ except that its slots | |
194 | * are numbered differently. In the code below, I have used slot | |
195 | * number to refer to the id select line and *not* the slot number | |
196 | * used in the AlphaPC64 documentation. However, in the table, I've | |
197 | * given the slot number, the id select line and the Jxx number that's | |
198 | * printed on the board. The interrupt pins from the PCI slots are | |
199 | * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806 | |
200 | * ISA. | |
201 | * | |
202 | * In the table, -1 means don't assign an IRQ number. This is usually | |
203 | * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip. | |
204 | */ | |
205 | ||
206 | static inline int __init | |
d5341942 | 207 | cabriolet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 LT |
208 | { |
209 | static char irq_tab[5][5] __initdata = { | |
210 | /*INT INTA INTB INTC INTD */ | |
211 | { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */ | |
212 | { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */ | |
213 | { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */ | |
214 | { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ | |
215 | { 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */ | |
216 | }; | |
217 | const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5; | |
218 | return COMMON_TABLE_LOOKUP; | |
219 | } | |
220 | ||
59b25ed9 ML |
221 | static inline void __init |
222 | cabriolet_enable_ide(void) | |
223 | { | |
224 | if (pc873xx_probe() == -1) { | |
225 | printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n"); | |
226 | } else { | |
227 | printk(KERN_INFO "Found %s Super IO chip at 0x%x\n", | |
228 | pc873xx_get_model(), pc873xx_get_base()); | |
229 | ||
230 | pc873xx_enable_ide(); | |
231 | } | |
232 | } | |
233 | ||
1da177e4 LT |
234 | static inline void __init |
235 | cabriolet_init_pci(void) | |
236 | { | |
237 | common_init_pci(); | |
59b25ed9 | 238 | cabriolet_enable_ide(); |
1da177e4 LT |
239 | } |
240 | ||
241 | static inline void __init | |
242 | cia_cab_init_pci(void) | |
243 | { | |
244 | cia_init_pci(); | |
59b25ed9 | 245 | cabriolet_enable_ide(); |
1da177e4 LT |
246 | } |
247 | ||
248 | /* | |
249 | * The PC164 and LX164 have 19 PCI interrupts, four from each of the four | |
250 | * PCI slots, the SIO, PCI/IDE, and USB. | |
251 | * | |
252 | * Each of the interrupts can be individually masked. This is | |
253 | * accomplished by setting the appropriate bit in the mask register. | |
254 | * A bit is set by writing a "1" to the desired position in the mask | |
255 | * register and cleared by writing a "0". There are 3 mask registers | |
256 | * located at ISA address 804h, 805h and 806h. | |
257 | * | |
258 | * An I/O read at ISA address 804h, 805h, 806h will return the | |
259 | * state of the 11 PCI interrupts and not the state of the MASKED | |
260 | * interrupts. | |
261 | * | |
262 | * Note: A write to I/O 804h, 805h, and 806h the mask register will be | |
263 | * updated. | |
264 | * | |
265 | * | |
266 | * ISA DATA<7:0> | |
267 | * ISA +--------------------------------------------------------------+ | |
268 | * ADDRESS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | |
269 | * +==============================================================+ | |
270 | * 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 | | |
271 | * +--------------------------------------------------------------+ | |
272 | * 0x805 | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 | | |
273 | * +--------------------------------------------------------------+ | |
274 | * 0x806 | Rsrv | Rsrv | Rsrv | Rsrv | Rsrv |INTD3 | INTD2 | INTD1 | | |
275 | * +--------------------------------------------------------------+ | |
276 | * * Rsrv = reserved bits | |
277 | * Note: The mask register is write-only. | |
278 | * | |
279 | * IdSel | |
280 | * 5 32 bit PCI option slot 2 | |
281 | * 6 64 bit PCI option slot 0 | |
282 | * 7 64 bit PCI option slot 1 | |
283 | * 8 Saturn I/O | |
284 | * 9 32 bit PCI option slot 3 | |
285 | * 10 USB | |
286 | * 11 IDE | |
287 | * | |
288 | */ | |
289 | ||
290 | static inline int __init | |
d5341942 | 291 | alphapc164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 LT |
292 | { |
293 | static char irq_tab[7][5] __initdata = { | |
294 | /*INT INTA INTB INTC INTD */ | |
295 | { 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */ | |
296 | { 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */ | |
297 | { 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */ | |
298 | { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ | |
299 | { 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */ | |
300 | { 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */ | |
301 | { 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */ | |
302 | }; | |
303 | const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5; | |
304 | return COMMON_TABLE_LOOKUP; | |
305 | } | |
306 | ||
307 | static inline void __init | |
308 | alphapc164_init_pci(void) | |
309 | { | |
310 | cia_init_pci(); | |
311 | SMC93x_Init(); | |
312 | } | |
313 | ||
314 | ||
315 | /* | |
316 | * The System Vector | |
317 | */ | |
318 | ||
319 | #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET) | |
320 | struct alpha_machine_vector cabriolet_mv __initmv = { | |
321 | .vector_name = "Cabriolet", | |
322 | DO_EV4_MMU, | |
323 | DO_DEFAULT_RTC, | |
324 | DO_APECS_IO, | |
325 | .machine_check = apecs_machine_check, | |
326 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
327 | .min_io_address = DEFAULT_IO_BASE, | |
328 | .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, | |
329 | ||
330 | .nr_irqs = 35, | |
331 | .device_interrupt = cabriolet_device_interrupt, | |
332 | ||
333 | .init_arch = apecs_init_arch, | |
334 | .init_irq = cabriolet_init_irq, | |
335 | .init_rtc = common_init_rtc, | |
336 | .init_pci = cabriolet_init_pci, | |
337 | .pci_map_irq = cabriolet_map_irq, | |
338 | .pci_swizzle = common_swizzle, | |
339 | }; | |
340 | #ifndef CONFIG_ALPHA_EB64P | |
341 | ALIAS_MV(cabriolet) | |
342 | #endif | |
343 | #endif | |
344 | ||
345 | #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164) | |
346 | struct alpha_machine_vector eb164_mv __initmv = { | |
347 | .vector_name = "EB164", | |
348 | DO_EV5_MMU, | |
349 | DO_DEFAULT_RTC, | |
350 | DO_CIA_IO, | |
351 | .machine_check = cia_machine_check, | |
352 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
353 | .min_io_address = DEFAULT_IO_BASE, | |
354 | .min_mem_address = CIA_DEFAULT_MEM_BASE, | |
355 | ||
356 | .nr_irqs = 35, | |
357 | .device_interrupt = cabriolet_device_interrupt, | |
358 | ||
359 | .init_arch = cia_init_arch, | |
360 | .init_irq = cabriolet_init_irq, | |
361 | .init_rtc = common_init_rtc, | |
362 | .init_pci = cia_cab_init_pci, | |
363 | .kill_arch = cia_kill_arch, | |
364 | .pci_map_irq = cabriolet_map_irq, | |
365 | .pci_swizzle = common_swizzle, | |
366 | }; | |
367 | ALIAS_MV(eb164) | |
368 | #endif | |
369 | ||
370 | #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P) | |
371 | struct alpha_machine_vector eb66p_mv __initmv = { | |
372 | .vector_name = "EB66+", | |
373 | DO_EV4_MMU, | |
374 | DO_DEFAULT_RTC, | |
375 | DO_LCA_IO, | |
376 | .machine_check = lca_machine_check, | |
377 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
378 | .min_io_address = DEFAULT_IO_BASE, | |
379 | .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, | |
380 | ||
381 | .nr_irqs = 35, | |
382 | .device_interrupt = cabriolet_device_interrupt, | |
383 | ||
384 | .init_arch = lca_init_arch, | |
385 | .init_irq = cabriolet_init_irq, | |
386 | .init_rtc = common_init_rtc, | |
387 | .init_pci = cabriolet_init_pci, | |
388 | .pci_map_irq = eb66p_map_irq, | |
389 | .pci_swizzle = common_swizzle, | |
390 | }; | |
391 | ALIAS_MV(eb66p) | |
392 | #endif | |
393 | ||
394 | #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164) | |
395 | struct alpha_machine_vector lx164_mv __initmv = { | |
396 | .vector_name = "LX164", | |
397 | DO_EV5_MMU, | |
398 | DO_DEFAULT_RTC, | |
399 | DO_PYXIS_IO, | |
400 | .machine_check = cia_machine_check, | |
401 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
402 | .min_io_address = DEFAULT_IO_BASE, | |
403 | .min_mem_address = DEFAULT_MEM_BASE, | |
404 | .pci_dac_offset = PYXIS_DAC_OFFSET, | |
405 | ||
406 | .nr_irqs = 35, | |
407 | .device_interrupt = cabriolet_device_interrupt, | |
408 | ||
409 | .init_arch = pyxis_init_arch, | |
410 | .init_irq = cabriolet_init_irq, | |
411 | .init_rtc = common_init_rtc, | |
412 | .init_pci = alphapc164_init_pci, | |
413 | .kill_arch = cia_kill_arch, | |
414 | .pci_map_irq = alphapc164_map_irq, | |
415 | .pci_swizzle = common_swizzle, | |
416 | }; | |
417 | ALIAS_MV(lx164) | |
418 | #endif | |
419 | ||
420 | #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164) | |
421 | struct alpha_machine_vector pc164_mv __initmv = { | |
422 | .vector_name = "PC164", | |
423 | DO_EV5_MMU, | |
424 | DO_DEFAULT_RTC, | |
425 | DO_CIA_IO, | |
426 | .machine_check = cia_machine_check, | |
427 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, | |
428 | .min_io_address = DEFAULT_IO_BASE, | |
429 | .min_mem_address = CIA_DEFAULT_MEM_BASE, | |
430 | ||
431 | .nr_irqs = 35, | |
432 | .device_interrupt = pc164_device_interrupt, | |
433 | ||
434 | .init_arch = cia_init_arch, | |
435 | .init_irq = pc164_init_irq, | |
436 | .init_rtc = common_init_rtc, | |
437 | .init_pci = alphapc164_init_pci, | |
438 | .kill_arch = cia_kill_arch, | |
439 | .pci_map_irq = alphapc164_map_irq, | |
440 | .pci_swizzle = common_swizzle, | |
441 | }; | |
442 | ALIAS_MV(pc164) | |
443 | #endif |