[deliverable/linux.git] / arch / alpha / kernel / sys_marvel.c

/*
 * linux/arch/alpha/kernel/sys_marvel.c
 *
 * Marvel / IO7 support
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/bitops.h>

#include <asm/ptrace.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/core_marvel.h>
#include <asm/hwrpb.h>
#include <asm/tlbflush.h>
#include <asm/vga.h>
#include <asm/rtc.h>

#include "proto.h"
#include "err_impl.h"
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"

#if NR_IRQS < MARVEL_NR_IRQS
# error NR_IRQS < MARVEL_NR_IRQS !!!
#endif

\f
/*
 * Interrupt handling.
 */
static void 
io7_device_interrupt(unsigned long vector)
{
	unsigned int pid;
	unsigned int irq;

	/*
	 * Vector is 0x800 + (interrupt)
	 *
	 * where (interrupt) is:
	 *
	 *	...16|15 14|13     4|3 0
	 *	-----+-----+--------+---
	 *	  PE |  0  |   irq  | 0
	 *
	 * where (irq) is 
	 *
	 *       0x0800 - 0x0ff0	 - 0x0800 + (LSI id << 4)
	 *	 0x1000 - 0x2ff0	 - 0x1000 + (MSI_DAT<8:0> << 4)
	 */
	pid = vector >> 16;
	irq = ((vector & 0xffff) - 0x800) >> 4;

	irq += 16;				/* offset for legacy */
	irq &= MARVEL_IRQ_VEC_IRQ_MASK;		/* not too many bits */
	irq |= pid << MARVEL_IRQ_VEC_PE_SHIFT;	/* merge the pid     */

	handle_irq(irq);
}

static volatile unsigned long *
io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
{
	volatile unsigned long *ctl;
	unsigned int pid;
	struct io7 *io7;

	pid = irq >> MARVEL_IRQ_VEC_PE_SHIFT;

	if (!(io7 = marvel_find_io7(pid))) {
		printk(KERN_ERR 
		       "%s for nonexistent io7 -- vec %x, pid %d\n",
		       __func__, irq, pid);
		return NULL;
	}

	irq &= MARVEL_IRQ_VEC_IRQ_MASK;	/* isolate the vector    */
	irq -= 16;			/* subtract legacy bias  */

	if (irq >= 0x180) {
		printk(KERN_ERR 
		       "%s for invalid irq -- pid %d adjusted irq %x\n",
		       __func__, pid, irq);
		return NULL;
	}

	ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */
	if (irq >= 0x80)	     	/* MSI */
		ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr;

	if (pio7) *pio7 = io7;
	return ctl;
}

static void
io7_enable_irq(struct irq_data *d)
{
	volatile unsigned long *ctl;
	unsigned int irq = d->irq;
	struct io7 *io7;

	ctl = io7_get_irq_ctl(irq, &io7);
	if (!ctl || !io7) {
		printk(KERN_ERR "%s: get_ctl failed for irq %x\n",
		       __func__, irq);
		return;
	}

	spin_lock(&io7->irq_lock);
	*ctl |= 1UL << 24;
	mb();
	*ctl;
	spin_unlock(&io7->irq_lock);
}

static void
io7_disable_irq(struct irq_data *d)
{
	volatile unsigned long *ctl;
	unsigned int irq = d->irq;
	struct io7 *io7;

	ctl = io7_get_irq_ctl(irq, &io7);
	if (!ctl || !io7) {
		printk(KERN_ERR "%s: get_ctl failed for irq %x\n",
		       __func__, irq);
		return;
	}

	spin_lock(&io7->irq_lock);
	*ctl &= ~(1UL << 24);
	mb();
	*ctl;
	spin_unlock(&io7->irq_lock);
}

static void
marvel_irq_noop(struct irq_data *d)
{
	return;
}

static struct irq_chip marvel_legacy_irq_type = {
	.name		= "LEGACY",
	.irq_mask	= marvel_irq_noop,
	.irq_unmask	= marvel_irq_noop,
};

static struct irq_chip io7_lsi_irq_type = {
	.name		= "LSI",
	.irq_unmask	= io7_enable_irq,
	.irq_mask	= io7_disable_irq,
	.irq_mask_ack	= io7_disable_irq,
};

static struct irq_chip io7_msi_irq_type = {
	.name		= "MSI",
	.irq_unmask	= io7_enable_irq,
	.irq_mask	= io7_disable_irq,
	.irq_ack	= marvel_irq_noop,
};

static void
io7_redirect_irq(struct io7 *io7, 
		 volatile unsigned long *csr, 
		 unsigned int where)
{
	unsigned long val;
	
	val = *csr;
	val &= ~(0x1ffUL << 24);		/* clear the target pid   */
	val |= ((unsigned long)where << 24);	/* set the new target pid */
	
	*csr = val;
	mb();
	*csr;
}

static void 
io7_redirect_one_lsi(struct io7 *io7, unsigned int which, unsigned int where)
{
	unsigned long val;

	/*
	 * LSI_CTL has target PID @ 14
	 */
	val = io7->csrs->PO7_LSI_CTL[which].csr;
	val &= ~(0x1ffUL << 14);		/* clear the target pid */
	val |= ((unsigned long)where << 14);	/* set the new target pid */

	io7->csrs->PO7_LSI_CTL[which].csr = val;
	mb();
	io7->csrs->PO7_LSI_CTL[which].csr;
}

static void 
io7_redirect_one_msi(struct io7 *io7, unsigned int which, unsigned int where)
{
	unsigned long val;

	/*
	 * MSI_CTL has target PID @ 14
	 */
	val = io7->csrs->PO7_MSI_CTL[which].csr;
	val &= ~(0x1ffUL << 14);		/* clear the target pid */
	val |= ((unsigned long)where << 14);	/* set the new target pid */

	io7->csrs->PO7_MSI_CTL[which].csr = val;
	mb();
	io7->csrs->PO7_MSI_CTL[which].csr;
}

static void __init
init_one_io7_lsi(struct io7 *io7, unsigned int which, unsigned int where)
{
	/*
	 * LSI_CTL has target PID @ 14
	 */
	io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14);
	mb();
	io7->csrs->PO7_LSI_CTL[which].csr;
}

static void __init
init_one_io7_msi(struct io7 *io7, unsigned int which, unsigned int where)
{
	/*
	 * MSI_CTL has target PID @ 14
	 */
	io7->csrs->PO7_MSI_CTL[which].csr = ((unsigned long)where << 14);
	mb();
	io7->csrs->PO7_MSI_CTL[which].csr;
}

static void __init
init_io7_irqs(struct io7 *io7, 
	      struct irq_chip *lsi_ops,
	      struct irq_chip *msi_ops)
{
	long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16;
	long i;

	printk("Initializing interrupts for IO7 at PE %u - base %lx\n",
		io7->pe, base);

	/*
	 * Where should interrupts from this IO7 go?
	 *
	 * They really should be sent to the local CPU to avoid having to
	 * traverse the mesh, but if it's not an SMP kernel, they have to
	 * go to the boot CPU. Send them all to the boot CPU for now,
	 * as each secondary starts, it can redirect it's local device 
	 * interrupts.
	 */
	printk("  Interrupts reported to CPU at PE %u\n", boot_cpuid);

	spin_lock(&io7->irq_lock);

	/* set up the error irqs */
	io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, boot_cpuid);
	io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, boot_cpuid);
	io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, boot_cpuid);
	io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid);
	io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid);

	/* Set up the lsi irqs.  */
	for (i = 0; i < 128; ++i) {
		irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq);
		irq_set_status_flags(i, IRQ_LEVEL);
	}

	/* Disable the implemented irqs in hardware.  */
	for (i = 0; i < 0x60; ++i) 
		init_one_io7_lsi(io7, i, boot_cpuid);

	init_one_io7_lsi(io7, 0x74, boot_cpuid);
	init_one_io7_lsi(io7, 0x75, boot_cpuid);


	/* Set up the msi irqs.  */
	for (i = 128; i < (128 + 512); ++i) {
		irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq);
		irq_set_status_flags(i, IRQ_LEVEL);
	}

	for (i = 0; i < 16; ++i)
		init_one_io7_msi(io7, i, boot_cpuid);

	spin_unlock(&io7->irq_lock);
}

static void __init
marvel_init_irq(void)
{
	int i;
	struct io7 *io7 = NULL;

	/* Reserve the legacy irqs.  */
	for (i = 0; i < 16; ++i) {
		irq_set_chip_and_handler(i, &marvel_legacy_irq_type,
					 handle_level_irq);
	}

	/* Init the io7 irqs.  */
	for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; )
		init_io7_irqs(io7, &io7_lsi_irq_type, &io7_msi_irq_type);
}

static int 
marvel_map_irq(const struct pci_dev *cdev, u8 slot, u8 pin)
{
	struct pci_dev *dev = (struct pci_dev *)cdev;
	struct pci_controller *hose = dev->sysdata;
	struct io7_port *io7_port = hose->sysdata;
	struct io7 *io7 = io7_port->io7;
	int msi_loc, msi_data_off;
	u16 msg_ctl;
	u16 msg_dat;
	u8 intline; 
	int irq;

	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
	irq = intline;

	msi_loc = pci_find_capability(dev, PCI_CAP_ID_MSI);
	msg_ctl = 0;
	if (msi_loc) 
		pci_read_config_word(dev, msi_loc + PCI_MSI_FLAGS, &msg_ctl);

	if (msg_ctl & PCI_MSI_FLAGS_ENABLE) {
 		msi_data_off = PCI_MSI_DATA_32;
		if (msg_ctl & PCI_MSI_FLAGS_64BIT) 
			msi_data_off = PCI_MSI_DATA_64;
		pci_read_config_word(dev, msi_loc + msi_data_off, &msg_dat);

		irq = msg_dat & 0x1ff;		/* we use msg_data<8:0> */
		irq += 0x80;			/* offset for lsi       */

#if 1
		printk("PCI:%d:%d:%d (hose %d) is using MSI\n",
		       dev->bus->number, 
		       PCI_SLOT(dev->devfn), 
		       PCI_FUNC(dev->devfn),
		       hose->index);
		printk("  %d message(s) from 0x%04x\n", 
		       1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
		       msg_dat);
		printk("  reporting on %d IRQ(s) from %d (0x%x)\n", 
		       1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
		       (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT),
		       (irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT));
#endif

#if 0
		pci_write_config_word(dev, msi_loc + PCI_MSI_FLAGS,
				      msg_ctl & ~PCI_MSI_FLAGS_ENABLE);
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
		irq = intline;

		printk("  forcing LSI interrupt on irq %d [0x%x]\n", irq, irq);
#endif
	}

	irq += 16;					/* offset for legacy */
	irq |= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT;	/* merge the pid     */

	return irq; 
}

static void __init
marvel_init_pci(void)
{
	struct io7 *io7;

	marvel_register_error_handlers();

	/* Indicate that we trust the console to configure things properly */
	pci_set_flags(PCI_PROBE_ONLY);
	common_init_pci();
	locate_and_init_vga(NULL);

	/* Clear any io7 errors.  */
	for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) 
		io7_clear_errors(io7);
}

static void __init
marvel_init_rtc(void)
{
	init_rtc_irq();
}

struct marvel_rtc_time {
	struct rtc_time *time;
	int retval;
};

#ifdef CONFIG_SMP
static void
smp_get_rtc_time(void *data)
{
	struct marvel_rtc_time *mrt = data;
	mrt->retval = __get_rtc_time(mrt->time);
}

static void
smp_set_rtc_time(void *data)
{
	struct marvel_rtc_time *mrt = data;
	mrt->retval = __set_rtc_time(mrt->time);
}
#endif

static unsigned int
marvel_get_rtc_time(struct rtc_time *time)
{
#ifdef CONFIG_SMP
	struct marvel_rtc_time mrt;

	if (smp_processor_id() != boot_cpuid) {
		mrt.time = time;
		smp_call_function_single(boot_cpuid, smp_get_rtc_time, &mrt, 1);
		return mrt.retval;
	}
#endif
	return __get_rtc_time(time);
}

static int
marvel_set_rtc_time(struct rtc_time *time)
{
#ifdef CONFIG_SMP
	struct marvel_rtc_time mrt;

	if (smp_processor_id() != boot_cpuid) {
		mrt.time = time;
		smp_call_function_single(boot_cpuid, smp_set_rtc_time, &mrt, 1);
		return mrt.retval;
	}
#endif
	return __set_rtc_time(time);
}

static void
marvel_smp_callin(void)
{
	int cpuid = hard_smp_processor_id();
	struct io7 *io7 = marvel_find_io7(cpuid);
	unsigned int i;

	if (!io7)
		return;

	/* 
	 * There is a local IO7 - redirect all of its interrupts here.
	 */
	printk("Redirecting IO7 interrupts to local CPU at PE %u\n", cpuid);

	/* Redirect the error IRQS here.  */
	io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, cpuid);
	io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, cpuid);
	io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, cpuid);
	io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, cpuid);
	io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, cpuid);

	/* Redirect the implemented LSIs here.  */
	for (i = 0; i < 0x60; ++i) 
		io7_redirect_one_lsi(io7, i, cpuid);

	io7_redirect_one_lsi(io7, 0x74, cpuid);
	io7_redirect_one_lsi(io7, 0x75, cpuid);

	/* Redirect the MSIs here.  */
	for (i = 0; i < 16; ++i)
		io7_redirect_one_msi(io7, i, cpuid);
}
\f
/*
 * System Vectors
 */
struct alpha_machine_vector marvel_ev7_mv __initmv = {
	.vector_name		= "MARVEL/EV7",
	DO_EV7_MMU,
	.rtc_port		= 0x70,
	.rtc_get_time		= marvel_get_rtc_time,
	.rtc_set_time		= marvel_set_rtc_time,
	DO_MARVEL_IO,
	.machine_check		= marvel_machine_check,
	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= IO7_DAC_OFFSET,

	.nr_irqs		= MARVEL_NR_IRQS,
	.device_interrupt	= io7_device_interrupt,

	.agp_info		= marvel_agp_info,

	.smp_callin		= marvel_smp_callin,
	.init_arch		= marvel_init_arch,
	.init_irq		= marvel_init_irq,
	.init_rtc		= marvel_init_rtc,
	.init_pci		= marvel_init_pci,
	.kill_arch		= marvel_kill_arch,
	.pci_map_irq		= marvel_map_irq,
	.pci_swizzle		= common_swizzle,

	.pa_to_nid		= marvel_pa_to_nid,
	.cpuid_to_nid		= marvel_cpuid_to_nid,
	.node_mem_start		= marvel_node_mem_start,
	.node_mem_size		= marvel_node_mem_size,
};
ALIAS_MV(marvel_ev7)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/alpha/kernel/sys_marvel.c
	3	*
	4	* Marvel / IO7 support
	5	*/
	6
	7	#include <linux/kernel.h>
	8	#include <linux/types.h>
	9	#include <linux/mm.h>
	10	#include <linux/sched.h>
	11	#include <linux/pci.h>
	12	#include <linux/init.h>
	13	#include <linux/bitops.h>
	14
	15	#include <asm/ptrace.h>
1da177e4 LT	16	#include <asm/dma.h>
	17	#include <asm/irq.h>
	18	#include <asm/mmu_context.h>
	19	#include <asm/io.h>
	20	#include <asm/pgtable.h>
	21	#include <asm/core_marvel.h>
	22	#include <asm/hwrpb.h>
	23	#include <asm/tlbflush.h>
025a2215	24	#include <asm/vga.h>
5f7dc5d7	25	#include <asm/rtc.h>
1da177e4 LT	26
	27	#include "proto.h"
	28	#include "err_impl.h"
	29	#include "irq_impl.h"
	30	#include "pci_impl.h"
	31	#include "machvec_impl.h"
	32
	33	#if NR_IRQS < MARVEL_NR_IRQS
	34	# error NR_IRQS < MARVEL_NR_IRQS !!!
	35	#endif
	36
	37	\f
	38	/*
	39	* Interrupt handling.
	40	*/
	41	static void
7ca56053	42	io7_device_interrupt(unsigned long vector)
1da177e4 LT	43	{
	44	unsigned int pid;
	45	unsigned int irq;
	46
	47	/*
	48	* Vector is 0x800 + (interrupt)
	49	*
	50	* where (interrupt) is:
	51	*
	52	* ...16\|15 14\|13 4\|3 0
	53	* -----+-----+--------+---
	54	* PE \| 0 \| irq \| 0
	55	*
	56	* where (irq) is
	57	*
	58	* 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4)
	59	* 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4)
	60	*/
	61	pid = vector >> 16;
	62	irq = ((vector & 0xffff) - 0x800) >> 4;
	63
	64	irq += 16; /* offset for legacy */
	65	irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* not too many bits */
	66	irq \|= pid << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */
	67
3dbb8c62	68	handle_irq(irq);
1da177e4 LT	69	}
	70
	71	static volatile unsigned long *
	72	io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
	73	{
	74	volatile unsigned long *ctl;
	75	unsigned int pid;
	76	struct io7 *io7;
	77
	78	pid = irq >> MARVEL_IRQ_VEC_PE_SHIFT;
	79
	80	if (!(io7 = marvel_find_io7(pid))) {
	81	printk(KERN_ERR
	82	"%s for nonexistent io7 -- vec %x, pid %d\n",
bbb8d343	83	__func__, irq, pid);
1da177e4 LT	84	return NULL;
	85	}
	86
	87	irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* isolate the vector */
	88	irq -= 16; /* subtract legacy bias */
	89
	90	if (irq >= 0x180) {
	91	printk(KERN_ERR
	92	"%s for invalid irq -- pid %d adjusted irq %x\n",
bbb8d343	93	__func__, pid, irq);
1da177e4 LT	94	return NULL;
	95	}
	96
	97	ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */
	98	if (irq >= 0x80) /* MSI */
	99	ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr;
	100
	101	if (pio7) *pio7 = io7;
	102	return ctl;
	103	}
	104
	105	static void
08876fe8	106	io7_enable_irq(struct irq_data *d)
1da177e4 LT	107	{
1da177e4 LT	108	volatile unsigned long *ctl;
08876fe8	109	unsigned int irq = d->irq;
1da177e4 LT	110	struct io7 *io7;
	111
	112	ctl = io7_get_irq_ctl(irq, &io7);
	113	if (!ctl \|\| !io7) {
bbb8d343 HH	114	printk(KERN_ERR "%s: get_ctl failed for irq %x\n",
bbb8d343 HH	115	__func__, irq);
1da177e4 LT	116	return;
1da177e4 LT	117	}
08876fe8	118
1da177e4 LT	119	spin_lock(&io7->irq_lock);
	120	*ctl \|= 1UL << 24;
	121	mb();
	122	*ctl;
	123	spin_unlock(&io7->irq_lock);
	124	}
	125
	126	static void
08876fe8	127	io7_disable_irq(struct irq_data *d)
1da177e4 LT	128	{
1da177e4 LT	129	volatile unsigned long *ctl;
08876fe8	130	unsigned int irq = d->irq;
1da177e4 LT	131	struct io7 *io7;
	132
	133	ctl = io7_get_irq_ctl(irq, &io7);
	134	if (!ctl \|\| !io7) {
bbb8d343 HH	135	printk(KERN_ERR "%s: get_ctl failed for irq %x\n",
bbb8d343 HH	136	__func__, irq);
1da177e4 LT	137	return;
1da177e4 LT	138	}
08876fe8	139
1da177e4 LT	140	spin_lock(&io7->irq_lock);
	141	*ctl &= ~(1UL << 24);
	142	mb();
	143	*ctl;
	144	spin_unlock(&io7->irq_lock);
	145	}
	146
1da177e4	147	static void
08876fe8 TG	148	marvel_irq_noop(struct irq_data *d)
	149	{
	150	return;
1da177e4 LT	151	}
1da177e4 LT	152
44377f62	153	static struct irq_chip marvel_legacy_irq_type = {
8ab1221c	154	.name = "LEGACY",
08876fe8 TG	155	.irq_mask = marvel_irq_noop,
08876fe8 TG	156	.irq_unmask = marvel_irq_noop,
1da177e4 LT	157	};
1da177e4 LT	158
44377f62	159	static struct irq_chip io7_lsi_irq_type = {
8ab1221c	160	.name = "LSI",
08876fe8 TG	161	.irq_unmask = io7_enable_irq,
	162	.irq_mask = io7_disable_irq,
	163	.irq_mask_ack = io7_disable_irq,
1da177e4 LT	164	};
1da177e4 LT	165
44377f62	166	static struct irq_chip io7_msi_irq_type = {
8ab1221c	167	.name = "MSI",
08876fe8 TG	168	.irq_unmask = io7_enable_irq,
	169	.irq_mask = io7_disable_irq,
	170	.irq_ack = marvel_irq_noop,
1da177e4 LT	171	};
	172
	173	static void
	174	io7_redirect_irq(struct io7 *io7,
	175	volatile unsigned long *csr,
	176	unsigned int where)
	177	{
	178	unsigned long val;
	179
	180	val = *csr;
	181	val &= ~(0x1ffUL << 24); /* clear the target pid */
	182	val \|= ((unsigned long)where << 24); /* set the new target pid */
	183
	184	*csr = val;
	185	mb();
	186	*csr;
	187	}
	188
	189	static void
	190	io7_redirect_one_lsi(struct io7 *io7, unsigned int which, unsigned int where)
	191	{
	192	unsigned long val;
	193
	194	/*
	195	* LSI_CTL has target PID @ 14
	196	*/
	197	val = io7->csrs->PO7_LSI_CTL[which].csr;
	198	val &= ~(0x1ffUL << 14); /* clear the target pid */
	199	val \|= ((unsigned long)where << 14); /* set the new target pid */
	200
	201	io7->csrs->PO7_LSI_CTL[which].csr = val;
	202	mb();
	203	io7->csrs->PO7_LSI_CTL[which].csr;
	204	}
	205
	206	static void
	207	io7_redirect_one_msi(struct io7 *io7, unsigned int which, unsigned int where)
	208	{
	209	unsigned long val;
	210
	211	/*
	212	* MSI_CTL has target PID @ 14
	213	*/
	214	val = io7->csrs->PO7_MSI_CTL[which].csr;
	215	val &= ~(0x1ffUL << 14); /* clear the target pid */
	216	val \|= ((unsigned long)where << 14); /* set the new target pid */
	217
	218	io7->csrs->PO7_MSI_CTL[which].csr = val;
	219	mb();
	220	io7->csrs->PO7_MSI_CTL[which].csr;
	221	}
	222
	223	static void __init
	224	init_one_io7_lsi(struct io7 *io7, unsigned int which, unsigned int where)
	225	{
	226	/*
	227	* LSI_CTL has target PID @ 14
	228	*/
	229	io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14);
	230	mb();
	231	io7->csrs->PO7_LSI_CTL[which].csr;
	232	}
	233
	234	static void __init
235	init_one_io7_msi(struct io7 *io7, unsigned int which, unsigned int where)
236	{
237	/*
238	* MSI_CTL has target PID @ 14
239	*/
240	io7->csrs->PO7_MSI_CTL[which].csr = ((unsigned long)where << 14);
241	mb();
242	io7->csrs->PO7_MSI_CTL[which].csr;
243	}
244
245	static void __init
246	init_io7_irqs(struct io7 *io7,
44377f62 TG	247	struct irq_chip *lsi_ops,
44377f62 TG	248	struct irq_chip *msi_ops)
1da177e4 LT	249	{
	250	long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16;
	251	long i;
	252
	253	printk("Initializing interrupts for IO7 at PE %u - base %lx\n",
	254	io7->pe, base);
	255
	256	/*
	257	* Where should interrupts from this IO7 go?
	258	*
	259	* They really should be sent to the local CPU to avoid having to
	260	* traverse the mesh, but if it's not an SMP kernel, they have to
	261	* go to the boot CPU. Send them all to the boot CPU for now,
	262	* as each secondary starts, it can redirect it's local device
	263	* interrupts.
	264	*/
	265	printk(" Interrupts reported to CPU at PE %u\n", boot_cpuid);
	266
	267	spin_lock(&io7->irq_lock);
	268
	269	/* set up the error irqs */
	270	io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, boot_cpuid);
	271	io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, boot_cpuid);
	272	io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, boot_cpuid);
	273	io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid);
	274	io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid);
	275
	276	/* Set up the lsi irqs. */
	277	for (i = 0; i < 128; ++i) {
a9eb076b	278	irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq);
08876fe8	279	irq_set_status_flags(i, IRQ_LEVEL);
1da177e4 LT	280	}
	281
	282	/* Disable the implemented irqs in hardware. */
	283	for (i = 0; i < 0x60; ++i)
	284	init_one_io7_lsi(io7, i, boot_cpuid);
	285
	286	init_one_io7_lsi(io7, 0x74, boot_cpuid);
	287	init_one_io7_lsi(io7, 0x75, boot_cpuid);
	288
	289
	290	/* Set up the msi irqs. */
	291	for (i = 128; i < (128 + 512); ++i) {
a9eb076b	292	irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq);
08876fe8	293	irq_set_status_flags(i, IRQ_LEVEL);
1da177e4 LT	294	}
	295
	296	for (i = 0; i < 16; ++i)
	297	init_one_io7_msi(io7, i, boot_cpuid);
	298
	299	spin_unlock(&io7->irq_lock);
	300	}
	301
	302	static void __init
	303	marvel_init_irq(void)
	304	{
	305	int i;
	306	struct io7 *io7 = NULL;
	307
	308	/* Reserve the legacy irqs. */
	309	for (i = 0; i < 16; ++i) {
a9eb076b TG	310	irq_set_chip_and_handler(i, &marvel_legacy_irq_type,
a9eb076b TG	311	handle_level_irq);
1da177e4 LT	312	}
	313
	314	/* Init the io7 irqs. */
	315	for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; )
	316	init_io7_irqs(io7, &io7_lsi_irq_type, &io7_msi_irq_type);
	317	}
	318
	319	static int
e4060099	320	marvel_map_irq(const struct pci_dev *cdev, u8 slot, u8 pin)
1da177e4	321	{
e4060099	322	struct pci_dev dev = (struct pci_dev )cdev;
1da177e4 LT	323	struct pci_controller *hose = dev->sysdata;
	324	struct io7_port *io7_port = hose->sysdata;
	325	struct io7 *io7 = io7_port->io7;
	326	int msi_loc, msi_data_off;
	327	u16 msg_ctl;
	328	u16 msg_dat;
	329	u8 intline;
	330	int irq;
	331
	332	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
	333	irq = intline;
	334
	335	msi_loc = pci_find_capability(dev, PCI_CAP_ID_MSI);
	336	msg_ctl = 0;
	337	if (msi_loc)
	338	pci_read_config_word(dev, msi_loc + PCI_MSI_FLAGS, &msg_ctl);
	339
	340	if (msg_ctl & PCI_MSI_FLAGS_ENABLE) {
	341	msi_data_off = PCI_MSI_DATA_32;
	342	if (msg_ctl & PCI_MSI_FLAGS_64BIT)
	343	msi_data_off = PCI_MSI_DATA_64;
	344	pci_read_config_word(dev, msi_loc + msi_data_off, &msg_dat);
	345
	346	irq = msg_dat & 0x1ff; /* we use msg_data<8:0> */
	347	irq += 0x80; /* offset for lsi */
	348
	349	#if 1
982245f0	350	printk("PCI:%d:%d:%d (hose %d) is using MSI\n",
1da177e4 LT	351	dev->bus->number,
	352	PCI_SLOT(dev->devfn),
	353	PCI_FUNC(dev->devfn),
982245f0	354	hose->index);
1da177e4 LT	355	printk(" %d message(s) from 0x%04x\n",
	356	1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
	357	msg_dat);
	358	printk(" reporting on %d IRQ(s) from %d (0x%x)\n",
	359	1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
	360	(irq + 16) \| (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT),
	361	(irq + 16) \| (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT));
	362	#endif
	363
	364	#if 0
	365	pci_write_config_word(dev, msi_loc + PCI_MSI_FLAGS,
	366	msg_ctl & ~PCI_MSI_FLAGS_ENABLE);
	367	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
	368	irq = intline;
	369
	370	printk(" forcing LSI interrupt on irq %d [0x%x]\n", irq, irq);
	371	#endif
	372	}
	373
	374	irq += 16; /* offset for legacy */
	375	irq \|= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */
	376
	377	return irq;
	378	}
	379
	380	static void __init
	381	marvel_init_pci(void)
	382	{
	383	struct io7 *io7;
	384
	385	marvel_register_error_handlers();
	386
151d16d5 BH	387	/* Indicate that we trust the console to configure things properly */
151d16d5 BH	388	pci_set_flags(PCI_PROBE_ONLY);
1da177e4	389	common_init_pci();
1da177e4	390	locate_and_init_vga(NULL);
1da177e4 LT	391
	392	/* Clear any io7 errors. */
	393	for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; )
	394	io7_clear_errors(io7);
	395	}
	396
ebaf4fc1	397	static void __init
1da177e4 LT	398	marvel_init_rtc(void)
	399	{
	400	init_rtc_irq();
	401	}
	402
5f7dc5d7 IK	403	struct marvel_rtc_time {
	404	struct rtc_time *time;
	405	int retval;
	406	};
	407
	408	#ifdef CONFIG_SMP
	409	static void
	410	smp_get_rtc_time(void *data)
	411	{
	412	struct marvel_rtc_time *mrt = data;
	413	mrt->retval = __get_rtc_time(mrt->time);
	414	}
	415
	416	static void
	417	smp_set_rtc_time(void *data)
	418	{
	419	struct marvel_rtc_time *mrt = data;
	420	mrt->retval = __set_rtc_time(mrt->time);
	421	}
	422	#endif
	423
	424	static unsigned int
	425	marvel_get_rtc_time(struct rtc_time *time)
	426	{
	427	#ifdef CONFIG_SMP
	428	struct marvel_rtc_time mrt;
	429
	430	if (smp_processor_id() != boot_cpuid) {
	431	mrt.time = time;
	432	smp_call_function_single(boot_cpuid, smp_get_rtc_time, &mrt, 1);
	433	return mrt.retval;
	434	}
	435	#endif
	436	return __get_rtc_time(time);
	437	}
	438
	439	static int
	440	marvel_set_rtc_time(struct rtc_time *time)
	441	{
	442	#ifdef CONFIG_SMP
	443	struct marvel_rtc_time mrt;
	444
	445	if (smp_processor_id() != boot_cpuid) {
	446	mrt.time = time;
	447	smp_call_function_single(boot_cpuid, smp_set_rtc_time, &mrt, 1);
	448	return mrt.retval;
	449	}
	450	#endif
	451	return __set_rtc_time(time);
	452	}
	453
1da177e4 LT	454	static void
	455	marvel_smp_callin(void)
	456	{
	457	int cpuid = hard_smp_processor_id();
	458	struct io7 *io7 = marvel_find_io7(cpuid);
	459	unsigned int i;
	460
	461	if (!io7)
	462	return;
	463
	464	/*
	465	* There is a local IO7 - redirect all of its interrupts here.
	466	*/
	467	printk("Redirecting IO7 interrupts to local CPU at PE %u\n", cpuid);
	468
	469	/* Redirect the error IRQS here. */
	470	io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, cpuid);
	471	io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, cpuid);
	472	io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, cpuid);
	473	io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, cpuid);
	474	io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, cpuid);
	475
	476	/* Redirect the implemented LSIs here. */
	477	for (i = 0; i < 0x60; ++i)
	478	io7_redirect_one_lsi(io7, i, cpuid);
	479
	480	io7_redirect_one_lsi(io7, 0x74, cpuid);
	481	io7_redirect_one_lsi(io7, 0x75, cpuid);
	482
	483	/* Redirect the MSIs here. */
	484	for (i = 0; i < 16; ++i)
	485	io7_redirect_one_msi(io7, i, cpuid);
	486	}
	487	\f
	488	/*
	489	* System Vectors
	490	*/
	491	struct alpha_machine_vector marvel_ev7_mv __initmv = {
	492	.vector_name = "MARVEL/EV7",
	493	DO_EV7_MMU,
5f7dc5d7 IK	494	.rtc_port = 0x70,
	495	.rtc_get_time = marvel_get_rtc_time,
	496	.rtc_set_time = marvel_set_rtc_time,
1da177e4 LT	497	DO_MARVEL_IO,
	498	.machine_check = marvel_machine_check,
	499	.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
	500	.min_io_address = DEFAULT_IO_BASE,
	501	.min_mem_address = DEFAULT_MEM_BASE,
	502	.pci_dac_offset = IO7_DAC_OFFSET,
	503
	504	.nr_irqs = MARVEL_NR_IRQS,
	505	.device_interrupt = io7_device_interrupt,
	506
	507	.agp_info = marvel_agp_info,
	508
	509	.smp_callin = marvel_smp_callin,
	510	.init_arch = marvel_init_arch,
	511	.init_irq = marvel_init_irq,
	512	.init_rtc = marvel_init_rtc,
	513	.init_pci = marvel_init_pci,
	514	.kill_arch = marvel_kill_arch,
	515	.pci_map_irq = marvel_map_irq,
	516	.pci_swizzle = common_swizzle,
	517
	518	.pa_to_nid = marvel_pa_to_nid,
	519	.cpuid_to_nid = marvel_cpuid_to_nid,
	520	.node_mem_start = marvel_node_mem_start,
	521	.node_mem_size = marvel_node_mem_size,
	522	};
	523	ALIAS_MV(marvel_ev7)