[deliverable/linux.git] / arch / alpha / kernel / sys_ruffian.c

/*
 *	linux/arch/alpha/kernel/sys_ruffian.c
 *
 *	Copyright (C) 1995 David A Rusling
 *	Copyright (C) 1996 Jay A Estabrook
 *	Copyright (C) 1998, 1999, 2000 Richard Henderson
 *
 * Code supporting the RUFFIAN.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/init.h>

#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/core_cia.h>
#include <asm/tlbflush.h>
#include <asm/8253pit.h>

#include "proto.h"
#include "irq_impl.h"
#include "pci_impl.h"
#include "machvec_impl.h"


static void __init
ruffian_init_irq(void)
{
	/* Invert 6&7 for i82371 */
	*(vulp)PYXIS_INT_HILO  = 0x000000c0UL; mb();
	*(vulp)PYXIS_INT_CNFG  = 0x00002064UL; mb();	 /* all clear */

	outb(0x11,0xA0);
	outb(0x08,0xA1);
	outb(0x02,0xA1);
	outb(0x01,0xA1);
	outb(0xFF,0xA1);
	
	outb(0x11,0x20);
	outb(0x00,0x21);
	outb(0x04,0x21);
	outb(0x01,0x21);
	outb(0xFF,0x21);
	
	/* Finish writing the 82C59A PIC Operation Control Words */
	outb(0x20,0xA0);
	outb(0x20,0x20);
	
	init_i8259a_irqs();

	/* Not interested in the bogus interrupts (0,3,6),
	   NMI (1), HALT (2), flash (5), or 21142 (8).  */
	init_pyxis_irqs(0x16f0000);

	common_init_isa_dma();
}

#define RUFFIAN_LATCH	DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ)

static void __init
ruffian_init_rtc(void)
{
	/* Ruffian does not have the RTC connected to the CPU timer
	   interrupt.  Instead, it uses the PIT connected to IRQ 0.  */

	/* Setup interval timer.  */
	outb(0x34, 0x43);		/* binary, mode 2, LSB/MSB, ch 0 */
	outb(RUFFIAN_LATCH & 0xff, 0x40);	/* LSB */
	outb(RUFFIAN_LATCH >> 8, 0x40);		/* MSB */

	outb(0xb6, 0x43);		/* pit counter 2: speaker */
	outb(0x31, 0x42);
	outb(0x13, 0x42);

	setup_irq(0, &timer_irqaction);
}

static void
ruffian_kill_arch (int mode)
{
	cia_kill_arch(mode);
#if 0
	/* This only causes re-entry to ARCSBIOS */
	/* Perhaps this works for other PYXIS as well?  */
	*(vuip) PYXIS_RESET = 0x0000dead;
	mb();
#endif
}

/*
 *  Interrupt routing:
 *
 *		Primary bus
 *	  IdSel		INTA	INTB	INTC	INTD
 * 21052   13		  -	  -	  -	  -
 * SIO	   14		 23	  -	  -	  -
 * 21143   15		 44	  -	  -	  -
 * Slot 0  17		 43	 42	 41	 40
 *
 *		Secondary bus
 *	  IdSel		INTA	INTB	INTC	INTD
 * Slot 0   8 (18)	 19	 18	 17	 16
 * Slot 1   9 (19)	 31	 30	 29	 28
 * Slot 2  10 (20)	 27	 26	 25	 24
 * Slot 3  11 (21)	 39	 38	 37	 36
 * Slot 4  12 (22)	 35	 34	 33	 32
 * 53c875  13 (23)	 20	  -	  -	  -
 *
 */

static int __init
ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
        static char irq_tab[11][5] __initdata = {
	      /*INT  INTA INTB INTC INTD */
		{-1,  -1,  -1,  -1,  -1},  /* IdSel 13,  21052	     */
		{-1,  -1,  -1,  -1,  -1},  /* IdSel 14,  SIO	     */
		{44,  44,  44,  44,  44},  /* IdSel 15,  21143	     */
		{-1,  -1,  -1,  -1,  -1},  /* IdSel 16,  none	     */
		{43,  43,  42,  41,  40},  /* IdSel 17,  64-bit slot */
		/* the next 6 are actually on PCI bus 1, across the bridge */
		{19,  19,  18,  17,  16},  /* IdSel  8,  slot 0	     */
		{31,  31,  30,  29,  28},  /* IdSel  9,  slot 1	     */
		{27,  27,  26,  25,  24},  /* IdSel 10,  slot 2	     */
		{39,  39,  38,  37,  36},  /* IdSel 11,  slot 3	     */
		{35,  35,  34,  33,  32},  /* IdSel 12,  slot 4	     */
		{20,  20,  20,  20,  20},  /* IdSel 13,  53c875	     */
        };
	const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5;
	return COMMON_TABLE_LOOKUP;
}

static u8 __init
ruffian_swizzle(struct pci_dev *dev, u8 *pinp)
{
	int slot, pin = *pinp;

	if (dev->bus->number == 0) {
		slot = PCI_SLOT(dev->devfn);
	}		
	/* Check for the built-in bridge.  */
	else if (PCI_SLOT(dev->bus->self->devfn) == 13) {
		slot = PCI_SLOT(dev->devfn) + 10;
	}
	else 
	{
		/* Must be a card-based bridge.  */
		do {
			if (PCI_SLOT(dev->bus->self->devfn) == 13) {
				slot = PCI_SLOT(dev->devfn) + 10;
				break;
			}
			pin = pci_swizzle_interrupt_pin(dev, pin);

			/* Move up the chain of bridges.  */
			dev = dev->bus->self;
			/* Slot of the next bridge.  */
			slot = PCI_SLOT(dev->devfn);
		} while (dev->bus->self);
	}
	*pinp = pin;
	return slot;
}

#ifdef BUILDING_FOR_MILO
/*
 * The DeskStation Ruffian motherboard firmware does not place
 * the memory size in the PALimpure area.  Therefore, we use
 * the Bank Configuration Registers in PYXIS to obtain the size.
 */
static unsigned long __init
ruffian_get_bank_size(unsigned long offset)
{
	unsigned long bank_addr, bank, ret = 0;

	/* Valid offsets are: 0x800, 0x840 and 0x880
	   since Ruffian only uses three banks.  */
	bank_addr = (unsigned long)PYXIS_MCR + offset;
	bank = *(vulp)bank_addr;

	/* Check BANK_ENABLE */
	if (bank & 0x01) {
		static unsigned long size[] __initdata = {
			0x40000000UL, /* 0x00,   1G */
			0x20000000UL, /* 0x02, 512M */
			0x10000000UL, /* 0x04, 256M */
			0x08000000UL, /* 0x06, 128M */
			0x04000000UL, /* 0x08,  64M */
			0x02000000UL, /* 0x0a,  32M */
			0x01000000UL, /* 0x0c,  16M */
			0x00800000UL, /* 0x0e,   8M */
			0x80000000UL, /* 0x10,   2G */
		};

		bank = (bank & 0x1e) >> 1;
		if (bank < ARRAY_SIZE(size))
			ret = size[bank];
	}

	return ret;
}
#endif /* BUILDING_FOR_MILO */

/*
 * The System Vector
 */

struct alpha_machine_vector ruffian_mv __initmv = {
	.vector_name		= "Ruffian",
	DO_EV5_MMU,
	DO_DEFAULT_RTC,
	DO_PYXIS_IO,
	.machine_check		= cia_machine_check,
	.max_isa_dma_address	= ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
	.min_io_address		= DEFAULT_IO_BASE,
	.min_mem_address	= DEFAULT_MEM_BASE,
	.pci_dac_offset		= PYXIS_DAC_OFFSET,

	.nr_irqs		= 48,
	.device_interrupt	= pyxis_device_interrupt,

	.init_arch		= pyxis_init_arch,
	.init_irq		= ruffian_init_irq,
	.init_rtc		= ruffian_init_rtc,
	.init_pci		= cia_init_pci,
	.kill_arch		= ruffian_kill_arch,
	.pci_map_irq		= ruffian_map_irq,
	.pci_swizzle		= ruffian_swizzle,
};
ALIAS_MV(ruffian)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/alpha/kernel/sys_ruffian.c
	3	*
	4	* Copyright (C) 1995 David A Rusling
	5	* Copyright (C) 1996 Jay A Estabrook
	6	* Copyright (C) 1998, 1999, 2000 Richard Henderson
	7	*
	8	* Code supporting the RUFFIAN.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/types.h>
	13	#include <linux/mm.h>
	14	#include <linux/sched.h>
	15	#include <linux/pci.h>
	16	#include <linux/ioport.h>
08604bd9	17	#include <linux/timex.h>
1da177e4 LT	18	#include <linux/init.h>
	19
	20	#include <asm/ptrace.h>
	21	#include <asm/system.h>
	22	#include <asm/dma.h>
	23	#include <asm/irq.h>
	24	#include <asm/mmu_context.h>
	25	#include <asm/io.h>
	26	#include <asm/pgtable.h>
	27	#include <asm/core_cia.h>
	28	#include <asm/tlbflush.h>
	29	#include <asm/8253pit.h>
	30
	31	#include "proto.h"
	32	#include "irq_impl.h"
	33	#include "pci_impl.h"
	34	#include "machvec_impl.h"
	35
	36
	37	static void __init
	38	ruffian_init_irq(void)
	39	{
	40	/* Invert 6&7 for i82371 */
	41	*(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();
	42	(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); / all clear */
	43
	44	outb(0x11,0xA0);
	45	outb(0x08,0xA1);
	46	outb(0x02,0xA1);
	47	outb(0x01,0xA1);
	48	outb(0xFF,0xA1);
	49
	50	outb(0x11,0x20);
	51	outb(0x00,0x21);
	52	outb(0x04,0x21);
	53	outb(0x01,0x21);
	54	outb(0xFF,0x21);
	55
	56	/* Finish writing the 82C59A PIC Operation Control Words */
	57	outb(0x20,0xA0);
	58	outb(0x20,0x20);
	59
	60	init_i8259a_irqs();
	61
	62	/* Not interested in the bogus interrupts (0,3,6),
	63	NMI (1), HALT (2), flash (5), or 21142 (8). */
	64	init_pyxis_irqs(0x16f0000);
	65
	66	common_init_isa_dma();
	67	}
	68
04d8a9db	69	#define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ)
1da177e4 LT	70
	71	static void __init
	72	ruffian_init_rtc(void)
	73	{
	74	/* Ruffian does not have the RTC connected to the CPU timer
	75	interrupt. Instead, it uses the PIT connected to IRQ 0. */
	76
	77	/* Setup interval timer. */
	78	outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */
	79	outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */
	80	outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */
	81
	82	outb(0xb6, 0x43); /* pit counter 2: speaker */
	83	outb(0x31, 0x42);
	84	outb(0x13, 0x42);
	85
	86	setup_irq(0, &timer_irqaction);
	87	}
	88
	89	static void
	90	ruffian_kill_arch (int mode)
	91	{
	92	cia_kill_arch(mode);
	93	#if 0
	94	/* This only causes re-entry to ARCSBIOS */
	95	/* Perhaps this works for other PYXIS as well? */
	96	*(vuip) PYXIS_RESET = 0x0000dead;
	97	mb();
	98	#endif
	99	}
	100
	101	/*
	102	* Interrupt routing:
	103	*
	104	* Primary bus
	105	* IdSel INTA INTB INTC INTD
	106	* 21052 13 - - - -
	107	* SIO 14 23 - - -
	108	* 21143 15 44 - - -
	109	* Slot 0 17 43 42 41 40
	110	*
	111	* Secondary bus
	112	* IdSel INTA INTB INTC INTD
	113	* Slot 0 8 (18) 19 18 17 16
	114	* Slot 1 9 (19) 31 30 29 28
	115	* Slot 2 10 (20) 27 26 25 24
	116	* Slot 3 11 (21) 39 38 37 36
	117	* Slot 4 12 (22) 35 34 33 32
	118	* 53c875 13 (23) 20 - - -
	119	*
	120	*/
	121
	122	static int __init
	123	ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	124	{
	125	static char irq_tab[11][5] __initdata = {
	126	/INT INTA INTB INTC INTD /
	127	{-1, -1, -1, -1, -1}, /* IdSel 13, 21052 */
	128	{-1, -1, -1, -1, -1}, /* IdSel 14, SIO */
	129	{44, 44, 44, 44, 44}, /* IdSel 15, 21143 */
	130	{-1, -1, -1, -1, -1}, /* IdSel 16, none */
	131	{43, 43, 42, 41, 40}, /* IdSel 17, 64-bit slot */
	132	/* the next 6 are actually on PCI bus 1, across the bridge */
	133	{19, 19, 18, 17, 16}, /* IdSel 8, slot 0 */
134	{31, 31, 30, 29, 28}, /* IdSel 9, slot 1 */
135	{27, 27, 26, 25, 24}, /* IdSel 10, slot 2 */
136	{39, 39, 38, 37, 36}, /* IdSel 11, slot 3 */
137	{35, 35, 34, 33, 32}, /* IdSel 12, slot 4 */
138	{20, 20, 20, 20, 20}, /* IdSel 13, 53c875 */
139	};
140	const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5;
141	return COMMON_TABLE_LOOKUP;
142	}
143
144	static u8 __init
145	ruffian_swizzle(struct pci_dev dev, u8 pinp)
146	{
147	int slot, pin = *pinp;
148
149	if (dev->bus->number == 0) {
150	slot = PCI_SLOT(dev->devfn);
151	}
152	/* Check for the built-in bridge. */
153	else if (PCI_SLOT(dev->bus->self->devfn) == 13) {
154	slot = PCI_SLOT(dev->devfn) + 10;
155	}
156	else
157	{
158	/* Must be a card-based bridge. */
159	do {
160	if (PCI_SLOT(dev->bus->self->devfn) == 13) {
161	slot = PCI_SLOT(dev->devfn) + 10;
162	break;
163	}
1be9baa0	164	pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4 LT	165
	166	/* Move up the chain of bridges. */
	167	dev = dev->bus->self;
	168	/* Slot of the next bridge. */
	169	slot = PCI_SLOT(dev->devfn);
	170	} while (dev->bus->self);
	171	}
	172	*pinp = pin;
	173	return slot;
	174	}
	175
	176	#ifdef BUILDING_FOR_MILO
	177	/*
	178	* The DeskStation Ruffian motherboard firmware does not place
	179	* the memory size in the PALimpure area. Therefore, we use
	180	* the Bank Configuration Registers in PYXIS to obtain the size.
	181	*/
	182	static unsigned long __init
	183	ruffian_get_bank_size(unsigned long offset)
	184	{
	185	unsigned long bank_addr, bank, ret = 0;
25c8716c	186
1da177e4 LT	187	/* Valid offsets are: 0x800, 0x840 and 0x880
	188	since Ruffian only uses three banks. */
	189	bank_addr = (unsigned long)PYXIS_MCR + offset;
	190	bank = *(vulp)bank_addr;
25c8716c	191
1da177e4 LT	192	/* Check BANK_ENABLE */
	193	if (bank & 0x01) {
	194	static unsigned long size[] __initdata = {
25c8716c	195	0x40000000UL, /* 0x00, 1G */
1da177e4 LT	196	0x20000000UL, /* 0x02, 512M */
	197	0x10000000UL, /* 0x04, 256M */
	198	0x08000000UL, /* 0x06, 128M */
	199	0x04000000UL, /* 0x08, 64M */
	200	0x02000000UL, /* 0x0a, 32M */
	201	0x01000000UL, /* 0x0c, 16M */
	202	0x00800000UL, /* 0x0e, 8M */
	203	0x80000000UL, /* 0x10, 2G */
	204	};
	205
	206	bank = (bank & 0x1e) >> 1;
25c8716c	207	if (bank < ARRAY_SIZE(size))
1da177e4 LT	208	ret = size[bank];
	209	}
	210
	211	return ret;
	212	}
	213	#endif /* BUILDING_FOR_MILO */
	214
	215	/*
	216	* The System Vector
	217	*/
	218
	219	struct alpha_machine_vector ruffian_mv __initmv = {
	220	.vector_name = "Ruffian",
	221	DO_EV5_MMU,
	222	DO_DEFAULT_RTC,
	223	DO_PYXIS_IO,
	224	.machine_check = cia_machine_check,
	225	.max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
	226	.min_io_address = DEFAULT_IO_BASE,
	227	.min_mem_address = DEFAULT_MEM_BASE,
	228	.pci_dac_offset = PYXIS_DAC_OFFSET,
	229
	230	.nr_irqs = 48,
	231	.device_interrupt = pyxis_device_interrupt,
	232
	233	.init_arch = pyxis_init_arch,
	234	.init_irq = ruffian_init_irq,
	235	.init_rtc = ruffian_init_rtc,
	236	.init_pci = cia_init_pci,
	237	.kill_arch = ruffian_kill_arch,
	238	.pci_map_irq = ruffian_map_irq,
	239	.pci_swizzle = ruffian_swizzle,
	240	};
	241	ALIAS_MV(ruffian)