Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/alpha/kernel/sys_ruffian.c | |
3 | * | |
4 | * Copyright (C) 1995 David A Rusling | |
5 | * Copyright (C) 1996 Jay A Estabrook | |
6 | * Copyright (C) 1998, 1999, 2000 Richard Henderson | |
7 | * | |
8 | * Code supporting the RUFFIAN. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/ioport.h> | |
08604bd9 | 17 | #include <linux/timex.h> |
1da177e4 LT |
18 | #include <linux/init.h> |
19 | ||
20 | #include <asm/ptrace.h> | |
1da177e4 LT |
21 | #include <asm/dma.h> |
22 | #include <asm/irq.h> | |
23 | #include <asm/mmu_context.h> | |
24 | #include <asm/io.h> | |
25 | #include <asm/pgtable.h> | |
26 | #include <asm/core_cia.h> | |
27 | #include <asm/tlbflush.h> | |
1da177e4 LT |
28 | |
29 | #include "proto.h" | |
30 | #include "irq_impl.h" | |
31 | #include "pci_impl.h" | |
32 | #include "machvec_impl.h" | |
33 | ||
34 | ||
35 | static void __init | |
36 | ruffian_init_irq(void) | |
37 | { | |
38 | /* Invert 6&7 for i82371 */ | |
39 | *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); | |
40 | *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ | |
41 | ||
42 | outb(0x11,0xA0); | |
43 | outb(0x08,0xA1); | |
44 | outb(0x02,0xA1); | |
45 | outb(0x01,0xA1); | |
46 | outb(0xFF,0xA1); | |
47 | ||
48 | outb(0x11,0x20); | |
49 | outb(0x00,0x21); | |
50 | outb(0x04,0x21); | |
51 | outb(0x01,0x21); | |
52 | outb(0xFF,0x21); | |
53 | ||
54 | /* Finish writing the 82C59A PIC Operation Control Words */ | |
55 | outb(0x20,0xA0); | |
56 | outb(0x20,0x20); | |
57 | ||
58 | init_i8259a_irqs(); | |
59 | ||
60 | /* Not interested in the bogus interrupts (0,3,6), | |
61 | NMI (1), HALT (2), flash (5), or 21142 (8). */ | |
62 | init_pyxis_irqs(0x16f0000); | |
63 | ||
64 | common_init_isa_dma(); | |
65 | } | |
66 | ||
04d8a9db | 67 | #define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ) |
1da177e4 LT |
68 | |
69 | static void __init | |
70 | ruffian_init_rtc(void) | |
71 | { | |
72 | /* Ruffian does not have the RTC connected to the CPU timer | |
73 | interrupt. Instead, it uses the PIT connected to IRQ 0. */ | |
74 | ||
75 | /* Setup interval timer. */ | |
76 | outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */ | |
77 | outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */ | |
78 | outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */ | |
79 | ||
80 | outb(0xb6, 0x43); /* pit counter 2: speaker */ | |
81 | outb(0x31, 0x42); | |
82 | outb(0x13, 0x42); | |
83 | ||
84 | setup_irq(0, &timer_irqaction); | |
85 | } | |
86 | ||
87 | static void | |
88 | ruffian_kill_arch (int mode) | |
89 | { | |
90 | cia_kill_arch(mode); | |
91 | #if 0 | |
92 | /* This only causes re-entry to ARCSBIOS */ | |
93 | /* Perhaps this works for other PYXIS as well? */ | |
94 | *(vuip) PYXIS_RESET = 0x0000dead; | |
95 | mb(); | |
96 | #endif | |
97 | } | |
98 | ||
99 | /* | |
100 | * Interrupt routing: | |
101 | * | |
102 | * Primary bus | |
103 | * IdSel INTA INTB INTC INTD | |
104 | * 21052 13 - - - - | |
105 | * SIO 14 23 - - - | |
106 | * 21143 15 44 - - - | |
107 | * Slot 0 17 43 42 41 40 | |
108 | * | |
109 | * Secondary bus | |
110 | * IdSel INTA INTB INTC INTD | |
111 | * Slot 0 8 (18) 19 18 17 16 | |
112 | * Slot 1 9 (19) 31 30 29 28 | |
113 | * Slot 2 10 (20) 27 26 25 24 | |
114 | * Slot 3 11 (21) 39 38 37 36 | |
115 | * Slot 4 12 (22) 35 34 33 32 | |
116 | * 53c875 13 (23) 20 - - - | |
117 | * | |
118 | */ | |
119 | ||
120 | static int __init | |
d5341942 | 121 | ruffian_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 LT |
122 | { |
123 | static char irq_tab[11][5] __initdata = { | |
124 | /*INT INTA INTB INTC INTD */ | |
125 | {-1, -1, -1, -1, -1}, /* IdSel 13, 21052 */ | |
126 | {-1, -1, -1, -1, -1}, /* IdSel 14, SIO */ | |
127 | {44, 44, 44, 44, 44}, /* IdSel 15, 21143 */ | |
128 | {-1, -1, -1, -1, -1}, /* IdSel 16, none */ | |
129 | {43, 43, 42, 41, 40}, /* IdSel 17, 64-bit slot */ | |
130 | /* the next 6 are actually on PCI bus 1, across the bridge */ | |
131 | {19, 19, 18, 17, 16}, /* IdSel 8, slot 0 */ | |
132 | {31, 31, 30, 29, 28}, /* IdSel 9, slot 1 */ | |
133 | {27, 27, 26, 25, 24}, /* IdSel 10, slot 2 */ | |
134 | {39, 39, 38, 37, 36}, /* IdSel 11, slot 3 */ | |
135 | {35, 35, 34, 33, 32}, /* IdSel 12, slot 4 */ | |
136 | {20, 20, 20, 20, 20}, /* IdSel 13, 53c875 */ | |
137 | }; | |
138 | const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5; | |
139 | return COMMON_TABLE_LOOKUP; | |
140 | } | |
141 | ||
142 | static u8 __init | |
143 | ruffian_swizzle(struct pci_dev *dev, u8 *pinp) | |
144 | { | |
145 | int slot, pin = *pinp; | |
146 | ||
147 | if (dev->bus->number == 0) { | |
148 | slot = PCI_SLOT(dev->devfn); | |
149 | } | |
150 | /* Check for the built-in bridge. */ | |
151 | else if (PCI_SLOT(dev->bus->self->devfn) == 13) { | |
152 | slot = PCI_SLOT(dev->devfn) + 10; | |
153 | } | |
154 | else | |
155 | { | |
156 | /* Must be a card-based bridge. */ | |
157 | do { | |
158 | if (PCI_SLOT(dev->bus->self->devfn) == 13) { | |
159 | slot = PCI_SLOT(dev->devfn) + 10; | |
160 | break; | |
161 | } | |
1be9baa0 | 162 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
163 | |
164 | /* Move up the chain of bridges. */ | |
165 | dev = dev->bus->self; | |
166 | /* Slot of the next bridge. */ | |
167 | slot = PCI_SLOT(dev->devfn); | |
168 | } while (dev->bus->self); | |
169 | } | |
170 | *pinp = pin; | |
171 | return slot; | |
172 | } | |
173 | ||
174 | #ifdef BUILDING_FOR_MILO | |
175 | /* | |
176 | * The DeskStation Ruffian motherboard firmware does not place | |
177 | * the memory size in the PALimpure area. Therefore, we use | |
178 | * the Bank Configuration Registers in PYXIS to obtain the size. | |
179 | */ | |
180 | static unsigned long __init | |
181 | ruffian_get_bank_size(unsigned long offset) | |
182 | { | |
183 | unsigned long bank_addr, bank, ret = 0; | |
25c8716c | 184 | |
1da177e4 LT |
185 | /* Valid offsets are: 0x800, 0x840 and 0x880 |
186 | since Ruffian only uses three banks. */ | |
187 | bank_addr = (unsigned long)PYXIS_MCR + offset; | |
188 | bank = *(vulp)bank_addr; | |
25c8716c | 189 | |
1da177e4 LT |
190 | /* Check BANK_ENABLE */ |
191 | if (bank & 0x01) { | |
192 | static unsigned long size[] __initdata = { | |
25c8716c | 193 | 0x40000000UL, /* 0x00, 1G */ |
1da177e4 LT |
194 | 0x20000000UL, /* 0x02, 512M */ |
195 | 0x10000000UL, /* 0x04, 256M */ | |
196 | 0x08000000UL, /* 0x06, 128M */ | |
197 | 0x04000000UL, /* 0x08, 64M */ | |
198 | 0x02000000UL, /* 0x0a, 32M */ | |
199 | 0x01000000UL, /* 0x0c, 16M */ | |
200 | 0x00800000UL, /* 0x0e, 8M */ | |
201 | 0x80000000UL, /* 0x10, 2G */ | |
202 | }; | |
203 | ||
204 | bank = (bank & 0x1e) >> 1; | |
25c8716c | 205 | if (bank < ARRAY_SIZE(size)) |
1da177e4 LT |
206 | ret = size[bank]; |
207 | } | |
208 | ||
209 | return ret; | |
210 | } | |
211 | #endif /* BUILDING_FOR_MILO */ | |
212 | ||
213 | /* | |
214 | * The System Vector | |
215 | */ | |
216 | ||
217 | struct alpha_machine_vector ruffian_mv __initmv = { | |
218 | .vector_name = "Ruffian", | |
219 | DO_EV5_MMU, | |
220 | DO_DEFAULT_RTC, | |
221 | DO_PYXIS_IO, | |
222 | .machine_check = cia_machine_check, | |
223 | .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS, | |
224 | .min_io_address = DEFAULT_IO_BASE, | |
225 | .min_mem_address = DEFAULT_MEM_BASE, | |
226 | .pci_dac_offset = PYXIS_DAC_OFFSET, | |
227 | ||
228 | .nr_irqs = 48, | |
229 | .device_interrupt = pyxis_device_interrupt, | |
230 | ||
231 | .init_arch = pyxis_init_arch, | |
232 | .init_irq = ruffian_init_irq, | |
233 | .init_rtc = ruffian_init_rtc, | |
234 | .init_pci = cia_init_pci, | |
235 | .kill_arch = ruffian_kill_arch, | |
236 | .pci_map_irq = ruffian_map_irq, | |
237 | .pci_swizzle = ruffian_swizzle, | |
238 | }; | |
239 | ALIAS_MV(ruffian) |