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1da177e4 LT |
1 | /* |
2 | * arch/alpha/lib/ev6-csum_ipv6_magic.S | |
3 | * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com> | |
4 | * | |
5 | * unsigned short csum_ipv6_magic(struct in6_addr *saddr, | |
6 | * struct in6_addr *daddr, | |
7 | * __u32 len, | |
8 | * unsigned short proto, | |
9 | * unsigned int csum); | |
10 | * | |
11 | * Much of the information about 21264 scheduling/coding comes from: | |
12 | * Compiler Writer's Guide for the Alpha 21264 | |
13 | * abbreviated as 'CWG' in other comments here | |
14 | * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html | |
15 | * Scheduling notation: | |
16 | * E - either cluster | |
17 | * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1 | |
18 | * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1 | |
19 | * Try not to change the actual algorithm if possible for consistency. | |
20 | * Determining actual stalls (other than slotting) doesn't appear to be easy to do. | |
21 | * | |
22 | * unsigned short csum_ipv6_magic(struct in6_addr *saddr, | |
23 | * struct in6_addr *daddr, | |
24 | * __u32 len, | |
25 | * unsigned short proto, | |
26 | * unsigned int csum); | |
27 | * | |
28 | * Swap <proto> (takes form 0xaabb) | |
29 | * Then shift it left by 48, so result is: | |
30 | * 0xbbaa0000 00000000 | |
31 | * Then turn it back into a sign extended 32-bit item | |
32 | * 0xbbaa0000 | |
33 | * | |
34 | * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence | |
35 | * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence) | |
36 | * Assume input takes form 0xAABBCCDD | |
37 | * | |
38 | * Finally, original 'folding' approach is to split the long into 4 unsigned shorts | |
39 | * add 4 ushorts, resulting in ushort/carry | |
40 | * add carry bits + ushort --> ushort | |
41 | * add carry bits + ushort --> ushort (in case the carry results in an overflow) | |
42 | * Truncate to a ushort. (took 13 instructions) | |
43 | * From doing some testing, using the approach in checksum.c:from64to16() | |
44 | * results in the same outcome: | |
45 | * split into 2 uints, add those, generating a ulong | |
46 | * add the 3 low ushorts together, generating a uint | |
47 | * a final add of the 2 lower ushorts | |
48 | * truncating the result. | |
58ed2f9c IK |
49 | * |
50 | * Misalignment handling added by Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
51 | * The cost is 16 instructions (~8 cycles), including two extra loads which | |
52 | * may cause additional delay in rare cases (load-load replay traps). | |
1da177e4 LT |
53 | */ |
54 | ||
00fc0e0d | 55 | #include <asm/export.h> |
1da177e4 LT |
56 | .globl csum_ipv6_magic |
57 | .align 4 | |
58 | .ent csum_ipv6_magic | |
59 | .frame $30,0,$26,0 | |
60 | csum_ipv6_magic: | |
61 | .prologue 0 | |
62 | ||
58ed2f9c | 63 | ldq_u $0,0($16) # L : Latency: 3 |
1da177e4 | 64 | inslh $18,7,$4 # U : 0000000000AABBCC |
58ed2f9c | 65 | ldq_u $1,8($16) # L : Latency: 3 |
1da177e4 LT |
66 | sll $19,8,$7 # U : U L U L : 0x00000000 00aabb00 |
67 | ||
58ed2f9c IK |
68 | and $16,7,$6 # E : src misalignment |
69 | ldq_u $5,15($16) # L : Latency: 3 | |
1da177e4 | 70 | zapnot $20,15,$20 # U : zero extend incoming csum |
58ed2f9c IK |
71 | ldq_u $2,0($17) # L : U L U L : Latency: 3 |
72 | ||
73 | extql $0,$6,$0 # U : | |
74 | extqh $1,$6,$22 # U : | |
75 | ldq_u $3,8($17) # L : Latency: 3 | |
76 | sll $19,24,$19 # U : U U L U : 0x000000aa bb000000 | |
77 | ||
78 | cmoveq $6,$31,$22 # E : src aligned? | |
79 | ldq_u $23,15($17) # L : Latency: 3 | |
1da177e4 | 80 | inswl $18,3,$18 # U : 000000CCDD000000 |
58ed2f9c | 81 | addl $19,$7,$19 # E : U L U L : <sign bits>bbaabb00 |
1da177e4 | 82 | |
58ed2f9c IK |
83 | or $0,$22,$0 # E : 1st src word complete |
84 | extql $1,$6,$1 # U : | |
85 | or $18,$4,$18 # E : 000000CCDDAABBCC | |
86 | extqh $5,$6,$5 # U : L U L U | |
1da177e4 | 87 | |
58ed2f9c IK |
88 | and $17,7,$6 # E : dst misalignment |
89 | extql $2,$6,$2 # U : | |
90 | or $1,$5,$1 # E : 2nd src word complete | |
91 | extqh $3,$6,$22 # U : L U L U : | |
92 | ||
93 | cmoveq $6,$31,$22 # E : dst aligned? | |
94 | extql $3,$6,$3 # U : | |
1da177e4 | 95 | addq $20,$0,$20 # E : begin summing the words |
58ed2f9c IK |
96 | extqh $23,$6,$23 # U : L U L U : |
97 | ||
1da177e4 | 98 | srl $18,16,$4 # U : 0000000000CCDDAA |
58ed2f9c | 99 | or $2,$22,$2 # E : 1st dst word complete |
1da177e4 | 100 | zap $19,0x3,$19 # U : <sign bits>bbaa0000 |
58ed2f9c | 101 | or $3,$23,$3 # E : U L U L : 2nd dst word complete |
1da177e4 LT |
102 | |
103 | cmpult $20,$0,$0 # E : | |
104 | addq $20,$1,$20 # E : | |
105 | zapnot $18,0xa,$18 # U : 00000000DD00BB00 | |
106 | zap $4,0xa,$4 # U : U U L L : 0000000000CC00AA | |
107 | ||
108 | or $18,$4,$18 # E : 00000000DDCCBBAA | |
109 | nop # E : | |
110 | cmpult $20,$1,$1 # E : | |
111 | addq $20,$2,$20 # E : U L U L | |
112 | ||
113 | cmpult $20,$2,$2 # E : | |
114 | addq $20,$3,$20 # E : | |
115 | cmpult $20,$3,$3 # E : (1 cycle stall on $20) | |
116 | addq $20,$18,$20 # E : U L U L (1 cycle stall on $20) | |
117 | ||
118 | cmpult $20,$18,$18 # E : | |
119 | addq $20,$19,$20 # E : (1 cycle stall on $20) | |
120 | addq $0,$1,$0 # E : merge the carries back into the csum | |
121 | addq $2,$3,$2 # E : | |
122 | ||
123 | cmpult $20,$19,$19 # E : | |
124 | addq $18,$19,$18 # E : (1 cycle stall on $19) | |
125 | addq $0,$2,$0 # E : | |
126 | addq $20,$18,$20 # E : U L U L : | |
127 | /* (1 cycle stall on $18, 2 cycles on $20) */ | |
128 | ||
129 | addq $0,$20,$0 # E : | |
130 | zapnot $0,15,$1 # U : Start folding output (1 cycle stall on $0) | |
131 | nop # E : | |
132 | srl $0,32,$0 # U : U L U L : (1 cycle stall on $0) | |
133 | ||
134 | addq $1,$0,$1 # E : Finished generating ulong | |
135 | extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1) | |
136 | zapnot $1,3,$0 # U : ushort[0] (1 cycle stall on $1) | |
137 | extwl $1,4,$1 # U : ushort[2] (1 cycle stall on $1) | |
138 | ||
139 | addq $0,$2,$0 # E | |
140 | addq $0,$1,$3 # E : Finished generating uint | |
141 | /* (1 cycle stall on $0) */ | |
142 | extwl $3,2,$1 # U : ushort[1] (1 cycle stall on $3) | |
143 | nop # E : L U L U | |
144 | ||
145 | addq $1,$3,$0 # E : Final carry | |
146 | not $0,$4 # E : complement (1 cycle stall on $0) | |
147 | zapnot $4,3,$0 # U : clear upper garbage bits | |
148 | /* (1 cycle stall on $4) */ | |
149 | ret # L0 : L U L U | |
150 | ||
151 | .end csum_ipv6_magic | |
00fc0e0d | 152 | EXPORT_SYMBOL(csum_ipv6_magic) |