Commit | Line | Data |
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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
2a440168 | 11 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
f06d19e4 | 12 | select BUILDTIME_EXTABLE_SORT |
69fbd098 | 13 | select CLKSRC_OF |
4adeefe1 | 14 | select CLONE_BACKWARDS |
69fbd098 | 15 | select COMMON_CLK |
cfdbc2e1 VG |
16 | select GENERIC_ATOMIC64 |
17 | select GENERIC_CLOCKEVENTS | |
18 | select GENERIC_FIND_FIRST_BIT | |
19 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
20 | select GENERIC_IRQ_SHOW | |
c1678ffc | 21 | select GENERIC_PCI_IOMAP |
cfdbc2e1 VG |
22 | select GENERIC_PENDING_IRQ if SMP |
23 | select GENERIC_SMP_IDLE_THREAD | |
f46121bd | 24 | select HAVE_ARCH_KGDB |
547f1125 | 25 | select HAVE_ARCH_TRACEHOOK |
5e057429 | 26 | select HAVE_FUTEX_CMPXCHG |
4368902b | 27 | select HAVE_IOREMAP_PROT |
4d86dfbb VG |
28 | select HAVE_KPROBES |
29 | select HAVE_KRETPROBES | |
c121c506 | 30 | select HAVE_MEMBLOCK |
854a0d95 | 31 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 32 | select HAVE_OPROFILE |
9c57564e | 33 | select HAVE_PERF_EVENTS |
1b0ccb8a | 34 | select HANDLE_DOMAIN_IRQ |
999159a5 | 35 | select IRQ_DOMAIN |
cfdbc2e1 | 36 | select MODULES_USE_ELF_RELA |
c121c506 | 37 | select NO_BOOTMEM |
999159a5 VG |
38 | select OF |
39 | select OF_EARLY_FLATTREE | |
1b10cb21 | 40 | select OF_RESERVED_MEM |
9c57564e | 41 | select PERF_USE_VMALLOC |
d1a1dc0b | 42 | select HAVE_DEBUG_STACKOVERFLOW |
32ed9a0e | 43 | select HAVE_GENERIC_DMA_COHERENT |
cfdbc2e1 | 44 | |
c1678ffc JP |
45 | config MIGHT_HAVE_PCI |
46 | bool | |
47 | ||
0dafafc3 VG |
48 | config TRACE_IRQFLAGS_SUPPORT |
49 | def_bool y | |
50 | ||
51 | config LOCKDEP_SUPPORT | |
52 | def_bool y | |
53 | ||
cfdbc2e1 VG |
54 | config SCHED_OMIT_FRAME_POINTER |
55 | def_bool y | |
56 | ||
57 | config GENERIC_CSUM | |
58 | def_bool y | |
59 | ||
60 | config RWSEM_GENERIC_SPINLOCK | |
61 | def_bool y | |
62 | ||
26f9d5fd VG |
63 | config ARCH_DISCONTIGMEM_ENABLE |
64 | def_bool y | |
65 | ||
cfdbc2e1 VG |
66 | config ARCH_FLATMEM_ENABLE |
67 | def_bool y | |
68 | ||
69 | config MMU | |
70 | def_bool y | |
71 | ||
ce816fa8 | 72 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
73 | def_bool y |
74 | ||
75 | config GENERIC_CALIBRATE_DELAY | |
76 | def_bool y | |
77 | ||
78 | config GENERIC_HWEIGHT | |
79 | def_bool y | |
80 | ||
44c8bb91 VG |
81 | config STACKTRACE_SUPPORT |
82 | def_bool y | |
83 | select STACKTRACE | |
84 | ||
fe6c1b86 VG |
85 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
86 | def_bool y | |
87 | depends on ARC_MMU_V4 | |
88 | ||
cfdbc2e1 VG |
89 | source "init/Kconfig" |
90 | source "kernel/Kconfig.freezer" | |
91 | ||
92 | menu "ARC Architecture Configuration" | |
93 | ||
93ad700d | 94 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 95 | |
fd155792 | 96 | source "arch/arc/plat-sim/Kconfig" |
072eb693 | 97 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 98 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 99 | #New platform adds here |
96665789 | 100 | source "arch/arc/plat-eznps/Kconfig" |
93ad700d | 101 | |
53d98958 | 102 | endmenu |
cfdbc2e1 | 103 | |
1f6ccfff VG |
104 | choice |
105 | prompt "ARC Instruction Set" | |
106 | default ISA_ARCOMPACT | |
107 | ||
108 | config ISA_ARCOMPACT | |
109 | bool "ARCompact ISA" | |
fff7fb0b | 110 | select CPU_NO_EFFICIENT_FFS |
1f6ccfff VG |
111 | help |
112 | The original ARC ISA of ARC600/700 cores | |
113 | ||
65bfbcdf VG |
114 | config ISA_ARCV2 |
115 | bool "ARC ISA v2" | |
116 | help | |
117 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
118 | |
119 | endchoice | |
120 | ||
cfdbc2e1 VG |
121 | menu "ARC CPU Configuration" |
122 | ||
123 | choice | |
124 | prompt "ARC Core" | |
1f6ccfff VG |
125 | default ARC_CPU_770 if ISA_ARCOMPACT |
126 | default ARC_CPU_HS if ISA_ARCV2 | |
127 | ||
128 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
129 | |
130 | config ARC_CPU_750D | |
131 | bool "ARC750D" | |
14a0abfc | 132 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
133 | help |
134 | Support for ARC750 core | |
135 | ||
136 | config ARC_CPU_770 | |
137 | bool "ARC770" | |
742f8af6 | 138 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
139 | help |
140 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
141 | This core has a bunch of cool new features: | |
142 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
143 | Shared Address Spaces (for sharing TLB entires in MMU) | |
144 | -Caches: New Prog Model, Region Flush | |
145 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
146 | ||
1f6ccfff VG |
147 | endif #ISA_ARCOMPACT |
148 | ||
149 | config ARC_CPU_HS | |
150 | bool "ARC-HS" | |
151 | depends on ISA_ARCV2 | |
152 | help | |
153 | Support for ARC HS38x Cores based on ARCv2 ISA | |
154 | The notable features are: | |
155 | - SMP configurations of upto 4 core with coherency | |
156 | - Optional L2 Cache and IO-Coherency | |
157 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
158 | auto stack switch, auto regfile save/restore) | |
159 | - MMUv4 (PIPT dcache, Huge Pages) | |
160 | - Instructions for | |
161 | * 64bit load/store: LDD, STD | |
162 | * Hardware assisted divide/remainder: DIV, REM | |
163 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
164 | * IRQ enable/disable: CLRI, SETI | |
165 | * pop count: FFS, FLS | |
166 | * SETcc, BMSKN, XBFU... | |
167 | ||
cfdbc2e1 VG |
168 | endchoice |
169 | ||
170 | config CPU_BIG_ENDIAN | |
171 | bool "Enable Big Endian Mode" | |
172 | default n | |
173 | help | |
174 | Build kernel for Big Endian Mode of ARC CPU | |
175 | ||
41195d23 | 176 | config SMP |
82fea5a1 | 177 | bool "Symmetric Multi-Processing" |
41195d23 | 178 | default n |
82fea5a1 VG |
179 | select ARC_HAS_COH_CACHES if ISA_ARCV2 |
180 | select ARC_MCIP if ISA_ARCV2 | |
41195d23 | 181 | help |
82fea5a1 | 182 | This enables support for systems with more than one CPU. |
41195d23 VG |
183 | |
184 | if SMP | |
185 | ||
186 | config ARC_HAS_COH_CACHES | |
187 | def_bool n | |
188 | ||
41195d23 VG |
189 | config ARC_HAS_REENTRANT_IRQ_LV2 |
190 | def_bool n | |
191 | ||
82fea5a1 VG |
192 | config ARC_MCIP |
193 | bool "ARConnect Multicore IP (MCIP) Support " | |
194 | depends on ISA_ARCV2 | |
195 | help | |
196 | This IP block enables SMP in ARC-HS38 cores. | |
197 | It provides for cross-core interrupts, multi-core debug | |
198 | hardware semaphores, shared memory,.... | |
41195d23 VG |
199 | |
200 | config NR_CPUS | |
3aa4f80e NC |
201 | int "Maximum number of CPUs (2-4096)" |
202 | range 2 4096 | |
82fea5a1 VG |
203 | default "4" |
204 | ||
3971cdc2 VG |
205 | config ARC_SMP_HALT_ON_RESET |
206 | bool "Enable Halt-on-reset boot mode" | |
207 | default y if ARC_UBOOT_SUPPORT | |
208 | help | |
209 | In SMP configuration cores can be configured as Halt-on-reset | |
210 | or they could all start at same time. For Halt-on-reset, non | |
211 | masters are parked until Master kicks them so they can start of | |
212 | at designated entry point. For other case, all jump to common | |
213 | entry point and spin wait for Master's signal. | |
214 | ||
82fea5a1 | 215 | endif #SMP |
41195d23 | 216 | |
cfdbc2e1 VG |
217 | menuconfig ARC_CACHE |
218 | bool "Enable Cache Support" | |
219 | default y | |
41195d23 VG |
220 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
221 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
222 | |
223 | if ARC_CACHE | |
224 | ||
225 | config ARC_CACHE_LINE_SHIFT | |
226 | int "Cache Line Length (as power of 2)" | |
227 | range 5 7 | |
228 | default "6" | |
229 | help | |
230 | Starting with ARC700 4.9, Cache line length is configurable, | |
231 | This option specifies "N", with Line-len = 2 power N | |
232 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
233 | Linux only supports same line lengths for I and D caches. | |
234 | ||
235 | config ARC_HAS_ICACHE | |
236 | bool "Use Instruction Cache" | |
237 | default y | |
238 | ||
239 | config ARC_HAS_DCACHE | |
240 | bool "Use Data Cache" | |
241 | default y | |
242 | ||
243 | config ARC_CACHE_PAGES | |
244 | bool "Per Page Cache Control" | |
245 | default y | |
246 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
247 | help | |
248 | This can be used to over-ride the global I/D Cache Enable on a | |
249 | per-page basis (but only for pages accessed via MMU such as | |
250 | Kernel Virtual address or User Virtual Address) | |
251 | TLB entries have a per-page Cache Enable Bit. | |
252 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
253 | Global DISABLE + Per Page ENABLE won't work | |
254 | ||
4102b533 VG |
255 | config ARC_CACHE_VIPT_ALIASING |
256 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 257 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 VG |
258 | default n |
259 | ||
cfdbc2e1 VG |
260 | endif #ARC_CACHE |
261 | ||
8b5850f8 VG |
262 | config ARC_HAS_ICCM |
263 | bool "Use ICCM" | |
264 | help | |
265 | Single Cycle RAMS to store Fast Path Code | |
266 | default n | |
267 | ||
268 | config ARC_ICCM_SZ | |
269 | int "ICCM Size in KB" | |
270 | default "64" | |
271 | depends on ARC_HAS_ICCM | |
272 | ||
273 | config ARC_HAS_DCCM | |
274 | bool "Use DCCM" | |
275 | help | |
276 | Single Cycle RAMS to store Fast Path Data | |
277 | default n | |
278 | ||
279 | config ARC_DCCM_SZ | |
280 | int "DCCM Size in KB" | |
281 | default "64" | |
282 | depends on ARC_HAS_DCCM | |
283 | ||
284 | config ARC_DCCM_BASE | |
285 | hex "DCCM map address" | |
286 | default "0xA0000000" | |
287 | depends on ARC_HAS_DCCM | |
288 | ||
cfdbc2e1 | 289 | choice |
1f6ccfff | 290 | prompt "MMU Version" |
cfdbc2e1 VG |
291 | default ARC_MMU_V3 if ARC_CPU_770 |
292 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 293 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 294 | |
c583ee4f VG |
295 | if ISA_ARCOMPACT |
296 | ||
cfdbc2e1 VG |
297 | config ARC_MMU_V1 |
298 | bool "MMU v1" | |
299 | help | |
300 | Orig ARC700 MMU | |
301 | ||
302 | config ARC_MMU_V2 | |
303 | bool "MMU v2" | |
304 | help | |
305 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
306 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
307 | ||
308 | config ARC_MMU_V3 | |
309 | bool "MMU v3" | |
310 | depends on ARC_CPU_770 | |
311 | help | |
312 | Introduced with ARC700 4.10: New Features | |
313 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
314 | Shared Address Spaces (SASID) | |
315 | ||
c583ee4f VG |
316 | endif |
317 | ||
d7a512bf VG |
318 | config ARC_MMU_V4 |
319 | bool "MMU v4" | |
320 | depends on ISA_ARCV2 | |
321 | ||
cfdbc2e1 VG |
322 | endchoice |
323 | ||
324 | ||
325 | choice | |
326 | prompt "MMU Page Size" | |
327 | default ARC_PAGE_SIZE_8K | |
328 | ||
329 | config ARC_PAGE_SIZE_8K | |
330 | bool "8KB" | |
331 | help | |
332 | Choose between 8k vs 16k | |
333 | ||
334 | config ARC_PAGE_SIZE_16K | |
335 | bool "16KB" | |
450ed0db | 336 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
337 | |
338 | config ARC_PAGE_SIZE_4K | |
339 | bool "4KB" | |
450ed0db | 340 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
341 | |
342 | endchoice | |
343 | ||
37eda9df VG |
344 | choice |
345 | prompt "MMU Super Page Size" | |
346 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE | |
347 | default ARC_HUGEPAGE_2M | |
348 | ||
349 | config ARC_HUGEPAGE_2M | |
350 | bool "2MB" | |
351 | ||
352 | config ARC_HUGEPAGE_16M | |
353 | bool "16MB" | |
354 | ||
355 | endchoice | |
356 | ||
26f9d5fd VG |
357 | config NODES_SHIFT |
358 | int "Maximum NUMA Nodes (as a power of 2)" | |
359 | default "1" if !DISCONTIGMEM | |
360 | default "2" if DISCONTIGMEM | |
361 | depends on NEED_MULTIPLE_NODES | |
362 | ---help--- | |
363 | Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory | |
364 | zones. | |
365 | ||
1f6ccfff VG |
366 | if ISA_ARCOMPACT |
367 | ||
4788a594 VG |
368 | config ARC_COMPACT_IRQ_LEVELS |
369 | bool "ARCompact IRQ Priorities: High(2)/Low(1)" | |
370 | default n | |
371 | # Timer HAS to be high priority, for any other high priority config | |
372 | select ARC_IRQ3_LV2 | |
41195d23 VG |
373 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
374 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | |
4788a594 VG |
375 | |
376 | if ARC_COMPACT_IRQ_LEVELS | |
377 | ||
378 | config ARC_IRQ3_LV2 | |
379 | bool | |
380 | ||
381 | config ARC_IRQ5_LV2 | |
382 | bool | |
383 | ||
384 | config ARC_IRQ6_LV2 | |
385 | bool | |
386 | ||
1f6ccfff | 387 | endif #ARC_COMPACT_IRQ_LEVELS |
4788a594 | 388 | |
cfdbc2e1 VG |
389 | config ARC_FPU_SAVE_RESTORE |
390 | bool "Enable FPU state persistence across context switch" | |
391 | default n | |
392 | help | |
393 | Double Precision Floating Point unit had dedictaed regs which | |
394 | need to be saved/restored across context-switch. | |
395 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
396 | hardware pieces to allow software to conditionally save/restore, | |
397 | based on actual usage of FPU by a task. Thus our implemn does | |
398 | this for all tasks in system. | |
399 | ||
1f6ccfff VG |
400 | endif #ISA_ARCOMPACT |
401 | ||
fbf8e13d VG |
402 | config ARC_CANT_LLSC |
403 | def_bool n | |
404 | ||
cfdbc2e1 VG |
405 | config ARC_HAS_LLSC |
406 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
407 | default y | |
14a0abfc | 408 | depends on !ARC_CANT_LLSC |
cfdbc2e1 | 409 | |
e78fdfef VG |
410 | config ARC_STAR_9000923308 |
411 | bool "Workaround for llock/scond livelock" | |
b31ac426 | 412 | default n |
e78fdfef VG |
413 | depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC |
414 | ||
cfdbc2e1 VG |
415 | config ARC_HAS_SWAPE |
416 | bool "Insn: SWAPE (endian-swap)" | |
417 | default y | |
cfdbc2e1 | 418 | |
1f6ccfff VG |
419 | if ISA_ARCV2 |
420 | ||
421 | config ARC_HAS_LL64 | |
422 | bool "Insn: 64bit LDD/STD" | |
423 | help | |
424 | Enable gcc to generate 64-bit load/store instructions | |
425 | ISA mandates even/odd registers to allow encoding of two | |
426 | dest operands with 2 possible source operands. | |
427 | default y | |
428 | ||
d05a76ab AB |
429 | config ARC_HAS_DIV_REM |
430 | bool "Insn: div, divu, rem, remu" | |
431 | default y | |
432 | ||
aa93e8ef VG |
433 | config ARC_HAS_RTC |
434 | bool "Local 64-bit r/o cycle counter" | |
435 | default n | |
436 | depends on !SMP | |
437 | ||
d584f0fb | 438 | config ARC_HAS_GFRC |
72d72880 VG |
439 | bool "SMP synchronized 64-bit cycle counter" |
440 | default y | |
441 | depends on SMP | |
442 | ||
1f6ccfff VG |
443 | config ARC_NUMBER_OF_INTERRUPTS |
444 | int "Number of interrupts" | |
445 | range 8 240 | |
446 | default 32 | |
447 | help | |
448 | This defines the number of interrupts on the ARCv2HS core. | |
449 | It affects the size of vector table. | |
450 | The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable | |
451 | in hardware, it keep things simple for Linux to assume they are always | |
452 | present. | |
453 | ||
454 | endif # ISA_ARCV2 | |
455 | ||
cfdbc2e1 VG |
456 | endmenu # "ARC CPU Configuration" |
457 | ||
cfdbc2e1 VG |
458 | config LINUX_LINK_BASE |
459 | hex "Linux Link Address" | |
460 | default "0x80000000" | |
461 | help | |
462 | ARC700 divides the 32 bit phy address space into two equal halves | |
463 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
464 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
465 | Typically Linux kernel is linked at the start of untransalted addr, | |
466 | hence the default value of 0x8zs. | |
467 | However some customers have peripherals mapped at this addr, so | |
468 | Linux needs to be scooted a bit. | |
469 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 470 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 471 | |
45890f6d VG |
472 | config HIGHMEM |
473 | bool "High Memory Support" | |
26f9d5fd | 474 | select DISCONTIGMEM |
45890f6d VG |
475 | help |
476 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
477 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
478 | in future | |
479 | ||
5a364c2a VG |
480 | config ARC_HAS_PAE40 |
481 | bool "Support for the 40-bit Physical Address Extension" | |
482 | default n | |
483 | depends on ISA_ARCV2 | |
5a364c2a VG |
484 | help |
485 | Enable access to physical memory beyond 4G, only supported on | |
486 | ARC cores with 40 bit Physical Addressing support | |
487 | ||
488 | config ARCH_PHYS_ADDR_T_64BIT | |
489 | def_bool ARC_HAS_PAE40 | |
490 | ||
491 | config ARCH_DMA_ADDR_T_64BIT | |
492 | bool | |
493 | ||
f2e3d553 VG |
494 | config ARC_PLAT_NEEDS_PHYS_TO_DMA |
495 | bool | |
496 | ||
15ca68a9 NC |
497 | config ARC_KVADDR_SIZE |
498 | int "Kernel Virtaul Address Space size (MB)" | |
499 | range 0 512 | |
500 | default "256" | |
501 | help | |
502 | The kernel address space is carved out of 256MB of translated address | |
503 | space for catering to vmalloc, modules, pkmap, fixmap. This however may | |
504 | not suffice vmalloc requirements of a 4K CPU EZChip system. So allow | |
505 | this to be stretched to 512 MB (by extending into the reserved | |
506 | kernel-user gutter) | |
507 | ||
080c3747 VG |
508 | config ARC_CURR_IN_REG |
509 | bool "Dedicate Register r25 for current_task pointer" | |
510 | default y | |
511 | help | |
512 | This reserved Register R25 to point to Current Task in | |
513 | kernel mode. This saves memory access for each such access | |
514 | ||
2e651ea1 | 515 | |
1736a56f | 516 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 517 | bool "Emulate unaligned memory access (userspace only)" |
1f6ccfff | 518 | default N |
2e651ea1 VG |
519 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
520 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 521 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
522 | help |
523 | This enables misaligned 16 & 32 bit memory access from user space. | |
524 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
525 | potential bugs in code | |
526 | ||
cfdbc2e1 VG |
527 | config HZ |
528 | int "Timer Frequency" | |
529 | default 100 | |
530 | ||
cbe056f7 VG |
531 | config ARC_METAWARE_HLINK |
532 | bool "Support for Metaware debugger assisted Host access" | |
533 | default n | |
534 | help | |
535 | This options allows a Linux userland apps to directly access | |
536 | host file system (open/creat/read/write etc) with help from | |
537 | Metaware Debugger. This can come in handy for Linux-host communication | |
538 | when there is no real usable peripheral such as EMAC. | |
539 | ||
cfdbc2e1 VG |
540 | menuconfig ARC_DBG |
541 | bool "ARC debugging" | |
542 | default y | |
543 | ||
aa6083ed VG |
544 | if ARC_DBG |
545 | ||
854a0d95 VG |
546 | config ARC_DW2_UNWIND |
547 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
548 | default y |
549 | select KALLSYMS | |
550 | help | |
551 | Compiles the kernel with DWARF unwind information and can be used | |
552 | to get stack backtraces. | |
553 | ||
554 | If you say Y here the resulting kernel image will be slightly larger | |
555 | but not slower, and it will give very useful debugging information. | |
556 | If you don't debug the kernel, you can say N, but we may not be able | |
557 | to solve problems without frame unwind information | |
558 | ||
cfdbc2e1 VG |
559 | config ARC_DBG_TLB_PARANOIA |
560 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 VG |
561 | default n |
562 | ||
563 | config ARC_DBG_TLB_MISS_COUNT | |
564 | bool "Profile TLB Misses" | |
565 | default n | |
566 | select DEBUG_FS | |
cfdbc2e1 VG |
567 | help |
568 | Counts number of I and D TLB Misses and exports them via Debugfs | |
569 | The counters can be cleared via Debugfs as well | |
570 | ||
aa6083ed VG |
571 | endif |
572 | ||
036b2c56 VG |
573 | config ARC_UBOOT_SUPPORT |
574 | bool "Support uboot arg Handling" | |
575 | default n | |
576 | help | |
577 | ARC Linux by default checks for uboot provided args as pointers to | |
578 | external cmdline or DTB. This however breaks in absence of uboot, | |
579 | when booting from Metaware debugger directly, as the registers are | |
580 | not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus | |
581 | registers look like uboot args to kernel which then chokes. | |
582 | So only enable the uboot arg checking/processing if users are sure | |
583 | of uboot being in play. | |
584 | ||
999159a5 VG |
585 | config ARC_BUILTIN_DTB_NAME |
586 | string "Built in DTB" | |
587 | help | |
588 | Set the name of the DTB to embed in the vmlinux binary | |
589 | Leaving it blank selects the minimal "skeleton" dtb | |
590 | ||
cfdbc2e1 VG |
591 | source "kernel/Kconfig.preempt" |
592 | ||
5628832f VG |
593 | menu "Executable file formats" |
594 | source "fs/Kconfig.binfmt" | |
595 | endmenu | |
596 | ||
cfdbc2e1 VG |
597 | endmenu # "ARC Architecture Configuration" |
598 | ||
599 | source "mm/Kconfig" | |
37eda9df VG |
600 | |
601 | config FORCE_MAX_ZONEORDER | |
602 | int "Maximum zone order" | |
603 | default "12" if ARC_HUGEPAGE_16M | |
604 | default "11" | |
605 | ||
cfdbc2e1 VG |
606 | source "net/Kconfig" |
607 | source "drivers/Kconfig" | |
c1678ffc JP |
608 | |
609 | menu "Bus Support" | |
610 | ||
611 | config PCI | |
612 | bool "PCI support" if MIGHT_HAVE_PCI | |
613 | help | |
614 | PCI is the name of a bus system, i.e., the way the CPU talks to | |
615 | the other stuff inside your box. Find out if your board/platform | |
616 | has PCI. | |
617 | ||
618 | Note: PCIe support for Synopsys Device will be available only | |
619 | when HAPS DX is configured with PCIe RC bitmap. If you have PCI, | |
620 | say Y, otherwise N. | |
621 | ||
622 | config PCI_SYSCALL | |
623 | def_bool PCI | |
624 | ||
625 | source "drivers/pci/Kconfig" | |
c1678ffc JP |
626 | |
627 | endmenu | |
628 | ||
cfdbc2e1 VG |
629 | source "fs/Kconfig" |
630 | source "arch/arc/Kconfig.debug" | |
631 | source "security/Kconfig" | |
632 | source "crypto/Kconfig" | |
633 | source "lib/Kconfig" | |
996bad6c | 634 | source "kernel/power/Kconfig" |