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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
2a440168 | 11 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
f06d19e4 | 12 | select BUILDTIME_EXTABLE_SORT |
d7f8a085 | 13 | select COMMON_CLK |
4adeefe1 | 14 | select CLONE_BACKWARDS |
cfdbc2e1 VG |
15 | select GENERIC_ATOMIC64 |
16 | select GENERIC_CLOCKEVENTS | |
17 | select GENERIC_FIND_FIRST_BIT | |
18 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
19 | select GENERIC_IRQ_SHOW | |
c1678ffc | 20 | select GENERIC_PCI_IOMAP |
cfdbc2e1 VG |
21 | select GENERIC_PENDING_IRQ if SMP |
22 | select GENERIC_SMP_IDLE_THREAD | |
f46121bd | 23 | select HAVE_ARCH_KGDB |
547f1125 | 24 | select HAVE_ARCH_TRACEHOOK |
5e057429 | 25 | select HAVE_FUTEX_CMPXCHG |
4368902b | 26 | select HAVE_IOREMAP_PROT |
4d86dfbb VG |
27 | select HAVE_KPROBES |
28 | select HAVE_KRETPROBES | |
c121c506 | 29 | select HAVE_MEMBLOCK |
854a0d95 | 30 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 31 | select HAVE_OPROFILE |
9c57564e | 32 | select HAVE_PERF_EVENTS |
999159a5 | 33 | select IRQ_DOMAIN |
cfdbc2e1 | 34 | select MODULES_USE_ELF_RELA |
c121c506 | 35 | select NO_BOOTMEM |
999159a5 VG |
36 | select OF |
37 | select OF_EARLY_FLATTREE | |
9c57564e | 38 | select PERF_USE_VMALLOC |
d1a1dc0b | 39 | select HAVE_DEBUG_STACKOVERFLOW |
cfdbc2e1 | 40 | |
c1678ffc JP |
41 | config MIGHT_HAVE_PCI |
42 | bool | |
43 | ||
0dafafc3 VG |
44 | config TRACE_IRQFLAGS_SUPPORT |
45 | def_bool y | |
46 | ||
47 | config LOCKDEP_SUPPORT | |
48 | def_bool y | |
49 | ||
cfdbc2e1 VG |
50 | config SCHED_OMIT_FRAME_POINTER |
51 | def_bool y | |
52 | ||
53 | config GENERIC_CSUM | |
54 | def_bool y | |
55 | ||
56 | config RWSEM_GENERIC_SPINLOCK | |
57 | def_bool y | |
58 | ||
59 | config ARCH_FLATMEM_ENABLE | |
60 | def_bool y | |
61 | ||
62 | config MMU | |
63 | def_bool y | |
64 | ||
ce816fa8 | 65 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
66 | def_bool y |
67 | ||
68 | config GENERIC_CALIBRATE_DELAY | |
69 | def_bool y | |
70 | ||
71 | config GENERIC_HWEIGHT | |
72 | def_bool y | |
73 | ||
44c8bb91 VG |
74 | config STACKTRACE_SUPPORT |
75 | def_bool y | |
76 | select STACKTRACE | |
77 | ||
fe6c1b86 VG |
78 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
79 | def_bool y | |
80 | depends on ARC_MMU_V4 | |
81 | ||
cfdbc2e1 VG |
82 | source "init/Kconfig" |
83 | source "kernel/Kconfig.freezer" | |
84 | ||
85 | menu "ARC Architecture Configuration" | |
86 | ||
93ad700d | 87 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 88 | |
fd155792 | 89 | source "arch/arc/plat-sim/Kconfig" |
072eb693 | 90 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 91 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 92 | #New platform adds here |
93ad700d | 93 | |
53d98958 | 94 | endmenu |
cfdbc2e1 | 95 | |
1f6ccfff VG |
96 | choice |
97 | prompt "ARC Instruction Set" | |
98 | default ISA_ARCOMPACT | |
99 | ||
100 | config ISA_ARCOMPACT | |
101 | bool "ARCompact ISA" | |
102 | help | |
103 | The original ARC ISA of ARC600/700 cores | |
104 | ||
65bfbcdf VG |
105 | config ISA_ARCV2 |
106 | bool "ARC ISA v2" | |
107 | help | |
108 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
109 | |
110 | endchoice | |
111 | ||
cfdbc2e1 VG |
112 | menu "ARC CPU Configuration" |
113 | ||
114 | choice | |
115 | prompt "ARC Core" | |
1f6ccfff VG |
116 | default ARC_CPU_770 if ISA_ARCOMPACT |
117 | default ARC_CPU_HS if ISA_ARCV2 | |
118 | ||
119 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
120 | |
121 | config ARC_CPU_750D | |
122 | bool "ARC750D" | |
14a0abfc | 123 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
124 | help |
125 | Support for ARC750 core | |
126 | ||
127 | config ARC_CPU_770 | |
128 | bool "ARC770" | |
742f8af6 | 129 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
130 | help |
131 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
132 | This core has a bunch of cool new features: | |
133 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
134 | Shared Address Spaces (for sharing TLB entires in MMU) | |
135 | -Caches: New Prog Model, Region Flush | |
136 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
137 | ||
1f6ccfff VG |
138 | endif #ISA_ARCOMPACT |
139 | ||
140 | config ARC_CPU_HS | |
141 | bool "ARC-HS" | |
142 | depends on ISA_ARCV2 | |
143 | help | |
144 | Support for ARC HS38x Cores based on ARCv2 ISA | |
145 | The notable features are: | |
146 | - SMP configurations of upto 4 core with coherency | |
147 | - Optional L2 Cache and IO-Coherency | |
148 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
149 | auto stack switch, auto regfile save/restore) | |
150 | - MMUv4 (PIPT dcache, Huge Pages) | |
151 | - Instructions for | |
152 | * 64bit load/store: LDD, STD | |
153 | * Hardware assisted divide/remainder: DIV, REM | |
154 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
155 | * IRQ enable/disable: CLRI, SETI | |
156 | * pop count: FFS, FLS | |
157 | * SETcc, BMSKN, XBFU... | |
158 | ||
cfdbc2e1 VG |
159 | endchoice |
160 | ||
161 | config CPU_BIG_ENDIAN | |
162 | bool "Enable Big Endian Mode" | |
163 | default n | |
164 | help | |
165 | Build kernel for Big Endian Mode of ARC CPU | |
166 | ||
41195d23 | 167 | config SMP |
82fea5a1 | 168 | bool "Symmetric Multi-Processing" |
41195d23 | 169 | default n |
82fea5a1 VG |
170 | select ARC_HAS_COH_CACHES if ISA_ARCV2 |
171 | select ARC_MCIP if ISA_ARCV2 | |
41195d23 | 172 | help |
82fea5a1 | 173 | This enables support for systems with more than one CPU. |
41195d23 VG |
174 | |
175 | if SMP | |
176 | ||
177 | config ARC_HAS_COH_CACHES | |
178 | def_bool n | |
179 | ||
41195d23 VG |
180 | config ARC_HAS_REENTRANT_IRQ_LV2 |
181 | def_bool n | |
182 | ||
82fea5a1 VG |
183 | config ARC_MCIP |
184 | bool "ARConnect Multicore IP (MCIP) Support " | |
185 | depends on ISA_ARCV2 | |
186 | help | |
187 | This IP block enables SMP in ARC-HS38 cores. | |
188 | It provides for cross-core interrupts, multi-core debug | |
189 | hardware semaphores, shared memory,.... | |
41195d23 VG |
190 | |
191 | config NR_CPUS | |
3aa4f80e NC |
192 | int "Maximum number of CPUs (2-4096)" |
193 | range 2 4096 | |
82fea5a1 VG |
194 | default "4" |
195 | ||
3971cdc2 VG |
196 | config ARC_SMP_HALT_ON_RESET |
197 | bool "Enable Halt-on-reset boot mode" | |
198 | default y if ARC_UBOOT_SUPPORT | |
199 | help | |
200 | In SMP configuration cores can be configured as Halt-on-reset | |
201 | or they could all start at same time. For Halt-on-reset, non | |
202 | masters are parked until Master kicks them so they can start of | |
203 | at designated entry point. For other case, all jump to common | |
204 | entry point and spin wait for Master's signal. | |
205 | ||
82fea5a1 | 206 | endif #SMP |
41195d23 | 207 | |
cfdbc2e1 VG |
208 | menuconfig ARC_CACHE |
209 | bool "Enable Cache Support" | |
210 | default y | |
41195d23 VG |
211 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
212 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
213 | |
214 | if ARC_CACHE | |
215 | ||
216 | config ARC_CACHE_LINE_SHIFT | |
217 | int "Cache Line Length (as power of 2)" | |
218 | range 5 7 | |
219 | default "6" | |
220 | help | |
221 | Starting with ARC700 4.9, Cache line length is configurable, | |
222 | This option specifies "N", with Line-len = 2 power N | |
223 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
224 | Linux only supports same line lengths for I and D caches. | |
225 | ||
226 | config ARC_HAS_ICACHE | |
227 | bool "Use Instruction Cache" | |
228 | default y | |
229 | ||
230 | config ARC_HAS_DCACHE | |
231 | bool "Use Data Cache" | |
232 | default y | |
233 | ||
234 | config ARC_CACHE_PAGES | |
235 | bool "Per Page Cache Control" | |
236 | default y | |
237 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
238 | help | |
239 | This can be used to over-ride the global I/D Cache Enable on a | |
240 | per-page basis (but only for pages accessed via MMU such as | |
241 | Kernel Virtual address or User Virtual Address) | |
242 | TLB entries have a per-page Cache Enable Bit. | |
243 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
244 | Global DISABLE + Per Page ENABLE won't work | |
245 | ||
4102b533 VG |
246 | config ARC_CACHE_VIPT_ALIASING |
247 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 248 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 VG |
249 | default n |
250 | ||
cfdbc2e1 VG |
251 | endif #ARC_CACHE |
252 | ||
8b5850f8 VG |
253 | config ARC_HAS_ICCM |
254 | bool "Use ICCM" | |
255 | help | |
256 | Single Cycle RAMS to store Fast Path Code | |
257 | default n | |
258 | ||
259 | config ARC_ICCM_SZ | |
260 | int "ICCM Size in KB" | |
261 | default "64" | |
262 | depends on ARC_HAS_ICCM | |
263 | ||
264 | config ARC_HAS_DCCM | |
265 | bool "Use DCCM" | |
266 | help | |
267 | Single Cycle RAMS to store Fast Path Data | |
268 | default n | |
269 | ||
270 | config ARC_DCCM_SZ | |
271 | int "DCCM Size in KB" | |
272 | default "64" | |
273 | depends on ARC_HAS_DCCM | |
274 | ||
275 | config ARC_DCCM_BASE | |
276 | hex "DCCM map address" | |
277 | default "0xA0000000" | |
278 | depends on ARC_HAS_DCCM | |
279 | ||
cfdbc2e1 | 280 | choice |
1f6ccfff | 281 | prompt "MMU Version" |
cfdbc2e1 VG |
282 | default ARC_MMU_V3 if ARC_CPU_770 |
283 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 284 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 285 | |
c583ee4f VG |
286 | if ISA_ARCOMPACT |
287 | ||
cfdbc2e1 VG |
288 | config ARC_MMU_V1 |
289 | bool "MMU v1" | |
290 | help | |
291 | Orig ARC700 MMU | |
292 | ||
293 | config ARC_MMU_V2 | |
294 | bool "MMU v2" | |
295 | help | |
296 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
297 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
298 | ||
299 | config ARC_MMU_V3 | |
300 | bool "MMU v3" | |
301 | depends on ARC_CPU_770 | |
302 | help | |
303 | Introduced with ARC700 4.10: New Features | |
304 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
305 | Shared Address Spaces (SASID) | |
306 | ||
c583ee4f VG |
307 | endif |
308 | ||
d7a512bf VG |
309 | config ARC_MMU_V4 |
310 | bool "MMU v4" | |
311 | depends on ISA_ARCV2 | |
312 | ||
cfdbc2e1 VG |
313 | endchoice |
314 | ||
315 | ||
316 | choice | |
317 | prompt "MMU Page Size" | |
318 | default ARC_PAGE_SIZE_8K | |
319 | ||
320 | config ARC_PAGE_SIZE_8K | |
321 | bool "8KB" | |
322 | help | |
323 | Choose between 8k vs 16k | |
324 | ||
325 | config ARC_PAGE_SIZE_16K | |
326 | bool "16KB" | |
450ed0db | 327 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
328 | |
329 | config ARC_PAGE_SIZE_4K | |
330 | bool "4KB" | |
450ed0db | 331 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
332 | |
333 | endchoice | |
334 | ||
37eda9df VG |
335 | choice |
336 | prompt "MMU Super Page Size" | |
337 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE | |
338 | default ARC_HUGEPAGE_2M | |
339 | ||
340 | config ARC_HUGEPAGE_2M | |
341 | bool "2MB" | |
342 | ||
343 | config ARC_HUGEPAGE_16M | |
344 | bool "16MB" | |
345 | ||
346 | endchoice | |
347 | ||
1f6ccfff VG |
348 | if ISA_ARCOMPACT |
349 | ||
4788a594 VG |
350 | config ARC_COMPACT_IRQ_LEVELS |
351 | bool "ARCompact IRQ Priorities: High(2)/Low(1)" | |
352 | default n | |
353 | # Timer HAS to be high priority, for any other high priority config | |
354 | select ARC_IRQ3_LV2 | |
41195d23 VG |
355 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
356 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | |
4788a594 VG |
357 | |
358 | if ARC_COMPACT_IRQ_LEVELS | |
359 | ||
360 | config ARC_IRQ3_LV2 | |
361 | bool | |
362 | ||
363 | config ARC_IRQ5_LV2 | |
364 | bool | |
365 | ||
366 | config ARC_IRQ6_LV2 | |
367 | bool | |
368 | ||
1f6ccfff | 369 | endif #ARC_COMPACT_IRQ_LEVELS |
4788a594 | 370 | |
cfdbc2e1 VG |
371 | config ARC_FPU_SAVE_RESTORE |
372 | bool "Enable FPU state persistence across context switch" | |
373 | default n | |
374 | help | |
375 | Double Precision Floating Point unit had dedictaed regs which | |
376 | need to be saved/restored across context-switch. | |
377 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
378 | hardware pieces to allow software to conditionally save/restore, | |
379 | based on actual usage of FPU by a task. Thus our implemn does | |
380 | this for all tasks in system. | |
381 | ||
1f6ccfff VG |
382 | endif #ISA_ARCOMPACT |
383 | ||
fbf8e13d VG |
384 | config ARC_CANT_LLSC |
385 | def_bool n | |
386 | ||
cfdbc2e1 VG |
387 | config ARC_HAS_LLSC |
388 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
389 | default y | |
14a0abfc | 390 | depends on !ARC_CANT_LLSC |
cfdbc2e1 | 391 | |
e78fdfef VG |
392 | config ARC_STAR_9000923308 |
393 | bool "Workaround for llock/scond livelock" | |
b31ac426 | 394 | default n |
e78fdfef VG |
395 | depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC |
396 | ||
cfdbc2e1 VG |
397 | config ARC_HAS_SWAPE |
398 | bool "Insn: SWAPE (endian-swap)" | |
399 | default y | |
cfdbc2e1 | 400 | |
1f6ccfff VG |
401 | if ISA_ARCV2 |
402 | ||
403 | config ARC_HAS_LL64 | |
404 | bool "Insn: 64bit LDD/STD" | |
405 | help | |
406 | Enable gcc to generate 64-bit load/store instructions | |
407 | ISA mandates even/odd registers to allow encoding of two | |
408 | dest operands with 2 possible source operands. | |
409 | default y | |
410 | ||
d05a76ab AB |
411 | config ARC_HAS_DIV_REM |
412 | bool "Insn: div, divu, rem, remu" | |
413 | default y | |
414 | ||
aa93e8ef VG |
415 | config ARC_HAS_RTC |
416 | bool "Local 64-bit r/o cycle counter" | |
417 | default n | |
418 | depends on !SMP | |
419 | ||
d584f0fb | 420 | config ARC_HAS_GFRC |
72d72880 VG |
421 | bool "SMP synchronized 64-bit cycle counter" |
422 | default y | |
423 | depends on SMP | |
424 | ||
1f6ccfff VG |
425 | config ARC_NUMBER_OF_INTERRUPTS |
426 | int "Number of interrupts" | |
427 | range 8 240 | |
428 | default 32 | |
429 | help | |
430 | This defines the number of interrupts on the ARCv2HS core. | |
431 | It affects the size of vector table. | |
432 | The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable | |
433 | in hardware, it keep things simple for Linux to assume they are always | |
434 | present. | |
435 | ||
436 | endif # ISA_ARCV2 | |
437 | ||
cfdbc2e1 VG |
438 | endmenu # "ARC CPU Configuration" |
439 | ||
cfdbc2e1 VG |
440 | config LINUX_LINK_BASE |
441 | hex "Linux Link Address" | |
442 | default "0x80000000" | |
443 | help | |
444 | ARC700 divides the 32 bit phy address space into two equal halves | |
445 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
446 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
447 | Typically Linux kernel is linked at the start of untransalted addr, | |
448 | hence the default value of 0x8zs. | |
449 | However some customers have peripherals mapped at this addr, so | |
450 | Linux needs to be scooted a bit. | |
451 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 452 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 453 | |
45890f6d VG |
454 | config HIGHMEM |
455 | bool "High Memory Support" | |
456 | help | |
457 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
458 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
459 | in future | |
460 | ||
5a364c2a VG |
461 | config ARC_HAS_PAE40 |
462 | bool "Support for the 40-bit Physical Address Extension" | |
463 | default n | |
464 | depends on ISA_ARCV2 | |
5a364c2a VG |
465 | help |
466 | Enable access to physical memory beyond 4G, only supported on | |
467 | ARC cores with 40 bit Physical Addressing support | |
468 | ||
469 | config ARCH_PHYS_ADDR_T_64BIT | |
470 | def_bool ARC_HAS_PAE40 | |
471 | ||
472 | config ARCH_DMA_ADDR_T_64BIT | |
473 | bool | |
474 | ||
f2e3d553 VG |
475 | config ARC_PLAT_NEEDS_PHYS_TO_DMA |
476 | bool | |
477 | ||
080c3747 VG |
478 | config ARC_CURR_IN_REG |
479 | bool "Dedicate Register r25 for current_task pointer" | |
480 | default y | |
481 | help | |
482 | This reserved Register R25 to point to Current Task in | |
483 | kernel mode. This saves memory access for each such access | |
484 | ||
2e651ea1 | 485 | |
1736a56f | 486 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 487 | bool "Emulate unaligned memory access (userspace only)" |
1f6ccfff | 488 | default N |
2e651ea1 VG |
489 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
490 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 491 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
492 | help |
493 | This enables misaligned 16 & 32 bit memory access from user space. | |
494 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
495 | potential bugs in code | |
496 | ||
cfdbc2e1 VG |
497 | config HZ |
498 | int "Timer Frequency" | |
499 | default 100 | |
500 | ||
cbe056f7 VG |
501 | config ARC_METAWARE_HLINK |
502 | bool "Support for Metaware debugger assisted Host access" | |
503 | default n | |
504 | help | |
505 | This options allows a Linux userland apps to directly access | |
506 | host file system (open/creat/read/write etc) with help from | |
507 | Metaware Debugger. This can come in handy for Linux-host communication | |
508 | when there is no real usable peripheral such as EMAC. | |
509 | ||
cfdbc2e1 VG |
510 | menuconfig ARC_DBG |
511 | bool "ARC debugging" | |
512 | default y | |
513 | ||
aa6083ed VG |
514 | if ARC_DBG |
515 | ||
854a0d95 VG |
516 | config ARC_DW2_UNWIND |
517 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
518 | default y |
519 | select KALLSYMS | |
520 | help | |
521 | Compiles the kernel with DWARF unwind information and can be used | |
522 | to get stack backtraces. | |
523 | ||
524 | If you say Y here the resulting kernel image will be slightly larger | |
525 | but not slower, and it will give very useful debugging information. | |
526 | If you don't debug the kernel, you can say N, but we may not be able | |
527 | to solve problems without frame unwind information | |
528 | ||
cfdbc2e1 VG |
529 | config ARC_DBG_TLB_PARANOIA |
530 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 VG |
531 | default n |
532 | ||
533 | config ARC_DBG_TLB_MISS_COUNT | |
534 | bool "Profile TLB Misses" | |
535 | default n | |
536 | select DEBUG_FS | |
cfdbc2e1 VG |
537 | help |
538 | Counts number of I and D TLB Misses and exports them via Debugfs | |
539 | The counters can be cleared via Debugfs as well | |
540 | ||
aa6083ed VG |
541 | endif |
542 | ||
036b2c56 VG |
543 | config ARC_UBOOT_SUPPORT |
544 | bool "Support uboot arg Handling" | |
545 | default n | |
546 | help | |
547 | ARC Linux by default checks for uboot provided args as pointers to | |
548 | external cmdline or DTB. This however breaks in absence of uboot, | |
549 | when booting from Metaware debugger directly, as the registers are | |
550 | not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus | |
551 | registers look like uboot args to kernel which then chokes. | |
552 | So only enable the uboot arg checking/processing if users are sure | |
553 | of uboot being in play. | |
554 | ||
999159a5 VG |
555 | config ARC_BUILTIN_DTB_NAME |
556 | string "Built in DTB" | |
557 | help | |
558 | Set the name of the DTB to embed in the vmlinux binary | |
559 | Leaving it blank selects the minimal "skeleton" dtb | |
560 | ||
cfdbc2e1 VG |
561 | source "kernel/Kconfig.preempt" |
562 | ||
5628832f VG |
563 | menu "Executable file formats" |
564 | source "fs/Kconfig.binfmt" | |
565 | endmenu | |
566 | ||
cfdbc2e1 VG |
567 | endmenu # "ARC Architecture Configuration" |
568 | ||
569 | source "mm/Kconfig" | |
37eda9df VG |
570 | |
571 | config FORCE_MAX_ZONEORDER | |
572 | int "Maximum zone order" | |
573 | default "12" if ARC_HUGEPAGE_16M | |
574 | default "11" | |
575 | ||
cfdbc2e1 VG |
576 | source "net/Kconfig" |
577 | source "drivers/Kconfig" | |
c1678ffc JP |
578 | |
579 | menu "Bus Support" | |
580 | ||
581 | config PCI | |
582 | bool "PCI support" if MIGHT_HAVE_PCI | |
583 | help | |
584 | PCI is the name of a bus system, i.e., the way the CPU talks to | |
585 | the other stuff inside your box. Find out if your board/platform | |
586 | has PCI. | |
587 | ||
588 | Note: PCIe support for Synopsys Device will be available only | |
589 | when HAPS DX is configured with PCIe RC bitmap. If you have PCI, | |
590 | say Y, otherwise N. | |
591 | ||
592 | config PCI_SYSCALL | |
593 | def_bool PCI | |
594 | ||
595 | source "drivers/pci/Kconfig" | |
596 | source "drivers/pci/pcie/Kconfig" | |
597 | ||
598 | endmenu | |
599 | ||
cfdbc2e1 VG |
600 | source "fs/Kconfig" |
601 | source "arch/arc/Kconfig.debug" | |
602 | source "security/Kconfig" | |
603 | source "crypto/Kconfig" | |
604 | source "lib/Kconfig" | |
996bad6c | 605 | source "kernel/power/Kconfig" |