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cfdbc2e1 VG |
1 | # |
2 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | # | |
4 | # This program is free software; you can redistribute it and/or modify | |
5 | # it under the terms of the GNU General Public License version 2 as | |
6 | # published by the Free Software Foundation. | |
7 | # | |
8 | ||
9 | config ARC | |
10 | def_bool y | |
f06d19e4 | 11 | select BUILDTIME_EXTABLE_SORT |
d7f8a085 | 12 | select COMMON_CLK |
4adeefe1 | 13 | select CLONE_BACKWARDS |
cfdbc2e1 VG |
14 | # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev |
15 | select DEVTMPFS if !INITRAMFS_SOURCE="" | |
16 | select GENERIC_ATOMIC64 | |
17 | select GENERIC_CLOCKEVENTS | |
18 | select GENERIC_FIND_FIRST_BIT | |
19 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
20 | select GENERIC_IRQ_SHOW | |
21 | select GENERIC_PENDING_IRQ if SMP | |
22 | select GENERIC_SMP_IDLE_THREAD | |
f46121bd | 23 | select HAVE_ARCH_KGDB |
547f1125 | 24 | select HAVE_ARCH_TRACEHOOK |
4368902b | 25 | select HAVE_IOREMAP_PROT |
4d86dfbb VG |
26 | select HAVE_KPROBES |
27 | select HAVE_KRETPROBES | |
c121c506 | 28 | select HAVE_MEMBLOCK |
854a0d95 | 29 | select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND |
769bc1fd | 30 | select HAVE_OPROFILE |
9c57564e | 31 | select HAVE_PERF_EVENTS |
999159a5 | 32 | select IRQ_DOMAIN |
cfdbc2e1 | 33 | select MODULES_USE_ELF_RELA |
c121c506 | 34 | select NO_BOOTMEM |
999159a5 VG |
35 | select OF |
36 | select OF_EARLY_FLATTREE | |
9c57564e | 37 | select PERF_USE_VMALLOC |
d1a1dc0b | 38 | select HAVE_DEBUG_STACKOVERFLOW |
cfdbc2e1 | 39 | |
0dafafc3 VG |
40 | config TRACE_IRQFLAGS_SUPPORT |
41 | def_bool y | |
42 | ||
43 | config LOCKDEP_SUPPORT | |
44 | def_bool y | |
45 | ||
cfdbc2e1 VG |
46 | config SCHED_OMIT_FRAME_POINTER |
47 | def_bool y | |
48 | ||
49 | config GENERIC_CSUM | |
50 | def_bool y | |
51 | ||
52 | config RWSEM_GENERIC_SPINLOCK | |
53 | def_bool y | |
54 | ||
55 | config ARCH_FLATMEM_ENABLE | |
56 | def_bool y | |
57 | ||
58 | config MMU | |
59 | def_bool y | |
60 | ||
ce816fa8 | 61 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
62 | def_bool y |
63 | ||
64 | config GENERIC_CALIBRATE_DELAY | |
65 | def_bool y | |
66 | ||
67 | config GENERIC_HWEIGHT | |
68 | def_bool y | |
69 | ||
44c8bb91 VG |
70 | config STACKTRACE_SUPPORT |
71 | def_bool y | |
72 | select STACKTRACE | |
73 | ||
cfdbc2e1 VG |
74 | config HAVE_LATENCYTOP_SUPPORT |
75 | def_bool y | |
76 | ||
cfdbc2e1 VG |
77 | source "init/Kconfig" |
78 | source "kernel/Kconfig.freezer" | |
79 | ||
80 | menu "ARC Architecture Configuration" | |
81 | ||
93ad700d | 82 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 83 | |
fd155792 | 84 | source "arch/arc/plat-sim/Kconfig" |
072eb693 | 85 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 86 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 87 | #New platform adds here |
93ad700d | 88 | |
53d98958 | 89 | endmenu |
cfdbc2e1 | 90 | |
1f6ccfff VG |
91 | choice |
92 | prompt "ARC Instruction Set" | |
93 | default ISA_ARCOMPACT | |
94 | ||
95 | config ISA_ARCOMPACT | |
96 | bool "ARCompact ISA" | |
97 | help | |
98 | The original ARC ISA of ARC600/700 cores | |
99 | ||
100 | ### For bisectability, disable ARCv2 support until we have all the bits in place | |
101 | #config ISA_ARCV2 | |
102 | # bool "ARC ISA v2" | |
103 | # help | |
104 | # ISA for the Next Generation ARC-HS cores | |
105 | ||
106 | endchoice | |
107 | ||
cfdbc2e1 VG |
108 | menu "ARC CPU Configuration" |
109 | ||
110 | choice | |
111 | prompt "ARC Core" | |
1f6ccfff VG |
112 | default ARC_CPU_770 if ISA_ARCOMPACT |
113 | default ARC_CPU_HS if ISA_ARCV2 | |
114 | ||
115 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
116 | |
117 | config ARC_CPU_750D | |
118 | bool "ARC750D" | |
119 | help | |
120 | Support for ARC750 core | |
121 | ||
122 | config ARC_CPU_770 | |
123 | bool "ARC770" | |
742f8af6 | 124 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
125 | help |
126 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
127 | This core has a bunch of cool new features: | |
128 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
129 | Shared Address Spaces (for sharing TLB entires in MMU) | |
130 | -Caches: New Prog Model, Region Flush | |
131 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
132 | ||
1f6ccfff VG |
133 | endif #ISA_ARCOMPACT |
134 | ||
135 | config ARC_CPU_HS | |
136 | bool "ARC-HS" | |
137 | depends on ISA_ARCV2 | |
138 | help | |
139 | Support for ARC HS38x Cores based on ARCv2 ISA | |
140 | The notable features are: | |
141 | - SMP configurations of upto 4 core with coherency | |
142 | - Optional L2 Cache and IO-Coherency | |
143 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
144 | auto stack switch, auto regfile save/restore) | |
145 | - MMUv4 (PIPT dcache, Huge Pages) | |
146 | - Instructions for | |
147 | * 64bit load/store: LDD, STD | |
148 | * Hardware assisted divide/remainder: DIV, REM | |
149 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
150 | * IRQ enable/disable: CLRI, SETI | |
151 | * pop count: FFS, FLS | |
152 | * SETcc, BMSKN, XBFU... | |
153 | ||
cfdbc2e1 VG |
154 | endchoice |
155 | ||
156 | config CPU_BIG_ENDIAN | |
157 | bool "Enable Big Endian Mode" | |
158 | default n | |
159 | help | |
160 | Build kernel for Big Endian Mode of ARC CPU | |
161 | ||
41195d23 VG |
162 | config SMP |
163 | bool "Symmetric Multi-Processing (Incomplete)" | |
164 | default n | |
41195d23 VG |
165 | help |
166 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
167 | a system with only one CPU, say N. If you have a system with more |
168 | than one CPU, say Y. | |
41195d23 VG |
169 | |
170 | if SMP | |
171 | ||
172 | config ARC_HAS_COH_CACHES | |
173 | def_bool n | |
174 | ||
41195d23 VG |
175 | config ARC_HAS_REENTRANT_IRQ_LV2 |
176 | def_bool n | |
177 | ||
1f6ccfff | 178 | endif #SMP |
41195d23 VG |
179 | |
180 | config NR_CPUS | |
3aa4f80e NC |
181 | int "Maximum number of CPUs (2-4096)" |
182 | range 2 4096 | |
41195d23 VG |
183 | depends on SMP |
184 | default "2" | |
185 | ||
cfdbc2e1 VG |
186 | menuconfig ARC_CACHE |
187 | bool "Enable Cache Support" | |
188 | default y | |
41195d23 VG |
189 | # if SMP, cache enabled ONLY if ARC implementation has cache coherency |
190 | depends on !SMP || ARC_HAS_COH_CACHES | |
cfdbc2e1 VG |
191 | |
192 | if ARC_CACHE | |
193 | ||
194 | config ARC_CACHE_LINE_SHIFT | |
195 | int "Cache Line Length (as power of 2)" | |
196 | range 5 7 | |
197 | default "6" | |
198 | help | |
199 | Starting with ARC700 4.9, Cache line length is configurable, | |
200 | This option specifies "N", with Line-len = 2 power N | |
201 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
202 | Linux only supports same line lengths for I and D caches. | |
203 | ||
204 | config ARC_HAS_ICACHE | |
205 | bool "Use Instruction Cache" | |
206 | default y | |
207 | ||
208 | config ARC_HAS_DCACHE | |
209 | bool "Use Data Cache" | |
210 | default y | |
211 | ||
212 | config ARC_CACHE_PAGES | |
213 | bool "Per Page Cache Control" | |
214 | default y | |
215 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
216 | help | |
217 | This can be used to over-ride the global I/D Cache Enable on a | |
218 | per-page basis (but only for pages accessed via MMU such as | |
219 | Kernel Virtual address or User Virtual Address) | |
220 | TLB entries have a per-page Cache Enable Bit. | |
221 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
222 | Global DISABLE + Per Page ENABLE won't work | |
223 | ||
4102b533 VG |
224 | config ARC_CACHE_VIPT_ALIASING |
225 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 226 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 VG |
227 | default n |
228 | ||
cfdbc2e1 VG |
229 | endif #ARC_CACHE |
230 | ||
8b5850f8 VG |
231 | config ARC_HAS_ICCM |
232 | bool "Use ICCM" | |
233 | help | |
234 | Single Cycle RAMS to store Fast Path Code | |
235 | default n | |
236 | ||
237 | config ARC_ICCM_SZ | |
238 | int "ICCM Size in KB" | |
239 | default "64" | |
240 | depends on ARC_HAS_ICCM | |
241 | ||
242 | config ARC_HAS_DCCM | |
243 | bool "Use DCCM" | |
244 | help | |
245 | Single Cycle RAMS to store Fast Path Data | |
246 | default n | |
247 | ||
248 | config ARC_DCCM_SZ | |
249 | int "DCCM Size in KB" | |
250 | default "64" | |
251 | depends on ARC_HAS_DCCM | |
252 | ||
253 | config ARC_DCCM_BASE | |
254 | hex "DCCM map address" | |
255 | default "0xA0000000" | |
256 | depends on ARC_HAS_DCCM | |
257 | ||
cfdbc2e1 VG |
258 | config ARC_HAS_HW_MPY |
259 | bool "Use Hardware Multiplier (Normal or Faster XMAC)" | |
260 | default y | |
261 | help | |
262 | Influences how gcc generates code for MPY operations. | |
263 | If enabled, MPYxx insns are generated, provided by Standard/XMAC | |
264 | Multipler. Otherwise software multipy lib is used | |
265 | ||
266 | choice | |
1f6ccfff | 267 | prompt "MMU Version" |
cfdbc2e1 VG |
268 | default ARC_MMU_V3 if ARC_CPU_770 |
269 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 270 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 VG |
271 | |
272 | config ARC_MMU_V1 | |
273 | bool "MMU v1" | |
274 | help | |
275 | Orig ARC700 MMU | |
276 | ||
277 | config ARC_MMU_V2 | |
278 | bool "MMU v2" | |
279 | help | |
280 | Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio | |
281 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. | |
282 | ||
283 | config ARC_MMU_V3 | |
284 | bool "MMU v3" | |
285 | depends on ARC_CPU_770 | |
286 | help | |
287 | Introduced with ARC700 4.10: New Features | |
288 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
289 | Shared Address Spaces (SASID) | |
290 | ||
d7a512bf VG |
291 | config ARC_MMU_V4 |
292 | bool "MMU v4" | |
293 | depends on ISA_ARCV2 | |
294 | ||
cfdbc2e1 VG |
295 | endchoice |
296 | ||
297 | ||
298 | choice | |
299 | prompt "MMU Page Size" | |
300 | default ARC_PAGE_SIZE_8K | |
301 | ||
302 | config ARC_PAGE_SIZE_8K | |
303 | bool "8KB" | |
304 | help | |
305 | Choose between 8k vs 16k | |
306 | ||
307 | config ARC_PAGE_SIZE_16K | |
308 | bool "16KB" | |
309 | depends on ARC_MMU_V3 | |
310 | ||
311 | config ARC_PAGE_SIZE_4K | |
312 | bool "4KB" | |
313 | depends on ARC_MMU_V3 | |
314 | ||
315 | endchoice | |
316 | ||
1f6ccfff VG |
317 | if ISA_ARCOMPACT |
318 | ||
4788a594 VG |
319 | config ARC_COMPACT_IRQ_LEVELS |
320 | bool "ARCompact IRQ Priorities: High(2)/Low(1)" | |
321 | default n | |
322 | # Timer HAS to be high priority, for any other high priority config | |
323 | select ARC_IRQ3_LV2 | |
41195d23 VG |
324 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
325 | depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 | |
4788a594 VG |
326 | |
327 | if ARC_COMPACT_IRQ_LEVELS | |
328 | ||
329 | config ARC_IRQ3_LV2 | |
330 | bool | |
331 | ||
332 | config ARC_IRQ5_LV2 | |
333 | bool | |
334 | ||
335 | config ARC_IRQ6_LV2 | |
336 | bool | |
337 | ||
1f6ccfff | 338 | endif #ARC_COMPACT_IRQ_LEVELS |
4788a594 | 339 | |
cfdbc2e1 VG |
340 | config ARC_FPU_SAVE_RESTORE |
341 | bool "Enable FPU state persistence across context switch" | |
342 | default n | |
343 | help | |
344 | Double Precision Floating Point unit had dedictaed regs which | |
345 | need to be saved/restored across context-switch. | |
346 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
347 | hardware pieces to allow software to conditionally save/restore, | |
348 | based on actual usage of FPU by a task. Thus our implemn does | |
349 | this for all tasks in system. | |
350 | ||
1f6ccfff VG |
351 | endif #ISA_ARCOMPACT |
352 | ||
fbf8e13d VG |
353 | config ARC_CANT_LLSC |
354 | def_bool n | |
355 | ||
cfdbc2e1 VG |
356 | config ARC_HAS_LLSC |
357 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
358 | default y | |
1f6ccfff | 359 | depends on !ARC_CPU_750D && !ARC_CANT_LLSC |
cfdbc2e1 VG |
360 | |
361 | config ARC_HAS_SWAPE | |
362 | bool "Insn: SWAPE (endian-swap)" | |
363 | default y | |
cfdbc2e1 | 364 | |
1f6ccfff VG |
365 | if ISA_ARCV2 |
366 | ||
367 | config ARC_HAS_LL64 | |
368 | bool "Insn: 64bit LDD/STD" | |
369 | help | |
370 | Enable gcc to generate 64-bit load/store instructions | |
371 | ISA mandates even/odd registers to allow encoding of two | |
372 | dest operands with 2 possible source operands. | |
373 | default y | |
374 | ||
aa93e8ef VG |
375 | config ARC_HAS_RTC |
376 | bool "Local 64-bit r/o cycle counter" | |
377 | default n | |
378 | depends on !SMP | |
379 | ||
1f6ccfff VG |
380 | config ARC_NUMBER_OF_INTERRUPTS |
381 | int "Number of interrupts" | |
382 | range 8 240 | |
383 | default 32 | |
384 | help | |
385 | This defines the number of interrupts on the ARCv2HS core. | |
386 | It affects the size of vector table. | |
387 | The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable | |
388 | in hardware, it keep things simple for Linux to assume they are always | |
389 | present. | |
390 | ||
391 | endif # ISA_ARCV2 | |
392 | ||
cfdbc2e1 VG |
393 | endmenu # "ARC CPU Configuration" |
394 | ||
cfdbc2e1 VG |
395 | config LINUX_LINK_BASE |
396 | hex "Linux Link Address" | |
397 | default "0x80000000" | |
398 | help | |
399 | ARC700 divides the 32 bit phy address space into two equal halves | |
400 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
401 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
402 | Typically Linux kernel is linked at the start of untransalted addr, | |
403 | hence the default value of 0x8zs. | |
404 | However some customers have peripherals mapped at this addr, so | |
405 | Linux needs to be scooted a bit. | |
406 | If you don't know what the above means, leave this setting alone. | |
407 | ||
080c3747 VG |
408 | config ARC_CURR_IN_REG |
409 | bool "Dedicate Register r25 for current_task pointer" | |
410 | default y | |
411 | help | |
412 | This reserved Register R25 to point to Current Task in | |
413 | kernel mode. This saves memory access for each such access | |
414 | ||
2e651ea1 | 415 | |
1736a56f | 416 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 417 | bool "Emulate unaligned memory access (userspace only)" |
1f6ccfff | 418 | default N |
2e651ea1 VG |
419 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
420 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 421 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
422 | help |
423 | This enables misaligned 16 & 32 bit memory access from user space. | |
424 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
425 | potential bugs in code | |
426 | ||
cfdbc2e1 VG |
427 | config HZ |
428 | int "Timer Frequency" | |
429 | default 100 | |
430 | ||
cbe056f7 VG |
431 | config ARC_METAWARE_HLINK |
432 | bool "Support for Metaware debugger assisted Host access" | |
433 | default n | |
434 | help | |
435 | This options allows a Linux userland apps to directly access | |
436 | host file system (open/creat/read/write etc) with help from | |
437 | Metaware Debugger. This can come in handy for Linux-host communication | |
438 | when there is no real usable peripheral such as EMAC. | |
439 | ||
cfdbc2e1 VG |
440 | menuconfig ARC_DBG |
441 | bool "ARC debugging" | |
442 | default y | |
443 | ||
854a0d95 VG |
444 | config ARC_DW2_UNWIND |
445 | bool "Enable DWARF specific kernel stack unwind" | |
446 | depends on ARC_DBG | |
447 | default y | |
448 | select KALLSYMS | |
449 | help | |
450 | Compiles the kernel with DWARF unwind information and can be used | |
451 | to get stack backtraces. | |
452 | ||
453 | If you say Y here the resulting kernel image will be slightly larger | |
454 | but not slower, and it will give very useful debugging information. | |
455 | If you don't debug the kernel, you can say N, but we may not be able | |
456 | to solve problems without frame unwind information | |
457 | ||
cfdbc2e1 VG |
458 | config ARC_DBG_TLB_PARANOIA |
459 | bool "Paranoia Checks in Low Level TLB Handlers" | |
f46121bd | 460 | depends on ARC_DBG |
cfdbc2e1 VG |
461 | default n |
462 | ||
463 | config ARC_DBG_TLB_MISS_COUNT | |
464 | bool "Profile TLB Misses" | |
465 | default n | |
466 | select DEBUG_FS | |
467 | depends on ARC_DBG | |
468 | help | |
469 | Counts number of I and D TLB Misses and exports them via Debugfs | |
470 | The counters can be cleared via Debugfs as well | |
471 | ||
036b2c56 VG |
472 | config ARC_UBOOT_SUPPORT |
473 | bool "Support uboot arg Handling" | |
474 | default n | |
475 | help | |
476 | ARC Linux by default checks for uboot provided args as pointers to | |
477 | external cmdline or DTB. This however breaks in absence of uboot, | |
478 | when booting from Metaware debugger directly, as the registers are | |
479 | not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus | |
480 | registers look like uboot args to kernel which then chokes. | |
481 | So only enable the uboot arg checking/processing if users are sure | |
482 | of uboot being in play. | |
483 | ||
999159a5 VG |
484 | config ARC_BUILTIN_DTB_NAME |
485 | string "Built in DTB" | |
486 | help | |
487 | Set the name of the DTB to embed in the vmlinux binary | |
488 | Leaving it blank selects the minimal "skeleton" dtb | |
489 | ||
cfdbc2e1 VG |
490 | source "kernel/Kconfig.preempt" |
491 | ||
5628832f VG |
492 | menu "Executable file formats" |
493 | source "fs/Kconfig.binfmt" | |
494 | endmenu | |
495 | ||
cfdbc2e1 VG |
496 | endmenu # "ARC Architecture Configuration" |
497 | ||
498 | source "mm/Kconfig" | |
499 | source "net/Kconfig" | |
500 | source "drivers/Kconfig" | |
501 | source "fs/Kconfig" | |
502 | source "arch/arc/Kconfig.debug" | |
503 | source "security/Kconfig" | |
504 | source "crypto/Kconfig" | |
505 | source "lib/Kconfig" | |
996bad6c | 506 | source "kernel/power/Kconfig" |