[deliverable/linux.git] / arch / arc / include / asm / entry-compact.h

/*
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
 *  Stack switching code can no longer reliably rely on the fact that
 *  if we are NOT in user mode, stack is switched to kernel mode.
 *  e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
 *  it's prologue including stack switching from user mode
 *
 * Vineetg: Aug 28th 2008: Bug #94984
 *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
 *   Normally CPU does this automatically, however when doing FAKE rtie,
 *   we also need to explicitly do this. The problem in macros
 *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
 *   was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context
 *
 * Vineetg: May 5th 2008
 *  -Modified CALLEE_REG save/restore macros to handle the fact that
 *      r25 contains the kernel current task ptr
 *  - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
 *  - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
 *      address Write back load ld.ab instead of seperate ld/add instn
 *
 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
 */

#ifndef __ASM_ARC_ENTRY_COMPACT_H
#define __ASM_ARC_ENTRY_COMPACT_H

#include <asm/asm-offsets.h>
#include <asm/thread_info.h>	/* For THREAD_SIZE */

/*--------------------------------------------------------------
 * Switch to Kernel Mode stack if SP points to User Mode stack
 *
 * Entry   : r9 contains pre-IRQ/exception/trap status32
 * Exit    : SP is set to kernel mode stack pointer
 *           If CURR_IN_REG, r25 set to "current" task pointer
 * Clobbers: r9
 *-------------------------------------------------------------*/

.macro SWITCH_TO_KERNEL_STK

	/* User Mode when this happened ? Yes: Proceed to switch stack */
	bbit1   r9, STATUS_U_BIT, 88f

	/* OK we were already in kernel mode when this event happened, thus can
	 * assume SP is kernel mode SP. _NO_ need to do any stack switching
	 */

#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
	/* However....
	 * If Level 2 Interrupts enabled, we may end up with a corner case:
	 * 1. User Task executing
	 * 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
	 * 3. But before it could switch SP from USER to KERNEL stack
	 *      a L2 IRQ "Interrupts" L1
	 * Thay way although L2 IRQ happened in Kernel mode, stack is still
	 * not switched.
	 * To handle this, we may need to switch stack even if in kernel mode
	 * provided SP has values in range of USER mode stack ( < 0x7000_0000 )
	 */
	brlo sp, VMALLOC_START, 88f

	/* TODO: vineetg:
	 * We need to be a bit more cautious here. What if a kernel bug in
	 * L1 ISR, caused SP to go whaco (some small value which looks like
	 * USER stk) and then we take L2 ISR.
	 * Above brlo alone would treat it as a valid L1-L2 sceanrio
	 * instead of shouting alound
	 * The only feasible way is to make sure this L2 happened in
	 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
	 * L1 ISR before it switches stack
	 */

#endif

	/* Save Pre Intr/Exception KERNEL MODE SP on kernel stack
	 * safe-keeping not really needed, but it keeps the epilogue code
	 * (SP restore) simpler/uniform.
	 */
	b.d	66f
	mov	r9, sp

88: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */

	GET_CURR_TASK_ON_CPU   r9

	/* With current tsk in r9, get it's kernel mode stack base */
	GET_TSK_STACK_BASE  r9, r9

66:
#ifdef CONFIG_ARC_CURR_IN_REG
	/*
	 * Treat r25 as scratch reg, save it on stack first
	 * Load it with current task pointer
	 */
	st	r25, [r9, -4]
	GET_CURR_TASK_ON_CPU   r25
#endif

	/* Save Pre Intr/Exception User SP on kernel stack */
	st.a    sp, [r9, -16]	; Make room for orig_r0, ECR, user_r25

	/* CAUTION:
	 * SP should be set at the very end when we are done with everything
	 * In case of 2 levels of interrupt we depend on value of SP to assume
	 * that everything else is done (loading r25 etc)
	 */

	/* set SP to point to kernel mode stack */
	mov sp, r9

	/* ----- Stack Switched to kernel Mode, Now save REG FILE ----- */

.endm

/*------------------------------------------------------------
 * "FAKE" a rtie to return from CPU Exception context
 * This is to re-enable Exceptions within exception
 * Look at EV_ProtV to see how this is actually used
 *-------------------------------------------------------------*/

.macro FAKE_RET_FROM_EXCPN

	ld  r9, [sp, PT_status32]
	bic r9, r9, (STATUS_U_MASK|STATUS_DE_MASK)
	bset  r9, r9, STATUS_L_BIT
	sr  r9, [erstatus]
	mov r9, 55f
	sr  r9, [eret]

	rtie
55:
.endm

/*--------------------------------------------------------------
 * For early Exception/ISR Prologue, a core reg is temporarily needed to
 * code the rest of prolog (stack switching). This is done by stashing
 * it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
 *
 * Before saving the full regfile - this reg is restored back, only
 * to be saved again on kernel mode stack, as part of pt_regs.
 *-------------------------------------------------------------*/
.macro PROLOG_FREEUP_REG	reg, mem
#ifdef CONFIG_SMP
	sr  \reg, [ARC_REG_SCRATCH_DATA0]
#else
	st  \reg, [\mem]
#endif
.endm

.macro PROLOG_RESTORE_REG	reg, mem
#ifdef CONFIG_SMP
	lr  \reg, [ARC_REG_SCRATCH_DATA0]
#else
	ld  \reg, [\mem]
#endif
.endm

/*--------------------------------------------------------------
 * Exception Entry prologue
 * -Switches stack to K mode (if not already)
 * -Saves the register file
 *
 * After this it is safe to call the "C" handlers
 *-------------------------------------------------------------*/
.macro EXCEPTION_PROLOGUE

	/* Need at least 1 reg to code the early exception prologue */
	PROLOG_FREEUP_REG r9, @ex_saved_reg1

	/* U/K mode at time of exception (stack not switched if already K) */
	lr  r9, [erstatus]

	/* ARC700 doesn't provide auto-stack switching */
	SWITCH_TO_KERNEL_STK

	lr	r9, [ecr]
	st      r9, [sp, 8]    /* ECR */
	st      r0, [sp, 4]    /* orig_r0, needed only for sys calls */

	/* Restore r9 used to code the early prologue */
	PROLOG_RESTORE_REG  r9, @ex_saved_reg1

	SAVE_R0_TO_R12
	PUSH	gp
	PUSH	fp
	PUSH	blink
	PUSHAX	eret
	PUSHAX	erstatus
	PUSH	lp_count
	PUSHAX	lp_end
	PUSHAX	lp_start
	PUSHAX	erbta
.endm

/*--------------------------------------------------------------
 * Restore all registers used by system call or Exceptions
 * SP should always be pointing to the next free stack element
 * when entering this macro.
 *
 * NOTE:
 *
 * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
 * for memory load operations. If used in that way interrupts are deffered
 * by hardware and that is not good.
 *-------------------------------------------------------------*/
.macro EXCEPTION_EPILOGUE
	POPAX	erbta
	POPAX	lp_start
	POPAX	lp_end

	POP	r9
	mov	lp_count, r9	;LD to lp_count is not allowed

	POPAX	erstatus
	POPAX	eret
	POP	blink
	POP	fp
	POP	gp
	RESTORE_R12_TO_R0

	ld  sp, [sp] /* restore original sp */
	/* orig_r0, ECR, user_r25 skipped automatically */
.endm

/* Dummy ECR values for Interrupts */
#define event_IRQ1		0x0031abcd
#define event_IRQ2		0x0032abcd

.macro INTERRUPT_PROLOGUE  LVL

	/* free up r9 as scratchpad */
	PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg

	/* Which mode (user/kernel) was the system in when intr occured */
	lr  r9, [status32_l\LVL\()]

	SWITCH_TO_KERNEL_STK

	/* restore original r9 */
	PROLOG_RESTORE_REG  r9, @int\LVL\()_saved_reg

	/* now we are ready to save the remaining context */
	st	0x003\LVL\()abcd, [sp, 8]    /* Dummy ECR */
	st      0, [sp, 4]    /* orig_r0 , N/A for IRQ */

	SAVE_R0_TO_R12
	PUSH	gp
	PUSH	fp
	PUSH	blink
	PUSH	ilink\LVL\()
	PUSHAX	status32_l\LVL\()
	PUSH	lp_count
	PUSHAX	lp_end
	PUSHAX	lp_start
	PUSHAX	bta_l\LVL\()
.endm

/*--------------------------------------------------------------
 * Restore all registers used by interrupt handlers.
 *
 * NOTE:
 *
 * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
 * for memory load operations. If used in that way interrupts are deffered
 * by hardware and that is not good.
 *-------------------------------------------------------------*/
.macro INTERRUPT_EPILOGUE  LVL
	POPAX	bta_l\LVL\()
	POPAX	lp_start
	POPAX	lp_end

	POP	r9
	mov	lp_count, r9	;LD to lp_count is not allowed

	POPAX	status32_l\LVL\()
	POP	ilink\LVL\()
	POP	blink
	POP	fp
	POP	gp
	RESTORE_R12_TO_R0

	ld  sp, [sp] /* restore original sp */
	/* orig_r0, ECR, user_r25 skipped automatically */
.endm

/* Get thread_info of "current" tsk */
.macro GET_CURR_THR_INFO_FROM_SP  reg
	bic \reg, sp, (THREAD_SIZE - 1)
.endm

/* Get CPU-ID of this core */
.macro  GET_CPU_ID  reg
	lr  \reg, [identity]
	lsr \reg, \reg, 8
	bmsk \reg, \reg, 7
.endm

#endif  /* __ASM_ARC_ENTRY_COMPACT_H */
Commit	Line	Data
6d1a20b1 VG	1	/*
	2	* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
	3	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* Vineetg: March 2009 (Supporting 2 levels of Interrupts)
	10	* Stack switching code can no longer reliably rely on the fact that
	11	* if we are NOT in user mode, stack is switched to kernel mode.
	12	* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
	13	* it's prologue including stack switching from user mode
	14	*
	15	* Vineetg: Aug 28th 2008: Bug #94984
	16	* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
	17	* Normally CPU does this automatically, however when doing FAKE rtie,
	18	* we also need to explicitly do this. The problem in macros
	19	* FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
	20	* was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context
	21	*
	22	* Vineetg: May 5th 2008
	23	* -Modified CALLEE_REG save/restore macros to handle the fact that
	24	* r25 contains the kernel current task ptr
	25	* - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
	26	* - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
	27	* address Write back load ld.ab instead of seperate ld/add instn
	28	*
	29	* Amit Bhor, Sameer Dhavale: Codito Technologies 2004
	30	*/
	31
	32	#ifndef __ASM_ARC_ENTRY_COMPACT_H
	33	#define __ASM_ARC_ENTRY_COMPACT_H
	34
	35	#include <asm/asm-offsets.h>
	36	#include <asm/thread_info.h> /* For THREAD_SIZE */
	37
	38	/*--------------------------------------------------------------
	39	* Switch to Kernel Mode stack if SP points to User Mode stack
	40	*
	41	* Entry : r9 contains pre-IRQ/exception/trap status32
	42	* Exit : SP is set to kernel mode stack pointer
	43	* If CURR_IN_REG, r25 set to "current" task pointer
	44	* Clobbers: r9
	45	-------------------------------------------------------------/
	46
	47	.macro SWITCH_TO_KERNEL_STK
	48
	49	/* User Mode when this happened ? Yes: Proceed to switch stack */
	50	bbit1 r9, STATUS_U_BIT, 88f
	51
	52	/* OK we were already in kernel mode when this event happened, thus can
	53	* assume SP is kernel mode SP. _NO_ need to do any stack switching
	54	*/
	55
	56	#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
	57	/* However....
	58	* If Level 2 Interrupts enabled, we may end up with a corner case:
	59	* 1. User Task executing
	60	* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
	61	* 3. But before it could switch SP from USER to KERNEL stack
	62	* a L2 IRQ "Interrupts" L1
	63	* Thay way although L2 IRQ happened in Kernel mode, stack is still
	64	* not switched.
65	* To handle this, we may need to switch stack even if in kernel mode
66	* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
67	*/
68	brlo sp, VMALLOC_START, 88f
69
70	/* TODO: vineetg:
71	* We need to be a bit more cautious here. What if a kernel bug in
72	* L1 ISR, caused SP to go whaco (some small value which looks like
73	* USER stk) and then we take L2 ISR.
74	* Above brlo alone would treat it as a valid L1-L2 sceanrio
75	* instead of shouting alound
76	* The only feasible way is to make sure this L2 happened in
77	* L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
78	* L1 ISR before it switches stack
79	*/
80
81	#endif
82
83	/* Save Pre Intr/Exception KERNEL MODE SP on kernel stack
84	* safe-keeping not really needed, but it keeps the epilogue code
85	* (SP restore) simpler/uniform.
86	*/
87	b.d 66f
88	mov r9, sp
89
90	88: /------Intr/Ecxp happened in user mode, "switch" stack ------ /
91
92	GET_CURR_TASK_ON_CPU r9
93
94	/* With current tsk in r9, get it's kernel mode stack base */
95	GET_TSK_STACK_BASE r9, r9
96
97	66:
98	#ifdef CONFIG_ARC_CURR_IN_REG
99	/*
100	* Treat r25 as scratch reg, save it on stack first
101	* Load it with current task pointer
102	*/
103	st r25, [r9, -4]
104	GET_CURR_TASK_ON_CPU r25
105	#endif
106
107	/* Save Pre Intr/Exception User SP on kernel stack */
108	st.a sp, [r9, -16] ; Make room for orig_r0, ECR, user_r25
109
110	/* CAUTION:
111	* SP should be set at the very end when we are done with everything
112	* In case of 2 levels of interrupt we depend on value of SP to assume
113	* that everything else is done (loading r25 etc)
114	*/
115
116	/* set SP to point to kernel mode stack */
117	mov sp, r9
118
119	/* ----- Stack Switched to kernel Mode, Now save REG FILE ----- */
120
121	.endm
122
123	/*------------------------------------------------------------
124	* "FAKE" a rtie to return from CPU Exception context
125	* This is to re-enable Exceptions within exception
126	* Look at EV_ProtV to see how this is actually used
127	-------------------------------------------------------------/
128
129	.macro FAKE_RET_FROM_EXCPN
130
131	ld r9, [sp, PT_status32]
132	bic r9, r9, (STATUS_U_MASK\|STATUS_DE_MASK)
133	bset r9, r9, STATUS_L_BIT
134	sr r9, [erstatus]
135	mov r9, 55f
136	sr r9, [eret]
137
138	rtie
139	55:
140	.endm
141
142	/*--------------------------------------------------------------
143	* For early Exception/ISR Prologue, a core reg is temporarily needed to
144	* code the rest of prolog (stack switching). This is done by stashing
145	* it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
146	*
147	* Before saving the full regfile - this reg is restored back, only
148	* to be saved again on kernel mode stack, as part of pt_regs.
149	-------------------------------------------------------------/
150	.macro PROLOG_FREEUP_REG reg, mem
151	#ifdef CONFIG_SMP
152	sr \reg, [ARC_REG_SCRATCH_DATA0]
153	#else
154	st \reg, [\mem]
155	#endif
156	.endm
157
158	.macro PROLOG_RESTORE_REG reg, mem
159	#ifdef CONFIG_SMP
160	lr \reg, [ARC_REG_SCRATCH_DATA0]
161	#else
162	ld \reg, [\mem]
163	#endif
164	.endm
165
166	/*--------------------------------------------------------------
167	* Exception Entry prologue
168	* -Switches stack to K mode (if not already)
169	* -Saves the register file
170	*
171	* After this it is safe to call the "C" handlers
172	-------------------------------------------------------------/
173	.macro EXCEPTION_PROLOGUE
174
175	/* Need at least 1 reg to code the early exception prologue */
176	PROLOG_FREEUP_REG r9, @ex_saved_reg1
177
178	/* U/K mode at time of exception (stack not switched if already K) */
179	lr r9, [erstatus]
180
181	/* ARC700 doesn't provide auto-stack switching */
182	SWITCH_TO_KERNEL_STK
183
184	lr r9, [ecr]
185	st r9, [sp, 8] /* ECR */
186	st r0, [sp, 4] /* orig_r0, needed only for sys calls */
187
188	/* Restore r9 used to code the early prologue */
189	PROLOG_RESTORE_REG r9, @ex_saved_reg1
190
191	SAVE_R0_TO_R12
192	PUSH gp
193	PUSH fp
194	PUSH blink
195	PUSHAX eret
196	PUSHAX erstatus
197	PUSH lp_count
198	PUSHAX lp_end
199	PUSHAX lp_start
200	PUSHAX erbta
201	.endm
202
203	/*--------------------------------------------------------------
204	* Restore all registers used by system call or Exceptions
205	* SP should always be pointing to the next free stack element
206	* when entering this macro.
207	*
208	* NOTE:
209	*
210	* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
211	* for memory load operations. If used in that way interrupts are deffered
212	* by hardware and that is not good.
213	-------------------------------------------------------------/
214	.macro EXCEPTION_EPILOGUE
215	POPAX erbta
216	POPAX lp_start
217	POPAX lp_end
218
219	POP r9
220	mov lp_count, r9 ;LD to lp_count is not allowed
221
222	POPAX erstatus
223	POPAX eret
224	POP blink
225	POP fp
226	POP gp
227	RESTORE_R12_TO_R0
228
229	ld sp, [sp] /* restore original sp */
230	/* orig_r0, ECR, user_r25 skipped automatically */
231	.endm
232
233	/* Dummy ECR values for Interrupts */
234	#define event_IRQ1 0x0031abcd
235	#define event_IRQ2 0x0032abcd
236
237	.macro INTERRUPT_PROLOGUE LVL
238
239	/* free up r9 as scratchpad */
240	PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg
241
242	/* Which mode (user/kernel) was the system in when intr occured */
243	lr r9, [status32_l\LVL\()]
244
245	SWITCH_TO_KERNEL_STK
246
247	/* restore original r9 */
248	PROLOG_RESTORE_REG r9, @int\LVL\()_saved_reg
249
250	/* now we are ready to save the remaining context */
251	st 0x003\LVL\()abcd, [sp, 8] /* Dummy ECR */
252	st 0, [sp, 4] /* orig_r0 , N/A for IRQ */
253
254	SAVE_R0_TO_R12
255	PUSH gp
256	PUSH fp
257	PUSH blink
258	PUSH ilink\LVL\()
259	PUSHAX status32_l\LVL\()
260	PUSH lp_count
261	PUSHAX lp_end
262	PUSHAX lp_start
263	PUSHAX bta_l\LVL\()
264	.endm
265
266	/*--------------------------------------------------------------
267	* Restore all registers used by interrupt handlers.
268	*
269	* NOTE:
270	*
271	* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
272	* for memory load operations. If used in that way interrupts are deffered
273	* by hardware and that is not good.
274	-------------------------------------------------------------/
275	.macro INTERRUPT_EPILOGUE LVL
276	POPAX bta_l\LVL\()
277	POPAX lp_start
278	POPAX lp_end
279
280	POP r9
281	mov lp_count, r9 ;LD to lp_count is not allowed
282
283	POPAX status32_l\LVL\()
284	POP ilink\LVL\()
285	POP blink
286	POP fp
287	POP gp
288	RESTORE_R12_TO_R0
289
290	ld sp, [sp] /* restore original sp */
291	/* orig_r0, ECR, user_r25 skipped automatically */
292	.endm
293
294	/* Get thread_info of "current" tsk */
295	.macro GET_CURR_THR_INFO_FROM_SP reg
296	bic \reg, sp, (THREAD_SIZE - 1)
297	.endm
298
299	/* Get CPU-ID of this core */
300	.macro GET_CPU_ID reg
301	lr \reg, [identity]
302	lsr \reg, \reg, 8
303	bmsk \reg, \reg, 7
304	.endm
305
306	#endif /* __ASM_ARC_ENTRY_COMPACT_H */