[deliverable/linux.git] / arch / arc / kernel / entry-compact.S

/*
 * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
 *
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * vineetg: May 2011
 *  -Userspace unaligned access emulation
 *
 * vineetg: Feb 2011 (ptrace low level code fixes)
 *  -traced syscall return code (r0) was not saved into pt_regs for restoring
 *   into user reg-file when traded task rets to user space.
 *  -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
 *   were not invoking post-syscall trace hook (jumping directly into
 *   ret_from_system_call)
 *
 * vineetg: Nov 2010:
 *  -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
 *  -To maintain the slot size of 8 bytes/vector, added nop, which is
 *   not executed at runtime.
 *
 * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
 *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
 *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
 *   need ptregs anymore
 *
 * Vineetg: Oct 2009
 *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
 *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
 *   active (AE bit enabled).  This causes a double fault for a subseq valid
 *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
 *   Instr Error could also cause similar scenario, so same there as well.
 *
 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
 *
 * Vineetg: Aug 28th 2008: Bug #94984
 *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
 *   Normally CPU does this automatically, however when doing FAKE rtie,
 *   we need to explicitly do this. The problem in macros
 *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
 *   was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
 *   setting it and not clearing it clears ZOL context
 *
 * Vineetg: May 16th, 2008
 *  - r25 now contains the Current Task when in kernel
 *
 * Vineetg: Dec 22, 2007
 *    Minor Surgery of Low Level ISR to make it SMP safe
 *    - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
 *    - _current_task is made an array of NR_CPUS
 *    - Access of _current_task wrapped inside a macro so that if hardware
 *       team agrees for a dedicated reg, no other code is touched
 *
 * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
 */

#include <linux/errno.h>
#include <linux/linkage.h>	/* {EXTRY,EXIT} */
#include <asm/entry.h>
#include <asm/irqflags.h>

	.cpu A7

;############################ Vector Table #################################

.macro VECTOR  lbl
#if 1   /* Just in case, build breaks */
	j   \lbl
#else
	b   \lbl
	nop
#endif
.endm

	.section .vector, "ax",@progbits
	.align 4

/* Each entry in the vector table must occupy 2 words. Since it is a jump
 * across sections (.vector to .text) we are gauranteed that 'j somewhere'
 * will use the 'j limm' form of the intrsuction as long as somewhere is in
 * a section other than .vector.
 */

; ********* Critical System Events **********************
VECTOR   res_service             ; 0x0, Reset Vector	(0x0)
VECTOR   mem_service             ; 0x8, Mem exception   (0x1)
VECTOR   instr_service           ; 0x10, Instrn Error   (0x2)

; ******************** Device ISRs **********************
#ifdef CONFIG_ARC_IRQ3_LV2
VECTOR   handle_interrupt_level2
#else
VECTOR   handle_interrupt_level1
#endif

VECTOR   handle_interrupt_level1

#ifdef CONFIG_ARC_IRQ5_LV2
VECTOR   handle_interrupt_level2
#else
VECTOR   handle_interrupt_level1
#endif

#ifdef CONFIG_ARC_IRQ6_LV2
VECTOR   handle_interrupt_level2
#else
VECTOR   handle_interrupt_level1
#endif

.rept   25
VECTOR   handle_interrupt_level1 ; Other devices
.endr

/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */

; ******************** Exceptions **********************
VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
				 ;         or Misaligned Access
VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)

.rept   24
VECTOR   reserved                ; Reserved Exceptions
.endr


;##################### Scratch Mem for IRQ stack switching #############

ARCFP_DATA int1_saved_reg
	.align 32
	.type   int1_saved_reg, @object
	.size   int1_saved_reg, 4
int1_saved_reg:
	.zero 4

/* Each Interrupt level needs its own scratch */
#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS

ARCFP_DATA int2_saved_reg
	.type   int2_saved_reg, @object
	.size   int2_saved_reg, 4
int2_saved_reg:
	.zero 4

#endif

; ---------------------------------------------
	.section .text, "ax",@progbits


reserved:
	flag 1		; Unexpected event, halt

;##################### Interrupt Handling ##############################

#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
; ---------------------------------------------
;  Level 2 ISR: Can interrupt a Level 1 ISR
; ---------------------------------------------
ENTRY(handle_interrupt_level2)

	INTERRUPT_PROLOGUE 2

	;------------------------------------------------------
	; if L2 IRQ interrupted a L1 ISR, disable preemption
	;
	; This is to avoid a potential L1-L2-L1 scenario
	;  -L1 IRQ taken
	;  -L2 interrupts L1 (before L1 ISR could run)
	;  -preemption off IRQ, user task in syscall picked to run
	;  -RTIE to userspace
	;	Returns from L2 context fine
	;	But both L1 and L2 re-enabled, so another L1 can be taken
	;	while prev L1 is still unserviced
	;
	;------------------------------------------------------

	; L2 interrupting L1 implies both L2 and L1 active
	; However both A2 and A1 are NOT set in STATUS32, thus
	; need to check STATUS32_L2 to determine if L1 was active

	ld r9, [sp, PT_status32]        ; get statu32_l2 (saved in pt_regs)
	bbit0 r9, STATUS_A1_BIT, 1f     ; L1 not active when L2 IRQ, so normal

	; bump thread_info->preempt_count (Disable preemption)
	GET_CURR_THR_INFO_FROM_SP   r10
	ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
	add     r9, r9, 1
	st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]

1:
	;------------------------------------------------------
	; setup params for Linux common ISR and invoke it
	;------------------------------------------------------
	lr  r0, [icause2]
	and r0, r0, 0x1f

	bl.d  @arch_do_IRQ
	mov r1, sp

	mov r8,0x2
	sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg

	b   ret_from_exception

END(handle_interrupt_level2)

#endif

; ---------------------------------------------
;  Level 1 ISR
; ---------------------------------------------
ENTRY(handle_interrupt_level1)

	INTERRUPT_PROLOGUE 1

	lr  r0, [icause1]
	and r0, r0, 0x1f

#ifdef CONFIG_TRACE_IRQFLAGS
	; icause1 needs to be read early, before calling tracing, which
	; can clobber scratch regs, hence use of stack to stash it
	push r0
	TRACE_ASM_IRQ_DISABLE
	pop  r0
#endif

	bl.d  @arch_do_IRQ
	mov r1, sp

	mov r8,0x1
	sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg

	b   ret_from_exception
END(handle_interrupt_level1)

;################### Non TLB Exception Handling #############################

; ---------------------------------------------
; Protection Violation Exception Handler
; ---------------------------------------------

ENTRY(EV_TLBProtV)

	EXCEPTION_PROLOGUE

	lr  r2, [ecr]
	lr  r0, [efa]	; Faulting Data address (not part of pt_regs saved above)

	; Exception auto-disables further Intr/exceptions.
	; Re-enable them by pretending to return from exception
	; (so rest of handler executes in pure K mode)

	FAKE_RET_FROM_EXCPN

	mov   r1, sp	; Handle to pt_regs

	;------ (5) Type of Protection Violation? ----------
	;
	; ProtV Hardware Exception is triggered for Access Faults of 2 types
	;   -Access Violaton	: 00_23_(00|01|02|03)_00
	;			         x  r  w  r+w
	;   -Unaligned Access	: 00_23_04_00
	;
	bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f

	;========= (6a) Access Violation Processing ========
	bl  do_page_fault
	b   ret_from_exception

	;========== (6b) Non aligned access ============
4:

	SAVE_CALLEE_SAVED_USER
	mov r2, sp              ; callee_regs

	bl  do_misaligned_access

	; TBD: optimize - do this only if a callee reg was involved
	; either a dst of emulated LD/ST or src with address-writeback
	RESTORE_CALLEE_SAVED_USER

	b   ret_from_exception

END(EV_TLBProtV)

; Wrapper for Linux page fault handler called from EV_TLBMiss*
; Very similar to ProtV handler case (6a) above, but avoids the extra checks
; for Misaligned access
;
ENTRY(call_do_page_fault)

	EXCEPTION_PROLOGUE
	lr  r0, [efa]	; Faulting Data address
	mov   r1, sp
	FAKE_RET_FROM_EXCPN

	mov blink, ret_from_exception
	b  do_page_fault

END(call_do_page_fault)

;############# Common Handlers for ARCompact and ARCv2 ##############

#include "entry.S"

;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
;
; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
; IRQ shd definitely not happen between now and rtie
; All 2 entry points to here already disable interrupts

.Lrestore_regs:

	TRACE_ASM_IRQ_ENABLE

	lr	r10, [status32]

	; Restore REG File. In case multiple Events outstanding,
	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
	; Note that we use realtime STATUS32 (not pt_regs->status32) to
	; decide that.

	and.f	0, r10, (STATUS_A1_MASK|STATUS_A2_MASK)
	bz	.Lexcep_or_pure_K_ret

	; Returning from Interrupts (Level 1 or 2)

#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS

	; Level 2 interrupt return Path - from hardware standpoint
	bbit0  r10, STATUS_A2_BIT, not_level2_interrupt

	;------------------------------------------------------------------
	; However the context returning might not have taken L2 intr itself
	; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
	; Special considerations needed for the context which took L2 intr

	ld   r9, [sp, PT_event]        ; Ensure this is L2 intr context
	brne r9, event_IRQ2, 149f

	;------------------------------------------------------------------
	; if L2 IRQ interrupted an L1 ISR,  we'd disabled preemption earlier
	; so that sched doesn't move to new task, causing L1 to be delayed
	; undeterministically. Now that we've achieved that, let's reset
	; things to what they were, before returning from L2 context
	;----------------------------------------------------------------

	ld r9, [sp, PT_status32]       ; get statu32_l2 (saved in pt_regs)
	bbit0 r9, STATUS_A1_BIT, 149f  ; L1 not active when L2 IRQ, so normal

	; decrement thread_info->preempt_count (re-enable preemption)
	GET_CURR_THR_INFO_FROM_SP   r10
	ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]

	; paranoid check, given A1 was active when A2 happened, preempt count
	; must not be 0 because we would have incremented it.
	; If this does happen we simply HALT as it means a BUG !!!
	cmp     r9, 0
	bnz     2f
	flag 1

2:
	sub     r9, r9, 1
	st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]

149:
	INTERRUPT_EPILOGUE 2	; return from level 2 interrupt
debug_marker_l2:
	rtie

not_level2_interrupt:

#endif

	INTERRUPT_EPILOGUE 1	; return from level 1 interrupt
debug_marker_l1:
	rtie

.Lexcep_or_pure_K_ret:

	;this case is for syscalls or Exceptions or pure kernel mode

	EXCEPTION_EPILOGUE
debug_marker_syscall:
	rtie

END(ret_from_exception)
Commit	Line	Data
6d1a20b1 VG	1	/*
	2	* Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
	3	*
	4	* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
	5	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* vineetg: May 2011
	12	* -Userspace unaligned access emulation
	13	*
	14	* vineetg: Feb 2011 (ptrace low level code fixes)
	15	* -traced syscall return code (r0) was not saved into pt_regs for restoring
	16	* into user reg-file when traded task rets to user space.
	17	* -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
	18	* were not invoking post-syscall trace hook (jumping directly into
	19	* ret_from_system_call)
	20	*
	21	* vineetg: Nov 2010:
	22	* -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
	23	* -To maintain the slot size of 8 bytes/vector, added nop, which is
	24	* not executed at runtime.
	25	*
	26	* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
	27	* -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
	28	* -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
	29	* need ptregs anymore
	30	*
	31	* Vineetg: Oct 2009
	32	* -In a rare scenario, Process gets a Priv-V exception and gets scheduled
	33	* out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
	34	* active (AE bit enabled). This causes a double fault for a subseq valid
	35	* exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
	36	* Instr Error could also cause similar scenario, so same there as well.
	37	*
	38	* Vineetg: March 2009 (Supporting 2 levels of Interrupts)
	39	*
	40	* Vineetg: Aug 28th 2008: Bug #94984
	41	* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
	42	* Normally CPU does this automatically, however when doing FAKE rtie,
	43	* we need to explicitly do this. The problem in macros
	44	* FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
	45	* was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
	46	* setting it and not clearing it clears ZOL context
	47	*
	48	* Vineetg: May 16th, 2008
	49	* - r25 now contains the Current Task when in kernel
	50	*
	51	* Vineetg: Dec 22, 2007
	52	* Minor Surgery of Low Level ISR to make it SMP safe
	53	* - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
	54	* - _current_task is made an array of NR_CPUS
	55	* - Access of _current_task wrapped inside a macro so that if hardware
	56	* team agrees for a dedicated reg, no other code is touched
	57	*
	58	* Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
	59	*/
	60
	61	#include <linux/errno.h>
	62	#include <linux/linkage.h> /* {EXTRY,EXIT} */
	63	#include <asm/entry.h>
	64	#include <asm/irqflags.h>
65
66	.cpu A7
67
68	;############################ Vector Table #################################
69
70	.macro VECTOR lbl
71	#if 1 /* Just in case, build breaks */
72	j \lbl
73	#else
74	b \lbl
75	nop
76	#endif
77	.endm
78
79	.section .vector, "ax",@progbits
80	.align 4
81
82	/* Each entry in the vector table must occupy 2 words. Since it is a jump
83	* across sections (.vector to .text) we are gauranteed that 'j somewhere'
84	* will use the 'j limm' form of the intrsuction as long as somewhere is in
85	* a section other than .vector.
86	*/
87
88	; ******* Critical System Events ********************
3971cdc2	89	VECTOR res_service ; 0x0, Reset Vector (0x0)
6d1a20b1 VG	90	VECTOR mem_service ; 0x8, Mem exception (0x1)
	91	VECTOR instr_service ; 0x10, Instrn Error (0x2)
	92
	93	; ****************** Device ISRs ********************
	94	#ifdef CONFIG_ARC_IRQ3_LV2
	95	VECTOR handle_interrupt_level2
	96	#else
	97	VECTOR handle_interrupt_level1
	98	#endif
	99
	100	VECTOR handle_interrupt_level1
	101
	102	#ifdef CONFIG_ARC_IRQ5_LV2
	103	VECTOR handle_interrupt_level2
	104	#else
	105	VECTOR handle_interrupt_level1
	106	#endif
	107
	108	#ifdef CONFIG_ARC_IRQ6_LV2
	109	VECTOR handle_interrupt_level2
	110	#else
	111	VECTOR handle_interrupt_level1
	112	#endif
	113
	114	.rept 25
	115	VECTOR handle_interrupt_level1 ; Other devices
	116	.endr
	117
	118	/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
	119
	120	; ****************** Exceptions ********************
	121	VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20)
	122	VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
	123	VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
	124	VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23)
	125	; or Misaligned Access
	126	VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24)
	127	VECTOR EV_Trap ; 0x128, Trap exception (0x25)
	128	VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26)
	129
	130	.rept 24
	131	VECTOR reserved ; Reserved Exceptions
	132	.endr
	133
	134
	135	;##################### Scratch Mem for IRQ stack switching #############
	136
	137	ARCFP_DATA int1_saved_reg
	138	.align 32
	139	.type int1_saved_reg, @object
	140	.size int1_saved_reg, 4
	141	int1_saved_reg:
	142	.zero 4
	143
	144	/* Each Interrupt level needs its own scratch */
	145	#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
	146
	147	ARCFP_DATA int2_saved_reg
	148	.type int2_saved_reg, @object
	149	.size int2_saved_reg, 4
	150	int2_saved_reg:
	151	.zero 4
	152
	153	#endif
154
155	; ---------------------------------------------
156	.section .text, "ax",@progbits
157
6d1a20b1	158
3971cdc2 VG	159	reserved:
3971cdc2 VG	160	flag 1 ; Unexpected event, halt
6d1a20b1 VG	161
	162	;##################### Interrupt Handling ##############################
	163
	164	#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
	165	; ---------------------------------------------
	166	; Level 2 ISR: Can interrupt a Level 1 ISR
	167	; ---------------------------------------------
	168	ENTRY(handle_interrupt_level2)
	169
	170	INTERRUPT_PROLOGUE 2
	171
	172	;------------------------------------------------------
	173	; if L2 IRQ interrupted a L1 ISR, disable preemption
5f888087 VG	174	;
	175	; This is to avoid a potential L1-L2-L1 scenario
	176	; -L1 IRQ taken
	177	; -L2 interrupts L1 (before L1 ISR could run)
	178	; -preemption off IRQ, user task in syscall picked to run
	179	; -RTIE to userspace
	180	; Returns from L2 context fine
	181	; But both L1 and L2 re-enabled, so another L1 can be taken
	182	; while prev L1 is still unserviced
	183	;
6d1a20b1 VG	184	;------------------------------------------------------
6d1a20b1 VG	185
5f888087 VG	186	; L2 interrupting L1 implies both L2 and L1 active
	187	; However both A2 and A1 are NOT set in STATUS32, thus
	188	; need to check STATUS32_L2 to determine if L1 was active
	189
6d1a20b1 VG	190	ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
	191	bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
	192
6d1a20b1 VG	193	; bump thread_info->preempt_count (Disable preemption)
	194	GET_CURR_THR_INFO_FROM_SP r10
	195	ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
	196	add r9, r9, 1
	197	st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
	198
	199	1:
	200	;------------------------------------------------------
	201	; setup params for Linux common ISR and invoke it
	202	;------------------------------------------------------
	203	lr r0, [icause2]
	204	and r0, r0, 0x1f
	205
	206	bl.d @arch_do_IRQ
	207	mov r1, sp
	208
	209	mov r8,0x2
	210	sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
	211
	212	b ret_from_exception
	213
	214	END(handle_interrupt_level2)
	215
	216	#endif
	217
	218	; ---------------------------------------------
	219	; Level 1 ISR
	220	; ---------------------------------------------
	221	ENTRY(handle_interrupt_level1)
	222
	223	INTERRUPT_PROLOGUE 1
	224
	225	lr r0, [icause1]
	226	and r0, r0, 0x1f
	227
	228	#ifdef CONFIG_TRACE_IRQFLAGS
	229	; icause1 needs to be read early, before calling tracing, which
	230	; can clobber scratch regs, hence use of stack to stash it
	231	push r0
	232	TRACE_ASM_IRQ_DISABLE
	233	pop r0
	234	#endif
	235
	236	bl.d @arch_do_IRQ
	237	mov r1, sp
	238
	239	mov r8,0x1
	240	sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
	241
	242	b ret_from_exception
	243	END(handle_interrupt_level1)
	244
	245	;################### Non TLB Exception Handling #############################
	246
	247	; ---------------------------------------------
	248	; Protection Violation Exception Handler
	249	; ---------------------------------------------
	250
	251	ENTRY(EV_TLBProtV)
	252
	253	EXCEPTION_PROLOGUE
	254
	255	lr r2, [ecr]
	256	lr r0, [efa] ; Faulting Data address (not part of pt_regs saved above)
257
258	; Exception auto-disables further Intr/exceptions.
259	; Re-enable them by pretending to return from exception
260	; (so rest of handler executes in pure K mode)
261
262	FAKE_RET_FROM_EXCPN
263
264	mov r1, sp ; Handle to pt_regs
265
266	;------ (5) Type of Protection Violation? ----------
267	;
268	; ProtV Hardware Exception is triggered for Access Faults of 2 types
269	; -Access Violaton : 00_23_(00\|01\|02\|03)_00
270	; x r w r+w
271	; -Unaligned Access : 00_23_04_00
272	;
273	bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
274
275	;========= (6a) Access Violation Processing ========
276	bl do_page_fault
277	b ret_from_exception
278
279	;========== (6b) Non aligned access ============
280	4:
281
282	SAVE_CALLEE_SAVED_USER
283	mov r2, sp ; callee_regs
284
285	bl do_misaligned_access
286
287	; TBD: optimize - do this only if a callee reg was involved
288	; either a dst of emulated LD/ST or src with address-writeback
289	RESTORE_CALLEE_SAVED_USER
290
291	b ret_from_exception
292
293	END(EV_TLBProtV)
294
295	; Wrapper for Linux page fault handler called from EV_TLBMiss*
296	; Very similar to ProtV handler case (6a) above, but avoids the extra checks
297	; for Misaligned access
298	;
299	ENTRY(call_do_page_fault)
300
301	EXCEPTION_PROLOGUE
302	lr r0, [efa] ; Faulting Data address
303	mov r1, sp
304	FAKE_RET_FROM_EXCPN
305
306	mov blink, ret_from_exception
307	b do_page_fault
308
309	END(call_do_page_fault)
310
311	;############# Common Handlers for ARCompact and ARCv2 ##############
312
313	#include "entry.S"
314
315	;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
316	;
317	; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
318	; IRQ shd definitely not happen between now and rtie
319	; All 2 entry points to here already disable interrupts
320
321	.Lrestore_regs:
322
323	TRACE_ASM_IRQ_ENABLE
324
325	lr r10, [status32]
326
327	; Restore REG File. In case multiple Events outstanding,
328	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
329	; Note that we use realtime STATUS32 (not pt_regs->status32) to
330	; decide that.
331
9fabcc63 VG	332	and.f 0, r10, (STATUS_A1_MASK\|STATUS_A2_MASK)
9fabcc63 VG	333	bz .Lexcep_or_pure_K_ret
6d1a20b1	334
9fabcc63	335	; Returning from Interrupts (Level 1 or 2)
6d1a20b1	336
6d1a20b1 VG	337	#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
	338
	339	; Level 2 interrupt return Path - from hardware standpoint
	340	bbit0 r10, STATUS_A2_BIT, not_level2_interrupt
	341
	342	;------------------------------------------------------------------
	343	; However the context returning might not have taken L2 intr itself
	344	; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
	345	; Special considerations needed for the context which took L2 intr
	346
	347	ld r9, [sp, PT_event] ; Ensure this is L2 intr context
	348	brne r9, event_IRQ2, 149f
	349
	350	;------------------------------------------------------------------
	351	; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
	352	; so that sched doesn't move to new task, causing L1 to be delayed
	353	; undeterministically. Now that we've achieved that, let's reset
	354	; things to what they were, before returning from L2 context
	355	;----------------------------------------------------------------
	356
	357	ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
	358	bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
	359
	360	; decrement thread_info->preempt_count (re-enable preemption)
	361	GET_CURR_THR_INFO_FROM_SP r10
	362	ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
	363
	364	; paranoid check, given A1 was active when A2 happened, preempt count
	365	; must not be 0 because we would have incremented it.
	366	; If this does happen we simply HALT as it means a BUG !!!
	367	cmp r9, 0
	368	bnz 2f
	369	flag 1
	370
	371	2:
	372	sub r9, r9, 1
	373	st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
	374
	375	149:
9fabcc63	376	INTERRUPT_EPILOGUE 2 ; return from level 2 interrupt
6d1a20b1 VG	377	debug_marker_l2:
	378	rtie
	379
	380	not_level2_interrupt:
	381
	382	#endif
	383
9fabcc63	384	INTERRUPT_EPILOGUE 1 ; return from level 1 interrupt
6d1a20b1 VG	385	debug_marker_l1:
	386	rtie
	387
9fabcc63	388	.Lexcep_or_pure_K_ret:
6d1a20b1	389
c80417b6	390	;this case is for syscalls or Exceptions or pure kernel mode
6d1a20b1 VG	391
	392	EXCEPTION_EPILOGUE
	393	debug_marker_syscall:
	394	rtie
c7e6d792 VG	395
c7e6d792 VG	396	END(ret_from_exception)