[deliverable/linux.git] / arch / arc / kernel / entry-compact.S

/*
 * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
 *
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * vineetg: May 2011
 *  -Userspace unaligned access emulation
 *
 * vineetg: Feb 2011 (ptrace low level code fixes)
 *  -traced syscall return code (r0) was not saved into pt_regs for restoring
 *   into user reg-file when traded task rets to user space.
 *  -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
 *   were not invoking post-syscall trace hook (jumping directly into
 *   ret_from_system_call)
 *
 * vineetg: Nov 2010:
 *  -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
 *  -To maintain the slot size of 8 bytes/vector, added nop, which is
 *   not executed at runtime.
 *
 * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
 *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
 *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
 *   need ptregs anymore
 *
 * Vineetg: Oct 2009
 *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
 *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
 *   active (AE bit enabled).  This causes a double fault for a subseq valid
 *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
 *   Instr Error could also cause similar scenario, so same there as well.
 *
 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
 *
 * Vineetg: Aug 28th 2008: Bug #94984
 *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
 *   Normally CPU does this automatically, however when doing FAKE rtie,
 *   we need to explicitly do this. The problem in macros
 *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
 *   was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
 *   setting it and not clearing it clears ZOL context
 *
 * Vineetg: May 16th, 2008
 *  - r25 now contains the Current Task when in kernel
 *
 * Vineetg: Dec 22, 2007
 *    Minor Surgery of Low Level ISR to make it SMP safe
 *    - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
 *    - _current_task is made an array of NR_CPUS
 *    - Access of _current_task wrapped inside a macro so that if hardware
 *       team agrees for a dedicated reg, no other code is touched
 *
 * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
 */

#include <linux/errno.h>
#include <linux/linkage.h>	/* {EXTRY,EXIT} */
#include <asm/entry.h>
#include <asm/irqflags.h>

	.cpu A7

;############################ Vector Table #################################

.macro VECTOR  lbl
#if 1   /* Just in case, build breaks */
	j   \lbl
#else
	b   \lbl
	nop
#endif
.endm

	.section .vector, "ax",@progbits
	.align 4

/* Each entry in the vector table must occupy 2 words. Since it is a jump
 * across sections (.vector to .text) we are gauranteed that 'j somewhere'
 * will use the 'j limm' form of the intrsuction as long as somewhere is in
 * a section other than .vector.
 */

; ********* Critical System Events **********************
VECTOR   res_service             ; 0x0, Restart Vector  (0x0)
VECTOR   mem_service             ; 0x8, Mem exception   (0x1)
VECTOR   instr_service           ; 0x10, Instrn Error   (0x2)

; ******************** Device ISRs **********************
#ifdef CONFIG_ARC_IRQ3_LV2
VECTOR   handle_interrupt_level2
#else
VECTOR   handle_interrupt_level1
#endif

VECTOR   handle_interrupt_level1

#ifdef CONFIG_ARC_IRQ5_LV2
VECTOR   handle_interrupt_level2
#else
VECTOR   handle_interrupt_level1
#endif

#ifdef CONFIG_ARC_IRQ6_LV2
VECTOR   handle_interrupt_level2
#else
VECTOR   handle_interrupt_level1
#endif

.rept   25
VECTOR   handle_interrupt_level1 ; Other devices
.endr

/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */

; ******************** Exceptions **********************
VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
				 ;         or Misaligned Access
VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)

.rept   24
VECTOR   reserved                ; Reserved Exceptions
.endr


;##################### Scratch Mem for IRQ stack switching #############

ARCFP_DATA int1_saved_reg
	.align 32
	.type   int1_saved_reg, @object
	.size   int1_saved_reg, 4
int1_saved_reg:
	.zero 4

/* Each Interrupt level needs its own scratch */
#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS

ARCFP_DATA int2_saved_reg
	.type   int2_saved_reg, @object
	.size   int2_saved_reg, 4
int2_saved_reg:
	.zero 4

#endif

; ---------------------------------------------
	.section .text, "ax",@progbits

res_service:		; processor restart
	flag    0x1     ; not implemented
	nop
	nop

reserved:		; processor restart
	rtie            ; jump to processor initializations

;##################### Interrupt Handling ##############################

#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
; ---------------------------------------------
;  Level 2 ISR: Can interrupt a Level 1 ISR
; ---------------------------------------------
ENTRY(handle_interrupt_level2)

	INTERRUPT_PROLOGUE 2

	;------------------------------------------------------
	; if L2 IRQ interrupted a L1 ISR, disable preemption
	;------------------------------------------------------

	ld r9, [sp, PT_status32]        ; get statu32_l2 (saved in pt_regs)
	bbit0 r9, STATUS_A1_BIT, 1f     ; L1 not active when L2 IRQ, so normal

	; A1 is set in status32_l2
	; bump thread_info->preempt_count (Disable preemption)
	GET_CURR_THR_INFO_FROM_SP   r10
	ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
	add     r9, r9, 1
	st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]

1:
	;------------------------------------------------------
	; setup params for Linux common ISR and invoke it
	;------------------------------------------------------
	lr  r0, [icause2]
	and r0, r0, 0x1f

	bl.d  @arch_do_IRQ
	mov r1, sp

	mov r8,0x2
	sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg

	b   ret_from_exception

END(handle_interrupt_level2)

#endif

; ---------------------------------------------
;  Level 1 ISR
; ---------------------------------------------
ENTRY(handle_interrupt_level1)

	INTERRUPT_PROLOGUE 1

	lr  r0, [icause1]
	and r0, r0, 0x1f

#ifdef CONFIG_TRACE_IRQFLAGS
	; icause1 needs to be read early, before calling tracing, which
	; can clobber scratch regs, hence use of stack to stash it
	push r0
	TRACE_ASM_IRQ_DISABLE
	pop  r0
#endif

	bl.d  @arch_do_IRQ
	mov r1, sp

	mov r8,0x1
	sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg

	b   ret_from_exception
END(handle_interrupt_level1)

;################### Non TLB Exception Handling #############################

; ---------------------------------------------
; Protection Violation Exception Handler
; ---------------------------------------------

ENTRY(EV_TLBProtV)

	EXCEPTION_PROLOGUE

	lr  r2, [ecr]
	lr  r0, [efa]	; Faulting Data address (not part of pt_regs saved above)

	; Exception auto-disables further Intr/exceptions.
	; Re-enable them by pretending to return from exception
	; (so rest of handler executes in pure K mode)

	FAKE_RET_FROM_EXCPN

	mov   r1, sp	; Handle to pt_regs

	;------ (5) Type of Protection Violation? ----------
	;
	; ProtV Hardware Exception is triggered for Access Faults of 2 types
	;   -Access Violaton	: 00_23_(00|01|02|03)_00
	;			         x  r  w  r+w
	;   -Unaligned Access	: 00_23_04_00
	;
	bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f

	;========= (6a) Access Violation Processing ========
	bl  do_page_fault
	b   ret_from_exception

	;========== (6b) Non aligned access ============
4:

	SAVE_CALLEE_SAVED_USER
	mov r2, sp              ; callee_regs

	bl  do_misaligned_access

	; TBD: optimize - do this only if a callee reg was involved
	; either a dst of emulated LD/ST or src with address-writeback
	RESTORE_CALLEE_SAVED_USER

	b   ret_from_exception

END(EV_TLBProtV)

; Wrapper for Linux page fault handler called from EV_TLBMiss*
; Very similar to ProtV handler case (6a) above, but avoids the extra checks
; for Misaligned access
;
ENTRY(call_do_page_fault)

	EXCEPTION_PROLOGUE
	lr  r0, [efa]	; Faulting Data address
	mov   r1, sp
	FAKE_RET_FROM_EXCPN

	mov blink, ret_from_exception
	b  do_page_fault

END(call_do_page_fault)

;############# Common Handlers for ARCompact and ARCv2 ##############

#include "entry.S"

;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
;
; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
; IRQ shd definitely not happen between now and rtie
; All 2 entry points to here already disable interrupts

.Lrestore_regs:

	TRACE_ASM_IRQ_ENABLE

	lr	r10, [status32]

	; Restore REG File. In case multiple Events outstanding,
	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
	; Note that we use realtime STATUS32 (not pt_regs->status32) to
	; decide that.

	; if Returning from Exception
	bbit0  r10, STATUS_AE_BIT, not_exception
	EXCEPTION_EPILOGUE
	rtie

	; Not Exception so maybe Interrupts (Level 1 or 2)

not_exception:

#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS

	; Level 2 interrupt return Path - from hardware standpoint
	bbit0  r10, STATUS_A2_BIT, not_level2_interrupt

	;------------------------------------------------------------------
	; However the context returning might not have taken L2 intr itself
	; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
	; Special considerations needed for the context which took L2 intr

	ld   r9, [sp, PT_event]        ; Ensure this is L2 intr context
	brne r9, event_IRQ2, 149f

	;------------------------------------------------------------------
	; if L2 IRQ interrupted an L1 ISR,  we'd disabled preemption earlier
	; so that sched doesn't move to new task, causing L1 to be delayed
	; undeterministically. Now that we've achieved that, let's reset
	; things to what they were, before returning from L2 context
	;----------------------------------------------------------------

	ld r9, [sp, PT_status32]       ; get statu32_l2 (saved in pt_regs)
	bbit0 r9, STATUS_A1_BIT, 149f  ; L1 not active when L2 IRQ, so normal

	; decrement thread_info->preempt_count (re-enable preemption)
	GET_CURR_THR_INFO_FROM_SP   r10
	ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]

	; paranoid check, given A1 was active when A2 happened, preempt count
	; must not be 0 because we would have incremented it.
	; If this does happen we simply HALT as it means a BUG !!!
	cmp     r9, 0
	bnz     2f
	flag 1

2:
	sub     r9, r9, 1
	st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]

149:
	;return from level 2
	INTERRUPT_EPILOGUE 2
debug_marker_l2:
	rtie

not_level2_interrupt:

#endif

	bbit0  r10, STATUS_A1_BIT, not_level1_interrupt

	;return from level 1
	INTERRUPT_EPILOGUE 1
debug_marker_l1:
	rtie

not_level1_interrupt:

	;this case is for syscalls or Exceptions (with fake rtie)

	EXCEPTION_EPILOGUE
debug_marker_syscall:
	rtie
Commit	Line	Data
6d1a20b1 VG	1	/*
	2	* Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
	3	*
	4	* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
	5	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* vineetg: May 2011
	12	* -Userspace unaligned access emulation
	13	*
	14	* vineetg: Feb 2011 (ptrace low level code fixes)
	15	* -traced syscall return code (r0) was not saved into pt_regs for restoring
	16	* into user reg-file when traded task rets to user space.
	17	* -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
	18	* were not invoking post-syscall trace hook (jumping directly into
	19	* ret_from_system_call)
	20	*
	21	* vineetg: Nov 2010:
	22	* -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
	23	* -To maintain the slot size of 8 bytes/vector, added nop, which is
	24	* not executed at runtime.
	25	*
	26	* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
	27	* -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
	28	* -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
	29	* need ptregs anymore
	30	*
	31	* Vineetg: Oct 2009
	32	* -In a rare scenario, Process gets a Priv-V exception and gets scheduled
	33	* out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
	34	* active (AE bit enabled). This causes a double fault for a subseq valid
	35	* exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
	36	* Instr Error could also cause similar scenario, so same there as well.
	37	*
	38	* Vineetg: March 2009 (Supporting 2 levels of Interrupts)
	39	*
	40	* Vineetg: Aug 28th 2008: Bug #94984
	41	* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
	42	* Normally CPU does this automatically, however when doing FAKE rtie,
	43	* we need to explicitly do this. The problem in macros
	44	* FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
	45	* was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
	46	* setting it and not clearing it clears ZOL context
	47	*
	48	* Vineetg: May 16th, 2008
	49	* - r25 now contains the Current Task when in kernel
	50	*
	51	* Vineetg: Dec 22, 2007
	52	* Minor Surgery of Low Level ISR to make it SMP safe
	53	* - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
	54	* - _current_task is made an array of NR_CPUS
	55	* - Access of _current_task wrapped inside a macro so that if hardware
	56	* team agrees for a dedicated reg, no other code is touched
	57	*
	58	* Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
	59	*/
	60
	61	#include <linux/errno.h>
	62	#include <linux/linkage.h> /* {EXTRY,EXIT} */
	63	#include <asm/entry.h>
	64	#include <asm/irqflags.h>
65
66	.cpu A7
67
68	;############################ Vector Table #################################
69
70	.macro VECTOR lbl
71	#if 1 /* Just in case, build breaks */
72	j \lbl
73	#else
74	b \lbl
75	nop
76	#endif
77	.endm
78
79	.section .vector, "ax",@progbits
80	.align 4
81
82	/* Each entry in the vector table must occupy 2 words. Since it is a jump
83	* across sections (.vector to .text) we are gauranteed that 'j somewhere'
84	* will use the 'j limm' form of the intrsuction as long as somewhere is in
85	* a section other than .vector.
86	*/
87
88	; ******* Critical System Events ********************
89	VECTOR res_service ; 0x0, Restart Vector (0x0)
90	VECTOR mem_service ; 0x8, Mem exception (0x1)
91	VECTOR instr_service ; 0x10, Instrn Error (0x2)
92
93	; ****************** Device ISRs ********************
94	#ifdef CONFIG_ARC_IRQ3_LV2
95	VECTOR handle_interrupt_level2
96	#else
97	VECTOR handle_interrupt_level1
98	#endif
99
100	VECTOR handle_interrupt_level1
101
102	#ifdef CONFIG_ARC_IRQ5_LV2
103	VECTOR handle_interrupt_level2
104	#else
105	VECTOR handle_interrupt_level1
106	#endif
107
108	#ifdef CONFIG_ARC_IRQ6_LV2
109	VECTOR handle_interrupt_level2
110	#else
111	VECTOR handle_interrupt_level1
112	#endif
113
114	.rept 25
115	VECTOR handle_interrupt_level1 ; Other devices
116	.endr
117
118	/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
119
120	; ****************** Exceptions ********************
121	VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20)
122	VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
123	VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
124	VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23)
125	; or Misaligned Access
126	VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24)
127	VECTOR EV_Trap ; 0x128, Trap exception (0x25)
128	VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26)
129
130	.rept 24
131	VECTOR reserved ; Reserved Exceptions
132	.endr
133
134
135	;##################### Scratch Mem for IRQ stack switching #############
136
137	ARCFP_DATA int1_saved_reg
138	.align 32
139	.type int1_saved_reg, @object
140	.size int1_saved_reg, 4
141	int1_saved_reg:
142	.zero 4
143
144	/* Each Interrupt level needs its own scratch */
145	#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
146
147	ARCFP_DATA int2_saved_reg
148	.type int2_saved_reg, @object
149	.size int2_saved_reg, 4
150	int2_saved_reg:
151	.zero 4
152
153	#endif
154
155	; ---------------------------------------------
156	.section .text, "ax",@progbits
157
158	res_service: ; processor restart
159	flag 0x1 ; not implemented
160	nop
161	nop
162
163	reserved: ; processor restart
164	rtie ; jump to processor initializations
165
166	;##################### Interrupt Handling ##############################
167
168	#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
169	; ---------------------------------------------
170	; Level 2 ISR: Can interrupt a Level 1 ISR
171	; ---------------------------------------------
172	ENTRY(handle_interrupt_level2)
173
174	INTERRUPT_PROLOGUE 2
175
176	;------------------------------------------------------
177	; if L2 IRQ interrupted a L1 ISR, disable preemption
178	;------------------------------------------------------
179
180	ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
181	bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
182
183	; A1 is set in status32_l2
184	; bump thread_info->preempt_count (Disable preemption)
185	GET_CURR_THR_INFO_FROM_SP r10
186	ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
187	add r9, r9, 1
188	st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
189
190	1:
191	;------------------------------------------------------
192	; setup params for Linux common ISR and invoke it
193	;------------------------------------------------------
194	lr r0, [icause2]
195	and r0, r0, 0x1f
196
197	bl.d @arch_do_IRQ
198	mov r1, sp
199
200	mov r8,0x2
201	sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
202
203	b ret_from_exception
204
205	END(handle_interrupt_level2)
206
207	#endif
208
209	; ---------------------------------------------
210	; Level 1 ISR
211	; ---------------------------------------------
212	ENTRY(handle_interrupt_level1)
213
214	INTERRUPT_PROLOGUE 1
215
216	lr r0, [icause1]
217	and r0, r0, 0x1f
218
219	#ifdef CONFIG_TRACE_IRQFLAGS
220	; icause1 needs to be read early, before calling tracing, which
221	; can clobber scratch regs, hence use of stack to stash it
222	push r0
223	TRACE_ASM_IRQ_DISABLE
224	pop r0
225	#endif
226
227	bl.d @arch_do_IRQ
228	mov r1, sp
229
230	mov r8,0x1
231	sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
232
233	b ret_from_exception
234	END(handle_interrupt_level1)
235
236	;################### Non TLB Exception Handling #############################
237
238	; ---------------------------------------------
239	; Protection Violation Exception Handler
240	; ---------------------------------------------
241
242	ENTRY(EV_TLBProtV)
243
244	EXCEPTION_PROLOGUE
245
246	lr r2, [ecr]
247	lr r0, [efa] ; Faulting Data address (not part of pt_regs saved above)
248
249	; Exception auto-disables further Intr/exceptions.
250	; Re-enable them by pretending to return from exception
251	; (so rest of handler executes in pure K mode)
252
253	FAKE_RET_FROM_EXCPN
254
255	mov r1, sp ; Handle to pt_regs
256
257	;------ (5) Type of Protection Violation? ----------
258	;
259	; ProtV Hardware Exception is triggered for Access Faults of 2 types
260	; -Access Violaton : 00_23_(00\|01\|02\|03)_00
261	; x r w r+w
262	; -Unaligned Access : 00_23_04_00
263	;
264	bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
265
266	;========= (6a) Access Violation Processing ========
267	bl do_page_fault
268	b ret_from_exception
269
270	;========== (6b) Non aligned access ============
271	4:
272
273	SAVE_CALLEE_SAVED_USER
274	mov r2, sp ; callee_regs
275
276	bl do_misaligned_access
277
278	; TBD: optimize - do this only if a callee reg was involved
279	; either a dst of emulated LD/ST or src with address-writeback
280	RESTORE_CALLEE_SAVED_USER
281
282	b ret_from_exception
283
284	END(EV_TLBProtV)
285
286	; Wrapper for Linux page fault handler called from EV_TLBMiss*
287	; Very similar to ProtV handler case (6a) above, but avoids the extra checks
288	; for Misaligned access
289	;
290	ENTRY(call_do_page_fault)
291
292	EXCEPTION_PROLOGUE
293	lr r0, [efa] ; Faulting Data address
294	mov r1, sp
295	FAKE_RET_FROM_EXCPN
296
297	mov blink, ret_from_exception
298	b do_page_fault
299
300	END(call_do_page_fault)
301
302	;############# Common Handlers for ARCompact and ARCv2 ##############
303
304	#include "entry.S"
305
306	;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
307	;
308	; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
309	; IRQ shd definitely not happen between now and rtie
310	; All 2 entry points to here already disable interrupts
311
312	.Lrestore_regs:
313
314	TRACE_ASM_IRQ_ENABLE
315
316	lr r10, [status32]
317
318	; Restore REG File. In case multiple Events outstanding,
319	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
320	; Note that we use realtime STATUS32 (not pt_regs->status32) to
321	; decide that.
322
323	; if Returning from Exception
324	bbit0 r10, STATUS_AE_BIT, not_exception
325	EXCEPTION_EPILOGUE
326	rtie
327
328	; Not Exception so maybe Interrupts (Level 1 or 2)
329
330	not_exception:
331
332	#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
333
334	; Level 2 interrupt return Path - from hardware standpoint
335	bbit0 r10, STATUS_A2_BIT, not_level2_interrupt
336
337	;------------------------------------------------------------------
338	; However the context returning might not have taken L2 intr itself
339	; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
340	; Special considerations needed for the context which took L2 intr
341
342	ld r9, [sp, PT_event] ; Ensure this is L2 intr context
343	brne r9, event_IRQ2, 149f
344
345	;------------------------------------------------------------------
346	; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
347	; so that sched doesn't move to new task, causing L1 to be delayed
348	; undeterministically. Now that we've achieved that, let's reset
349	; things to what they were, before returning from L2 context
350	;----------------------------------------------------------------
351
352	ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
353	bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
354
355	; decrement thread_info->preempt_count (re-enable preemption)
356	GET_CURR_THR_INFO_FROM_SP r10
357	ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
358
359	; paranoid check, given A1 was active when A2 happened, preempt count
360	; must not be 0 because we would have incremented it.
361	; If this does happen we simply HALT as it means a BUG !!!
362	cmp r9, 0
363	bnz 2f
364	flag 1
365
366	2:
367	sub r9, r9, 1
368	st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
369
370	149:
371	;return from level 2
372	INTERRUPT_EPILOGUE 2
373	debug_marker_l2:
374	rtie
375
376	not_level2_interrupt:
377
378	#endif
379
380	bbit0 r10, STATUS_A1_BIT, not_level1_interrupt
381
382	;return from level 1
383	INTERRUPT_EPILOGUE 1
384	debug_marker_l1:
385	rtie
386
387	not_level1_interrupt:
388
389	;this case is for syscalls or Exceptions (with fake rtie)
390
391	EXCEPTION_EPILOGUE
392	debug_marker_syscall:
393	rtie