Commit | Line | Data |
---|---|---|
0dd450fe MJ |
1 | /* |
2 | * Linux performance counter support for ARC700 series | |
3 | * | |
4 | * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) | |
5 | * | |
6 | * This code is inspired by the perf support of various other architectures. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | #include <linux/errno.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/perf_event.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <asm/arcregs.h> | |
19 | ||
20 | struct arc_pmu { | |
21 | struct pmu pmu; | |
22 | int counter_size; /* in bits */ | |
23 | int n_counters; | |
24 | unsigned long used_mask[BITS_TO_LONGS(ARC_PMU_MAX_HWEVENTS)]; | |
25 | int ev_hw_idx[PERF_COUNT_ARC_HW_MAX]; | |
26 | }; | |
27 | ||
03c94fcf VG |
28 | static struct arc_pmu *arc_pmu; |
29 | ||
0dd450fe MJ |
30 | /* read counter #idx; note that counter# != event# on ARC! */ |
31 | static uint64_t arc_pmu_read_counter(int idx) | |
32 | { | |
33 | uint32_t tmp; | |
34 | uint64_t result; | |
35 | ||
36 | /* | |
37 | * ARC supports making 'snapshots' of the counters, so we don't | |
38 | * need to care about counters wrapping to 0 underneath our feet | |
39 | */ | |
40 | write_aux_reg(ARC_REG_PCT_INDEX, idx); | |
41 | tmp = read_aux_reg(ARC_REG_PCT_CONTROL); | |
42 | write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN); | |
43 | result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32; | |
44 | result |= read_aux_reg(ARC_REG_PCT_SNAPL); | |
45 | ||
46 | return result; | |
47 | } | |
48 | ||
49 | static void arc_perf_event_update(struct perf_event *event, | |
50 | struct hw_perf_event *hwc, int idx) | |
51 | { | |
0dd450fe MJ |
52 | uint64_t prev_raw_count, new_raw_count; |
53 | int64_t delta; | |
54 | ||
55 | do { | |
56 | prev_raw_count = local64_read(&hwc->prev_count); | |
57 | new_raw_count = arc_pmu_read_counter(idx); | |
58 | } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
59 | new_raw_count) != prev_raw_count); | |
60 | ||
61 | delta = (new_raw_count - prev_raw_count) & | |
62 | ((1ULL << arc_pmu->counter_size) - 1ULL); | |
63 | ||
64 | local64_add(delta, &event->count); | |
65 | local64_sub(delta, &hwc->period_left); | |
66 | } | |
67 | ||
68 | static void arc_pmu_read(struct perf_event *event) | |
69 | { | |
70 | arc_perf_event_update(event, &event->hw, event->hw.idx); | |
71 | } | |
72 | ||
73 | static int arc_pmu_cache_event(u64 config) | |
74 | { | |
75 | unsigned int cache_type, cache_op, cache_result; | |
76 | int ret; | |
77 | ||
78 | cache_type = (config >> 0) & 0xff; | |
79 | cache_op = (config >> 8) & 0xff; | |
80 | cache_result = (config >> 16) & 0xff; | |
81 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
82 | return -EINVAL; | |
da990a4f | 83 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
0dd450fe | 84 | return -EINVAL; |
da990a4f | 85 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
0dd450fe MJ |
86 | return -EINVAL; |
87 | ||
88 | ret = arc_pmu_cache_map[cache_type][cache_op][cache_result]; | |
89 | ||
90 | if (ret == CACHE_OP_UNSUPPORTED) | |
91 | return -ENOENT; | |
92 | ||
bde80c23 VG |
93 | pr_debug("init cache event: type/op/result %d/%d/%d with h/w %d \'%s\'\n", |
94 | cache_type, cache_op, cache_result, ret, | |
95 | arc_pmu_ev_hw_map[ret]); | |
96 | ||
0dd450fe MJ |
97 | return ret; |
98 | } | |
99 | ||
100 | /* initializes hw_perf_event structure if event is supported */ | |
101 | static int arc_pmu_event_init(struct perf_event *event) | |
102 | { | |
0dd450fe MJ |
103 | struct hw_perf_event *hwc = &event->hw; |
104 | int ret; | |
105 | ||
106 | switch (event->attr.type) { | |
107 | case PERF_TYPE_HARDWARE: | |
108 | if (event->attr.config >= PERF_COUNT_HW_MAX) | |
109 | return -ENOENT; | |
110 | if (arc_pmu->ev_hw_idx[event->attr.config] < 0) | |
111 | return -ENOENT; | |
112 | hwc->config = arc_pmu->ev_hw_idx[event->attr.config]; | |
bde80c23 VG |
113 | pr_debug("init event %d with h/w %d \'%s\'\n", |
114 | (int) event->attr.config, (int) hwc->config, | |
115 | arc_pmu_ev_hw_map[event->attr.config]); | |
0dd450fe MJ |
116 | return 0; |
117 | case PERF_TYPE_HW_CACHE: | |
118 | ret = arc_pmu_cache_event(event->attr.config); | |
119 | if (ret < 0) | |
120 | return ret; | |
121 | hwc->config = arc_pmu->ev_hw_idx[ret]; | |
122 | return 0; | |
123 | default: | |
124 | return -ENOENT; | |
125 | } | |
126 | } | |
127 | ||
128 | /* starts all counters */ | |
129 | static void arc_pmu_enable(struct pmu *pmu) | |
130 | { | |
131 | uint32_t tmp; | |
132 | tmp = read_aux_reg(ARC_REG_PCT_CONTROL); | |
133 | write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1); | |
134 | } | |
135 | ||
136 | /* stops all counters */ | |
137 | static void arc_pmu_disable(struct pmu *pmu) | |
138 | { | |
139 | uint32_t tmp; | |
140 | tmp = read_aux_reg(ARC_REG_PCT_CONTROL); | |
141 | write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0); | |
142 | } | |
143 | ||
144 | /* | |
145 | * Assigns hardware counter to hardware condition. | |
146 | * Note that there is no separate start/stop mechanism; | |
147 | * stopping is achieved by assigning the 'never' condition | |
148 | */ | |
149 | static void arc_pmu_start(struct perf_event *event, int flags) | |
150 | { | |
151 | struct hw_perf_event *hwc = &event->hw; | |
152 | int idx = hwc->idx; | |
153 | ||
154 | if (WARN_ON_ONCE(idx == -1)) | |
155 | return; | |
156 | ||
157 | if (flags & PERF_EF_RELOAD) | |
158 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
159 | ||
160 | event->hw.state = 0; | |
161 | ||
162 | /* enable ARC pmu here */ | |
163 | write_aux_reg(ARC_REG_PCT_INDEX, idx); | |
164 | write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); | |
165 | } | |
166 | ||
167 | static void arc_pmu_stop(struct perf_event *event, int flags) | |
168 | { | |
169 | struct hw_perf_event *hwc = &event->hw; | |
170 | int idx = hwc->idx; | |
171 | ||
172 | if (!(event->hw.state & PERF_HES_STOPPED)) { | |
173 | /* stop ARC pmu here */ | |
174 | write_aux_reg(ARC_REG_PCT_INDEX, idx); | |
175 | ||
176 | /* condition code #0 is always "never" */ | |
177 | write_aux_reg(ARC_REG_PCT_CONFIG, 0); | |
178 | ||
179 | event->hw.state |= PERF_HES_STOPPED; | |
180 | } | |
181 | ||
182 | if ((flags & PERF_EF_UPDATE) && | |
183 | !(event->hw.state & PERF_HES_UPTODATE)) { | |
184 | arc_perf_event_update(event, &event->hw, idx); | |
185 | event->hw.state |= PERF_HES_UPTODATE; | |
186 | } | |
187 | } | |
188 | ||
189 | static void arc_pmu_del(struct perf_event *event, int flags) | |
190 | { | |
0dd450fe MJ |
191 | arc_pmu_stop(event, PERF_EF_UPDATE); |
192 | __clear_bit(event->hw.idx, arc_pmu->used_mask); | |
193 | ||
194 | perf_event_update_userpage(event); | |
195 | } | |
196 | ||
197 | /* allocate hardware counter and optionally start counting */ | |
198 | static int arc_pmu_add(struct perf_event *event, int flags) | |
199 | { | |
0dd450fe MJ |
200 | struct hw_perf_event *hwc = &event->hw; |
201 | int idx = hwc->idx; | |
202 | ||
203 | if (__test_and_set_bit(idx, arc_pmu->used_mask)) { | |
204 | idx = find_first_zero_bit(arc_pmu->used_mask, | |
205 | arc_pmu->n_counters); | |
206 | if (idx == arc_pmu->n_counters) | |
207 | return -EAGAIN; | |
208 | ||
209 | __set_bit(idx, arc_pmu->used_mask); | |
210 | hwc->idx = idx; | |
211 | } | |
212 | ||
213 | write_aux_reg(ARC_REG_PCT_INDEX, idx); | |
214 | write_aux_reg(ARC_REG_PCT_CONFIG, 0); | |
215 | write_aux_reg(ARC_REG_PCT_COUNTL, 0); | |
216 | write_aux_reg(ARC_REG_PCT_COUNTH, 0); | |
217 | local64_set(&hwc->prev_count, 0); | |
218 | ||
219 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | |
220 | if (flags & PERF_EF_START) | |
221 | arc_pmu_start(event, PERF_EF_RELOAD); | |
222 | ||
223 | perf_event_update_userpage(event); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int arc_pmu_device_probe(struct platform_device *pdev) | |
229 | { | |
230 | struct arc_pmu *arc_pmu; | |
231 | struct arc_reg_pct_build pct_bcr; | |
232 | struct arc_reg_cc_build cc_bcr; | |
233 | int i, j, ret; | |
234 | ||
235 | union cc_name { | |
236 | struct { | |
237 | uint32_t word0, word1; | |
238 | char sentinel; | |
239 | } indiv; | |
240 | char str[9]; | |
241 | } cc_name; | |
242 | ||
243 | ||
244 | READ_BCR(ARC_REG_PCT_BUILD, pct_bcr); | |
245 | if (!pct_bcr.v) { | |
246 | pr_err("This core does not have performance counters!\n"); | |
247 | return -ENODEV; | |
248 | } | |
56372082 | 249 | BUG_ON(pct_bcr.c > ARC_PMU_MAX_HWEVENTS); |
0dd450fe | 250 | |
56372082 VG |
251 | READ_BCR(ARC_REG_CC_BUILD, cc_bcr); |
252 | if (!cc_bcr.v) { | |
253 | pr_err("Performance counters exist, but no countable conditions?\n"); | |
254 | return -ENODEV; | |
255 | } | |
256 | ||
257 | arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL); | |
0dd450fe MJ |
258 | if (!arc_pmu) |
259 | return -ENOMEM; | |
260 | ||
261 | arc_pmu->n_counters = pct_bcr.c; | |
0dd450fe | 262 | arc_pmu->counter_size = 32 + (pct_bcr.s << 4); |
0dd450fe | 263 | |
56372082 VG |
264 | pr_info("ARC perf\t: %d counters (%d bits), %d countable conditions\n", |
265 | arc_pmu->n_counters, arc_pmu->counter_size, cc_bcr.c); | |
0dd450fe MJ |
266 | |
267 | cc_name.str[8] = 0; | |
bde80c23 | 268 | for (i = 0; i < PERF_COUNT_ARC_HW_MAX; i++) |
0dd450fe MJ |
269 | arc_pmu->ev_hw_idx[i] = -1; |
270 | ||
bde80c23 | 271 | /* loop thru all available h/w condition indexes */ |
0dd450fe MJ |
272 | for (j = 0; j < cc_bcr.c; j++) { |
273 | write_aux_reg(ARC_REG_CC_INDEX, j); | |
274 | cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0); | |
275 | cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1); | |
bde80c23 VG |
276 | |
277 | /* See if it has been mapped to a perf event_id */ | |
0dd450fe MJ |
278 | for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) { |
279 | if (arc_pmu_ev_hw_map[i] && | |
280 | !strcmp(arc_pmu_ev_hw_map[i], cc_name.str) && | |
281 | strlen(arc_pmu_ev_hw_map[i])) { | |
bde80c23 VG |
282 | pr_debug("mapping perf event %2d to h/w event \'%8s\' (idx %d)\n", |
283 | i, cc_name.str, j); | |
0dd450fe MJ |
284 | arc_pmu->ev_hw_idx[i] = j; |
285 | } | |
286 | } | |
287 | } | |
288 | ||
289 | arc_pmu->pmu = (struct pmu) { | |
290 | .pmu_enable = arc_pmu_enable, | |
291 | .pmu_disable = arc_pmu_disable, | |
292 | .event_init = arc_pmu_event_init, | |
293 | .add = arc_pmu_add, | |
294 | .del = arc_pmu_del, | |
295 | .start = arc_pmu_start, | |
296 | .stop = arc_pmu_stop, | |
297 | .read = arc_pmu_read, | |
298 | }; | |
299 | ||
2cc9e588 VW |
300 | /* ARC 700 PMU does not support sampling events */ |
301 | arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
302 | ||
0dd450fe MJ |
303 | ret = perf_pmu_register(&arc_pmu->pmu, pdev->name, PERF_TYPE_RAW); |
304 | ||
305 | return ret; | |
306 | } | |
307 | ||
308 | #ifdef CONFIG_OF | |
309 | static const struct of_device_id arc_pmu_match[] = { | |
310 | { .compatible = "snps,arc700-pmu" }, | |
311 | {}, | |
312 | }; | |
313 | MODULE_DEVICE_TABLE(of, arc_pmu_match); | |
314 | #endif | |
315 | ||
316 | static struct platform_driver arc_pmu_driver = { | |
317 | .driver = { | |
318 | .name = "arc700-pmu", | |
319 | .of_match_table = of_match_ptr(arc_pmu_match), | |
320 | }, | |
321 | .probe = arc_pmu_device_probe, | |
322 | }; | |
323 | ||
324 | module_platform_driver(arc_pmu_driver); | |
325 | ||
326 | MODULE_LICENSE("GPL"); | |
327 | MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>"); | |
328 | MODULE_DESCRIPTION("ARC PMU driver"); |