Commit | Line | Data |
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c121c506 VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/seq_file.h> | |
10 | #include <linux/fs.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/root_dev.h> | |
13 | #include <linux/console.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/cpu.h> | |
999159a5 | 16 | #include <linux/of_fdt.h> |
d7f8a085 | 17 | #include <linux/of_platform.h> |
1ec9db10 | 18 | #include <linux/cache.h> |
999159a5 | 19 | #include <asm/sections.h> |
c121c506 VG |
20 | #include <asm/arcregs.h> |
21 | #include <asm/tlb.h> | |
c121c506 VG |
22 | #include <asm/setup.h> |
23 | #include <asm/page.h> | |
24 | #include <asm/irq.h> | |
854a0d95 | 25 | #include <asm/unwind.h> |
03a6d28c | 26 | #include <asm/mach_desc.h> |
619f3018 | 27 | #include <asm/smp.h> |
c121c506 VG |
28 | |
29 | #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) | |
30 | ||
4255b07f VG |
31 | unsigned int intr_to_DE_cnt; |
32 | ||
59ed9413 VG |
33 | /* Part of U-boot ABI: see head.S */ |
34 | int __initdata uboot_tag; | |
35 | char __initdata *uboot_arg; | |
36 | ||
880beb88 | 37 | const struct machine_desc *machine_desc; |
c121c506 VG |
38 | |
39 | struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ | |
40 | ||
41 | struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; | |
42 | ||
a150b085 VG |
43 | static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu) |
44 | { | |
45 | if (is_isa_arcompact()) { | |
46 | struct bcr_iccm_arcompact iccm; | |
47 | struct bcr_dccm_arcompact dccm; | |
48 | ||
49 | READ_BCR(ARC_REG_ICCM_BUILD, iccm); | |
50 | if (iccm.ver) { | |
51 | cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */ | |
52 | cpu->iccm.base_addr = iccm.base << 16; | |
53 | } | |
54 | ||
55 | READ_BCR(ARC_REG_DCCM_BUILD, dccm); | |
56 | if (dccm.ver) { | |
57 | unsigned long base; | |
58 | cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */ | |
59 | ||
60 | base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD); | |
61 | cpu->dccm.base_addr = base & ~0xF; | |
62 | } | |
63 | } else { | |
64 | struct bcr_iccm_arcv2 iccm; | |
65 | struct bcr_dccm_arcv2 dccm; | |
66 | unsigned long region; | |
67 | ||
68 | READ_BCR(ARC_REG_ICCM_BUILD, iccm); | |
69 | if (iccm.ver) { | |
70 | cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */ | |
71 | if (iccm.sz00 == 0xF && iccm.sz01 > 0) | |
72 | cpu->iccm.sz <<= iccm.sz01; | |
73 | ||
74 | region = read_aux_reg(ARC_REG_AUX_ICCM); | |
75 | cpu->iccm.base_addr = region & 0xF0000000; | |
76 | } | |
77 | ||
78 | READ_BCR(ARC_REG_DCCM_BUILD, dccm); | |
79 | if (dccm.ver) { | |
80 | cpu->dccm.sz = 256 << dccm.sz0; | |
81 | if (dccm.sz0 == 0xF && dccm.sz1 > 0) | |
82 | cpu->dccm.sz <<= dccm.sz1; | |
83 | ||
84 | region = read_aux_reg(ARC_REG_AUX_DCCM); | |
85 | cpu->dccm.base_addr = region & 0xF0000000; | |
86 | } | |
87 | } | |
88 | } | |
89 | ||
8e457d6a | 90 | static void read_arc_build_cfg_regs(void) |
c121c506 | 91 | { |
b89bd1f4 | 92 | struct bcr_timer timer; |
56372082 | 93 | struct bcr_generic bcr; |
af617428 VG |
94 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; |
95 | FIX_PTR(cpu); | |
96 | ||
97 | READ_BCR(AUX_IDENTITY, cpu->core); | |
56372082 | 98 | READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa); |
af617428 | 99 | |
b89bd1f4 VG |
100 | READ_BCR(ARC_REG_TIMERS_BCR, timer); |
101 | cpu->extn.timer0 = timer.t0; | |
102 | cpu->extn.timer1 = timer.t1; | |
103 | cpu->extn.rtc = timer.rtc; | |
104 | ||
af617428 | 105 | cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); |
af617428 | 106 | |
56372082 | 107 | READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); |
af617428 | 108 | |
56372082 VG |
109 | cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ |
110 | cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ | |
111 | cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ | |
112 | cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; | |
113 | cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ | |
af617428 VG |
114 | READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); |
115 | ||
a150b085 VG |
116 | /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */ |
117 | read_decode_ccm_bcr(cpu); | |
118 | ||
c121c506 VG |
119 | read_decode_mmu_bcr(); |
120 | read_decode_cache_bcr(); | |
af617428 | 121 | |
1f6ccfff | 122 | if (is_isa_arcompact()) { |
56372082 VG |
123 | struct bcr_fp_arcompact sp, dp; |
124 | struct bcr_bpu_arcompact bpu; | |
125 | ||
126 | READ_BCR(ARC_REG_FP_BCR, sp); | |
127 | READ_BCR(ARC_REG_DPFP_BCR, dp); | |
128 | cpu->extn.fpu_sp = sp.ver ? 1 : 0; | |
129 | cpu->extn.fpu_dp = dp.ver ? 1 : 0; | |
130 | ||
131 | READ_BCR(ARC_REG_BPU_BCR, bpu); | |
132 | cpu->bpu.ver = bpu.ver; | |
133 | cpu->bpu.full = bpu.fam ? 1 : 0; | |
134 | if (bpu.ent) { | |
135 | cpu->bpu.num_cache = 256 << (bpu.ent - 1); | |
136 | cpu->bpu.num_pred = 256 << (bpu.ent - 1); | |
137 | } | |
1f6ccfff VG |
138 | } else { |
139 | struct bcr_fp_arcv2 spdp; | |
140 | struct bcr_bpu_arcv2 bpu; | |
141 | ||
142 | READ_BCR(ARC_REG_FP_V2_BCR, spdp); | |
143 | cpu->extn.fpu_sp = spdp.sp ? 1 : 0; | |
144 | cpu->extn.fpu_dp = spdp.dp ? 1 : 0; | |
145 | ||
146 | READ_BCR(ARC_REG_BPU_BCR, bpu); | |
147 | cpu->bpu.ver = bpu.ver; | |
148 | cpu->bpu.full = bpu.ft; | |
149 | cpu->bpu.num_cache = 256 << bpu.bce; | |
150 | cpu->bpu.num_pred = 2048 << bpu.pte; | |
56372082 VG |
151 | } |
152 | ||
153 | READ_BCR(ARC_REG_AP_BCR, bcr); | |
154 | cpu->extn.ap = bcr.ver ? 1 : 0; | |
155 | ||
156 | READ_BCR(ARC_REG_SMART_BCR, bcr); | |
157 | cpu->extn.smart = bcr.ver ? 1 : 0; | |
158 | ||
a44ec8bd VG |
159 | READ_BCR(ARC_REG_RTT_BCR, bcr); |
160 | cpu->extn.rtt = bcr.ver ? 1 : 0; | |
161 | ||
162 | cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt; | |
af617428 VG |
163 | } |
164 | ||
165 | static const struct cpuinfo_data arc_cpu_tbl[] = { | |
624b71ee | 166 | #ifdef CONFIG_ISA_ARCOMPACT |
af617428 VG |
167 | { {0x20, "ARC 600" }, 0x2F}, |
168 | { {0x30, "ARC 700" }, 0x33}, | |
169 | { {0x34, "ARC 700 R4.10"}, 0x34}, | |
56372082 | 170 | { {0x35, "ARC 700 R4.11"}, 0x35}, |
624b71ee VG |
171 | #else |
172 | { {0x50, "ARC HS38 R2.0"}, 0x51}, | |
173 | { {0x52, "ARC HS38 R2.1"}, 0x52}, | |
174 | #endif | |
af617428 VG |
175 | { {0x00, NULL } } |
176 | }; | |
177 | ||
56372082 | 178 | |
8e457d6a | 179 | static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) |
af617428 | 180 | { |
af617428 VG |
181 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; |
182 | struct bcr_identity *core = &cpu->core; | |
183 | const struct cpuinfo_data *tbl; | |
56372082 VG |
184 | char *isa_nm; |
185 | int i, be, atomic; | |
186 | int n = 0; | |
187 | ||
af617428 VG |
188 | FIX_PTR(cpu); |
189 | ||
1f6ccfff | 190 | if (is_isa_arcompact()) { |
56372082 VG |
191 | isa_nm = "ARCompact"; |
192 | be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); | |
193 | ||
194 | atomic = cpu->isa.atomic1; | |
195 | if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */ | |
196 | atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); | |
1f6ccfff VG |
197 | } else { |
198 | isa_nm = "ARCv2"; | |
199 | be = cpu->isa.be; | |
200 | atomic = cpu->isa.atomic; | |
56372082 VG |
201 | } |
202 | ||
af617428 | 203 | n += scnprintf(buf + n, len - n, |
56372082 VG |
204 | "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", |
205 | core->family, core->cpu_id, core->chip_id); | |
af617428 VG |
206 | |
207 | for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) { | |
208 | if ((core->family >= tbl->info.id) && | |
209 | (core->family <= tbl->up_range)) { | |
210 | n += scnprintf(buf + n, len - n, | |
56372082 VG |
211 | "processor [%d]\t: %s (%s ISA) %s\n", |
212 | cpu_id, tbl->info.str, isa_nm, | |
213 | IS_AVAIL1(be, "[Big-Endian]")); | |
af617428 VG |
214 | break; |
215 | } | |
216 | } | |
217 | ||
218 | if (tbl->info.id == 0) | |
219 | n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n"); | |
220 | ||
aa93e8ef | 221 | n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ", |
b89bd1f4 VG |
222 | IS_AVAIL1(cpu->extn.timer0, "Timer0 "), |
223 | IS_AVAIL1(cpu->extn.timer1, "Timer1 "), | |
224 | IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ", | |
aa93e8ef | 225 | CONFIG_ARC_HAS_RTC)); |
af617428 | 226 | |
1f6ccfff VG |
227 | n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s", |
228 | IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC), | |
229 | IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), | |
230 | IS_AVAIL1(cpu->isa.unalign, "unalign (not used)")); | |
af617428 | 231 | |
56372082 VG |
232 | if (i) |
233 | n += scnprintf(buf + n, len - n, "\n\t\t: "); | |
af617428 | 234 | |
1f6ccfff VG |
235 | if (cpu->extn_mpy.ver) { |
236 | if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */ | |
237 | n += scnprintf(buf + n, len - n, "mpy "); | |
238 | } else { | |
239 | int opt = 2; /* stock MPY/MPYH */ | |
240 | ||
241 | if (cpu->extn_mpy.dsp) /* OPT 7-9 */ | |
242 | opt = cpu->extn_mpy.dsp + 6; | |
243 | ||
244 | n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); | |
245 | } | |
1f6ccfff VG |
246 | } |
247 | ||
56372082 | 248 | n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", |
1f6ccfff | 249 | IS_AVAIL1(cpu->isa.div_rem, "div_rem "), |
56372082 VG |
250 | IS_AVAIL1(cpu->extn.norm, "norm "), |
251 | IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), | |
252 | IS_AVAIL1(cpu->extn.swap, "swap "), | |
253 | IS_AVAIL1(cpu->extn.minmax, "minmax "), | |
254 | IS_AVAIL1(cpu->extn.crc, "crc "), | |
255 | IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE)); | |
af617428 | 256 | |
56372082 VG |
257 | if (cpu->bpu.ver) |
258 | n += scnprintf(buf + n, len - n, | |
259 | "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n", | |
260 | IS_AVAIL1(cpu->bpu.full, "full"), | |
261 | IS_AVAIL1(!cpu->bpu.full, "partial"), | |
262 | cpu->bpu.num_cache, cpu->bpu.num_pred); | |
af617428 | 263 | |
56372082 VG |
264 | return buf; |
265 | } | |
af617428 | 266 | |
8e457d6a | 267 | static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) |
af617428 VG |
268 | { |
269 | int n = 0; | |
270 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; | |
271 | ||
272 | FIX_PTR(cpu); | |
af617428 VG |
273 | |
274 | n += scnprintf(buf + n, len - n, | |
deaf7565 VG |
275 | "Vector Table\t: %#x\nUncached Base\t: %#lx\n", |
276 | cpu->vec_base, perip_base); | |
56372082 VG |
277 | |
278 | if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) | |
279 | n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", | |
280 | IS_AVAIL1(cpu->extn.fpu_sp, "SP "), | |
281 | IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); | |
282 | ||
283 | if (cpu->extn.debug) | |
284 | n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n", | |
285 | IS_AVAIL1(cpu->extn.ap, "ActionPoint "), | |
286 | IS_AVAIL1(cpu->extn.smart, "smaRT "), | |
287 | IS_AVAIL1(cpu->extn.rtt, "RTT ")); | |
288 | ||
289 | if (cpu->dccm.sz || cpu->iccm.sz) | |
290 | n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", | |
291 | cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), | |
af617428 VG |
292 | cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); |
293 | ||
af617428 | 294 | n += scnprintf(buf + n, len - n, |
8ff14bbc | 295 | "OS ABI [v3]\t: no-legacy-syscalls\n"); |
af617428 VG |
296 | |
297 | return buf; | |
298 | } | |
299 | ||
c4b9856b | 300 | static void arc_chk_core_config(void) |
8b5850f8 | 301 | { |
8b5850f8 | 302 | struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; |
c4b9856b | 303 | int fpu_enabled; |
8b5850f8 | 304 | |
b89bd1f4 | 305 | if (!cpu->extn.timer0) |
56372082 VG |
306 | panic("Timer0 is not present!\n"); |
307 | ||
b89bd1f4 | 308 | if (!cpu->extn.timer1) |
56372082 VG |
309 | panic("Timer1 is not present!\n"); |
310 | ||
8b5850f8 VG |
311 | #ifdef CONFIG_ARC_HAS_DCCM |
312 | /* | |
313 | * DCCM can be arbit placed in hardware. | |
314 | * Make sure it's placement/sz matches what Linux is built with | |
315 | */ | |
316 | if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) | |
317 | panic("Linux built with incorrect DCCM Base address\n"); | |
318 | ||
319 | if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz) | |
320 | panic("Linux built with incorrect DCCM Size\n"); | |
321 | #endif | |
322 | ||
323 | #ifdef CONFIG_ARC_HAS_ICCM | |
324 | if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) | |
325 | panic("Linux built with incorrect ICCM Size\n"); | |
326 | #endif | |
8b5850f8 | 327 | |
c4b9856b VG |
328 | /* |
329 | * FP hardware/software config sanity | |
330 | * -If hardware contains DPFP, kernel needs to save/restore FPU state | |
331 | * -If not, it will crash trying to save/restore the non-existant regs | |
332 | * | |
333 | * (only DPDP checked since SP has no arch visible regs) | |
334 | */ | |
335 | fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE); | |
af617428 | 336 | |
56372082 | 337 | if (cpu->extn.fpu_dp && !fpu_enabled) |
c4b9856b | 338 | pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n"); |
56372082 | 339 | else if (!cpu->extn.fpu_dp && fpu_enabled) |
c4b9856b | 340 | panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n"); |
c121c506 VG |
341 | } |
342 | ||
343 | /* | |
344 | * Initialize and setup the processor core | |
345 | * This is called by all the CPUs thus should not do special case stuff | |
346 | * such as only for boot CPU etc | |
347 | */ | |
348 | ||
ce759956 | 349 | void setup_processor(void) |
c121c506 | 350 | { |
af617428 VG |
351 | char str[512]; |
352 | int cpu_id = smp_processor_id(); | |
353 | ||
c121c506 VG |
354 | read_arc_build_cfg_regs(); |
355 | arc_init_IRQ(); | |
af617428 VG |
356 | |
357 | printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); | |
358 | ||
c121c506 VG |
359 | arc_mmu_init(); |
360 | arc_cache_init(); | |
af617428 VG |
361 | |
362 | printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); | |
af617428 | 363 | printk(arc_platform_smp_cpuinfo()); |
af617428 | 364 | |
c4b9856b | 365 | arc_chk_core_config(); |
c121c506 VG |
366 | } |
367 | ||
59ed9413 VG |
368 | static inline int is_kernel(unsigned long addr) |
369 | { | |
370 | if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end) | |
371 | return 1; | |
372 | return 0; | |
373 | } | |
374 | ||
c121c506 VG |
375 | void __init setup_arch(char **cmdline_p) |
376 | { | |
036b2c56 | 377 | #ifdef CONFIG_ARC_UBOOT_SUPPORT |
e57d339a VG |
378 | /* make sure that uboot passed pointer to cmdline/dtb is valid */ |
379 | if (uboot_tag && is_kernel((unsigned long)uboot_arg)) | |
380 | panic("Invalid uboot arg\n"); | |
381 | ||
382 | /* See if u-boot passed an external Device Tree blob */ | |
383 | machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */ | |
036b2c56 VG |
384 | if (!machine_desc) |
385 | #endif | |
386 | { | |
e57d339a | 387 | /* No, so try the embedded one */ |
59ed9413 VG |
388 | machine_desc = setup_machine_fdt(__dtb_start); |
389 | if (!machine_desc) | |
390 | panic("Embedded DT invalid\n"); | |
391 | ||
392 | /* | |
e57d339a VG |
393 | * If we are here, it is established that @uboot_arg didn't |
394 | * point to DT blob. Instead if u-boot says it is cmdline, | |
395 | * Appent to embedded DT cmdline. | |
59ed9413 VG |
396 | * setup_machine_fdt() would have populated @boot_command_line |
397 | */ | |
398 | if (uboot_tag == 1) { | |
59ed9413 VG |
399 | /* Ensure a whitespace between the 2 cmdlines */ |
400 | strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); | |
401 | strlcat(boot_command_line, uboot_arg, | |
402 | COMMAND_LINE_SIZE); | |
403 | } | |
e57d339a | 404 | } |
c121c506 VG |
405 | |
406 | /* Save unparsed command line copy for /proc/cmdline */ | |
9593a933 | 407 | *cmdline_p = boot_command_line; |
999159a5 | 408 | |
c121c506 VG |
409 | /* To force early parsing of things like mem=xxx */ |
410 | parse_early_param(); | |
411 | ||
412 | /* Platform/board specific: e.g. early console registration */ | |
03a6d28c VG |
413 | if (machine_desc->init_early) |
414 | machine_desc->init_early(); | |
c121c506 | 415 | |
41195d23 | 416 | smp_init_cpus(); |
e55af4da VG |
417 | |
418 | setup_processor(); | |
c121c506 VG |
419 | setup_arch_memory(); |
420 | ||
eab6a08c | 421 | /* copy flat DT out of .init and then unflatten it */ |
1efc959e | 422 | unflatten_and_copy_device_tree(); |
999159a5 | 423 | |
c121c506 VG |
424 | /* Can be issue if someone passes cmd line arg "ro" |
425 | * But that is unlikely so keeping it as it is | |
426 | */ | |
427 | root_mountflags &= ~MS_RDONLY; | |
428 | ||
c121c506 VG |
429 | #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) |
430 | conswitchp = &dummy_con; | |
431 | #endif | |
432 | ||
854a0d95 | 433 | arc_unwind_init(); |
c121c506 VG |
434 | } |
435 | ||
03a6d28c VG |
436 | static int __init customize_machine(void) |
437 | { | |
d7f8a085 VG |
438 | /* |
439 | * Traverses flattened DeviceTree - registering platform devices | |
440 | * (if any) complete with their resources | |
441 | */ | |
26cf9cc5 | 442 | of_platform_default_populate(NULL, NULL, NULL); |
d7f8a085 | 443 | |
03a6d28c VG |
444 | if (machine_desc->init_machine) |
445 | machine_desc->init_machine(); | |
446 | ||
447 | return 0; | |
448 | } | |
449 | arch_initcall(customize_machine); | |
450 | ||
451 | static int __init init_late_machine(void) | |
452 | { | |
453 | if (machine_desc->init_late) | |
454 | machine_desc->init_late(); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | late_initcall(init_late_machine); | |
c121c506 VG |
459 | /* |
460 | * Get CPU information for use by the procfs. | |
461 | */ | |
462 | ||
463 | #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c))) | |
464 | #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p)) | |
465 | ||
466 | static int show_cpuinfo(struct seq_file *m, void *v) | |
467 | { | |
468 | char *str; | |
469 | int cpu_id = ptr_to_cpu(v); | |
20c7dbbd AB |
470 | struct device_node *core_clk = of_find_node_by_name(NULL, "core_clk"); |
471 | u32 freq = 0; | |
c121c506 | 472 | |
4c86231c VG |
473 | if (!cpu_online(cpu_id)) { |
474 | seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); | |
475 | goto done; | |
476 | } | |
477 | ||
c121c506 VG |
478 | str = (char *)__get_free_page(GFP_TEMPORARY); |
479 | if (!str) | |
480 | goto done; | |
481 | ||
af617428 | 482 | seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
c121c506 | 483 | |
20c7dbbd AB |
484 | of_property_read_u32(core_clk, "clock-frequency", &freq); |
485 | if (freq) | |
486 | seq_printf(m, "CPU speed\t: %u.%02u Mhz\n", | |
487 | freq / 1000000, (freq / 10000) % 100); | |
488 | ||
56372082 | 489 | seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", |
c121c506 VG |
490 | loops_per_jiffy / (500000 / HZ), |
491 | (loops_per_jiffy / (5000 / HZ)) % 100); | |
492 | ||
af617428 | 493 | seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 494 | seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 495 | seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); |
af617428 | 496 | seq_printf(m, arc_platform_smp_cpuinfo()); |
af617428 | 497 | |
c121c506 VG |
498 | free_page((unsigned long)str); |
499 | done: | |
4c86231c | 500 | seq_printf(m, "\n"); |
c121c506 VG |
501 | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static void *c_start(struct seq_file *m, loff_t *pos) | |
506 | { | |
507 | /* | |
508 | * Callback returns cpu-id to iterator for show routine, NULL to stop. | |
509 | * However since NULL is also a valid cpu-id (0), we use a round-about | |
510 | * way to pass it w/o having to kmalloc/free a 2 byte string. | |
511 | * Encode cpu-id as 0xFFcccc, which is decoded by show routine. | |
512 | */ | |
513 | return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL; | |
514 | } | |
515 | ||
516 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
517 | { | |
518 | ++*pos; | |
519 | return c_start(m, pos); | |
520 | } | |
521 | ||
522 | static void c_stop(struct seq_file *m, void *v) | |
523 | { | |
524 | } | |
525 | ||
526 | const struct seq_operations cpuinfo_op = { | |
527 | .start = c_start, | |
528 | .next = c_next, | |
529 | .stop = c_stop, | |
530 | .show = show_cpuinfo | |
531 | }; | |
532 | ||
533 | static DEFINE_PER_CPU(struct cpu, cpu_topology); | |
534 | ||
535 | static int __init topology_init(void) | |
536 | { | |
537 | int cpu; | |
538 | ||
539 | for_each_present_cpu(cpu) | |
540 | register_cpu(&per_cpu(cpu_topology, cpu), cpu); | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
545 | subsys_initcall(topology_init); |