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41195d23 VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * RajeshwarR: Dec 11, 2007 | |
9 | * -- Added support for Inter Processor Interrupts | |
10 | * | |
11 | * Vineetg: Nov 1st, 2007 | |
12 | * -- Initial Write (Borrowed heavily from ARM) | |
13 | */ | |
14 | ||
41195d23 VG |
15 | #include <linux/spinlock.h> |
16 | #include <linux/sched.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/profile.h> | |
41195d23 VG |
19 | #include <linux/mm.h> |
20 | #include <linux/cpu.h> | |
41195d23 | 21 | #include <linux/irq.h> |
41195d23 | 22 | #include <linux/atomic.h> |
41195d23 | 23 | #include <linux/cpumask.h> |
41195d23 VG |
24 | #include <linux/reboot.h> |
25 | #include <asm/processor.h> | |
26 | #include <asm/setup.h> | |
03a6d28c | 27 | #include <asm/mach_desc.h> |
41195d23 VG |
28 | |
29 | arch_spinlock_t smp_atomic_ops_lock = __ARCH_SPIN_LOCK_UNLOCKED; | |
30 | arch_spinlock_t smp_bitops_lock = __ARCH_SPIN_LOCK_UNLOCKED; | |
31 | ||
10b12718 VG |
32 | struct plat_smp_ops plat_smp_ops; |
33 | ||
41195d23 VG |
34 | /* XXX: per cpu ? Only needed once in early seconday boot */ |
35 | struct task_struct *secondary_idle_tsk; | |
36 | ||
37 | /* Called from start_kernel */ | |
38 | void __init smp_prepare_boot_cpu(void) | |
39 | { | |
40 | } | |
41 | ||
42 | /* | |
43 | * Initialise the CPU possible map early - this describes the CPUs | |
44 | * which may be present or become present in the system. | |
45 | */ | |
46 | void __init smp_init_cpus(void) | |
47 | { | |
48 | unsigned int i; | |
49 | ||
50 | for (i = 0; i < NR_CPUS; i++) | |
51 | set_cpu_possible(i, true); | |
52 | } | |
53 | ||
54 | /* called from init ( ) => process 1 */ | |
55 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
56 | { | |
57 | int i; | |
58 | ||
59 | /* | |
60 | * Initialise the present map, which describes the set of CPUs | |
61 | * actually populated at the present time. | |
62 | */ | |
63 | for (i = 0; i < max_cpus; i++) | |
64 | set_cpu_present(i, true); | |
65 | } | |
66 | ||
67 | void __init smp_cpus_done(unsigned int max_cpus) | |
68 | { | |
69 | ||
70 | } | |
71 | ||
72 | /* | |
73 | * After power-up, a non Master CPU needs to wait for Master to kick start it | |
74 | * | |
75 | * The default implementation halts | |
76 | * | |
77 | * This relies on platform specific support allowing Master to directly set | |
78 | * this CPU's PC (to be @first_lines_of_secondary() and kick start it. | |
79 | * | |
80 | * In lack of such h/w assist, platforms can override this function | |
81 | * - make this function busy-spin on a token, eventually set by Master | |
82 | * (from arc_platform_smp_wakeup_cpu()) | |
83 | * - Once token is available, jump to @first_lines_of_secondary | |
84 | * (using inline asm). | |
85 | * | |
86 | * Alert: can NOT use stack here as it has not been determined/setup for CPU. | |
87 | * If it turns out to be elaborate, it's better to code it in assembly | |
88 | * | |
89 | */ | |
064a6269 | 90 | void __weak arc_platform_smp_wait_to_boot(int cpu) |
41195d23 VG |
91 | { |
92 | /* | |
93 | * As a hack for debugging - since debugger will single-step over the | |
94 | * FLAG insn - wrap the halt itself it in a self loop | |
95 | */ | |
96 | __asm__ __volatile__( | |
97 | "1: \n" | |
98 | " flag 1 \n" | |
99 | " b 1b \n"); | |
100 | } | |
101 | ||
10b12718 VG |
102 | const char *arc_platform_smp_cpuinfo(void) |
103 | { | |
619f3018 | 104 | return plat_smp_ops.info ? : ""; |
10b12718 VG |
105 | } |
106 | ||
41195d23 VG |
107 | /* |
108 | * The very first "C" code executed by secondary | |
109 | * Called from asm stub in head.S | |
110 | * "current"/R25 already setup by low level boot code | |
111 | */ | |
ce759956 | 112 | void start_kernel_secondary(void) |
41195d23 VG |
113 | { |
114 | struct mm_struct *mm = &init_mm; | |
115 | unsigned int cpu = smp_processor_id(); | |
116 | ||
117 | /* MMU, Caches, Vector Table, Interrupts etc */ | |
118 | setup_processor(); | |
119 | ||
120 | atomic_inc(&mm->mm_users); | |
121 | atomic_inc(&mm->mm_count); | |
122 | current->active_mm = mm; | |
5ea72a90 | 123 | cpumask_set_cpu(cpu, mm_cpumask(mm)); |
41195d23 VG |
124 | |
125 | notify_cpu_starting(cpu); | |
126 | set_cpu_online(cpu, true); | |
127 | ||
128 | pr_info("## CPU%u LIVE ##: Executing Code...\n", cpu); | |
129 | ||
03a6d28c | 130 | if (machine_desc->init_smp) |
2b75c0f9 | 131 | machine_desc->init_smp(cpu); |
41195d23 | 132 | |
2d4899f6 | 133 | arc_local_timer_setup(); |
41195d23 VG |
134 | |
135 | local_irq_enable(); | |
136 | preempt_disable(); | |
fa35e42a | 137 | cpu_startup_entry(CPUHP_ONLINE); |
41195d23 VG |
138 | } |
139 | ||
140 | /* | |
141 | * Called from kernel_init( ) -> smp_init( ) - for each CPU | |
142 | * | |
143 | * At this point, Secondary Processor is "HALT"ed: | |
144 | * -It booted, but was halted in head.S | |
145 | * -It was configured to halt-on-reset | |
146 | * So need to wake it up. | |
147 | * | |
148 | * Essential requirements being where to run from (PC) and stack (SP) | |
149 | */ | |
ce759956 | 150 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
41195d23 VG |
151 | { |
152 | unsigned long wait_till; | |
153 | ||
154 | secondary_idle_tsk = idle; | |
155 | ||
156 | pr_info("Idle Task [%d] %p", cpu, idle); | |
157 | pr_info("Trying to bring up CPU%u ...\n", cpu); | |
158 | ||
10b12718 VG |
159 | if (plat_smp_ops.cpu_kick) |
160 | plat_smp_ops.cpu_kick(cpu, | |
41195d23 VG |
161 | (unsigned long)first_lines_of_secondary); |
162 | ||
163 | /* wait for 1 sec after kicking the secondary */ | |
164 | wait_till = jiffies + HZ; | |
165 | while (time_before(jiffies, wait_till)) { | |
166 | if (cpu_online(cpu)) | |
167 | break; | |
168 | } | |
169 | ||
170 | if (!cpu_online(cpu)) { | |
171 | pr_info("Timeout: CPU%u FAILED to comeup !!!\n", cpu); | |
172 | return -1; | |
173 | } | |
174 | ||
175 | secondary_idle_tsk = NULL; | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | /* | |
181 | * not supported here | |
182 | */ | |
183 | int __init setup_profiling_timer(unsigned int multiplier) | |
184 | { | |
185 | return -EINVAL; | |
186 | } | |
187 | ||
188 | /*****************************************************************************/ | |
189 | /* Inter Processor Interrupt Handling */ | |
190 | /*****************************************************************************/ | |
191 | ||
41195d23 | 192 | enum ipi_msg_type { |
f2a4aa56 | 193 | IPI_EMPTY = 0, |
41195d23 VG |
194 | IPI_RESCHEDULE = 1, |
195 | IPI_CALL_FUNC, | |
f2a4aa56 | 196 | IPI_CPU_STOP, |
41195d23 VG |
197 | }; |
198 | ||
f2a4aa56 VG |
199 | /* |
200 | * In arches with IRQ for each msg type (above), receiver can use IRQ-id to | |
201 | * figure out what msg was sent. For those which don't (ARC has dedicated IPI | |
202 | * IRQ), the msg-type needs to be conveyed via per-cpu data | |
203 | */ | |
41195d23 | 204 | |
f2a4aa56 | 205 | static DEFINE_PER_CPU(unsigned long, ipi_data); |
41195d23 | 206 | |
ddf84433 | 207 | static void ipi_send_msg_one(int cpu, enum ipi_msg_type msg) |
41195d23 | 208 | { |
f2a4aa56 | 209 | unsigned long __percpu *ipi_data_ptr = per_cpu_ptr(&ipi_data, cpu); |
d8e8c7dd | 210 | unsigned long old, new; |
41195d23 | 211 | unsigned long flags; |
41195d23 | 212 | |
f2a4aa56 VG |
213 | pr_debug("%d Sending msg [%d] to %d\n", smp_processor_id(), msg, cpu); |
214 | ||
41195d23 VG |
215 | local_irq_save(flags); |
216 | ||
d8e8c7dd VG |
217 | /* |
218 | * Atomically write new msg bit (in case others are writing too), | |
219 | * and read back old value | |
220 | */ | |
221 | do { | |
222 | new = old = *ipi_data_ptr; | |
223 | new |= 1U << msg; | |
224 | } while (cmpxchg(ipi_data_ptr, old, new) != old); | |
41195d23 | 225 | |
d8e8c7dd VG |
226 | /* |
227 | * Call the platform specific IPI kick function, but avoid if possible: | |
228 | * Only do so if there's no pending msg from other concurrent sender(s). | |
229 | * Otherwise, recevier will see this msg as well when it takes the | |
230 | * IPI corresponding to that msg. This is true, even if it is already in | |
231 | * IPI handler, because !@old means it has not yet dequeued the msg(s) | |
232 | * so @new msg can be a free-loader | |
233 | */ | |
234 | if (plat_smp_ops.ipi_send && !old) | |
ddf84433 | 235 | plat_smp_ops.ipi_send(cpu); |
41195d23 VG |
236 | |
237 | local_irq_restore(flags); | |
238 | } | |
239 | ||
ddf84433 VG |
240 | static void ipi_send_msg(const struct cpumask *callmap, enum ipi_msg_type msg) |
241 | { | |
242 | unsigned int cpu; | |
243 | ||
244 | for_each_cpu(cpu, callmap) | |
245 | ipi_send_msg_one(cpu, msg); | |
246 | } | |
247 | ||
41195d23 VG |
248 | void smp_send_reschedule(int cpu) |
249 | { | |
ddf84433 | 250 | ipi_send_msg_one(cpu, IPI_RESCHEDULE); |
41195d23 VG |
251 | } |
252 | ||
253 | void smp_send_stop(void) | |
254 | { | |
255 | struct cpumask targets; | |
256 | cpumask_copy(&targets, cpu_online_mask); | |
257 | cpumask_clear_cpu(smp_processor_id(), &targets); | |
258 | ipi_send_msg(&targets, IPI_CPU_STOP); | |
259 | } | |
260 | ||
261 | void arch_send_call_function_single_ipi(int cpu) | |
262 | { | |
ddf84433 | 263 | ipi_send_msg_one(cpu, IPI_CALL_FUNC); |
41195d23 VG |
264 | } |
265 | ||
266 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) | |
267 | { | |
268 | ipi_send_msg(mask, IPI_CALL_FUNC); | |
269 | } | |
270 | ||
271 | /* | |
272 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
273 | */ | |
53dc110c | 274 | static void ipi_cpu_stop(void) |
41195d23 VG |
275 | { |
276 | machine_halt(); | |
277 | } | |
278 | ||
d8e8c7dd | 279 | static inline void __do_IPI(unsigned long msg) |
41195d23 | 280 | { |
d8e8c7dd VG |
281 | switch (msg) { |
282 | case IPI_RESCHEDULE: | |
283 | scheduler_ipi(); | |
284 | break; | |
41195d23 | 285 | |
d8e8c7dd VG |
286 | case IPI_CALL_FUNC: |
287 | generic_smp_call_function_interrupt(); | |
288 | break; | |
f2a4aa56 | 289 | |
d8e8c7dd VG |
290 | case IPI_CPU_STOP: |
291 | ipi_cpu_stop(); | |
292 | break; | |
f2a4aa56 | 293 | |
d8e8c7dd VG |
294 | default: |
295 | pr_warn("IPI with unexpected msg %ld\n", msg); | |
f2a4aa56 | 296 | } |
41195d23 VG |
297 | } |
298 | ||
299 | /* | |
300 | * arch-common ISR to handle for inter-processor interrupts | |
301 | * Has hooks for platform specific IPI | |
302 | */ | |
303 | irqreturn_t do_IPI(int irq, void *dev_id) | |
304 | { | |
f2a4aa56 VG |
305 | unsigned long pending; |
306 | ||
307 | pr_debug("IPI [%ld] received on cpu %d\n", | |
308 | *this_cpu_ptr(&ipi_data), smp_processor_id()); | |
41195d23 | 309 | |
10b12718 | 310 | if (plat_smp_ops.ipi_clear) |
ccdaa6e0 | 311 | plat_smp_ops.ipi_clear(irq); |
41195d23 VG |
312 | |
313 | /* | |
d8e8c7dd VG |
314 | * "dequeue" the msg corresponding to this IPI (and possibly other |
315 | * piggybacked msg from elided IPIs: see ipi_send_msg_one() above) | |
41195d23 | 316 | */ |
d8e8c7dd VG |
317 | pending = xchg(this_cpu_ptr(&ipi_data), 0); |
318 | ||
319 | do { | |
320 | unsigned long msg = __ffs(pending); | |
321 | __do_IPI(msg); | |
322 | pending &= ~(1U << msg); | |
323 | } while (pending); | |
41195d23 VG |
324 | |
325 | return IRQ_HANDLED; | |
326 | } | |
327 | ||
328 | /* | |
329 | * API called by platform code to hookup arch-common ISR to their IPI IRQ | |
330 | */ | |
331 | static DEFINE_PER_CPU(int, ipi_dev); | |
7e512219 | 332 | |
41195d23 VG |
333 | int smp_ipi_irq_setup(int cpu, int irq) |
334 | { | |
2b75c0f9 VG |
335 | int *dev = per_cpu_ptr(&ipi_dev, cpu); |
336 | ||
337 | arc_request_percpu_irq(irq, cpu, do_IPI, "IPI Interrupt", dev); | |
7e512219 NC |
338 | |
339 | return 0; | |
41195d23 | 340 | } |