[deliverable/linux.git] / arch / arc / kernel / time.c

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * vineetg: Jan 1011
 *  -sched_clock( ) no longer jiffies based. Uses the same clocksource
 *   as gtod
 *
 * Rajeshwarr/Vineetg: Mar 2008
 *  -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
 *   for arch independent gettimeofday()
 *  -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
 *
 * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
 */

/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
 * Each can programmed to go from @count to @limit and optionally
 * interrupt when that happens.
 * A write to Control Register clears the Interrupt
 *
 * We've designated TIMER0 for events (clockevents)
 * while TIMER1 for free running (clocksource)
 *
 * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
 * which however is currently broken
 */

#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <asm/irq.h>
#include <asm/arcregs.h>

#include <asm/mcip.h>

/* Timer related Aux registers */
#define ARC_REG_TIMER0_LIMIT	0x23	/* timer 0 limit */
#define ARC_REG_TIMER0_CTRL	0x22	/* timer 0 control */
#define ARC_REG_TIMER0_CNT	0x21	/* timer 0 count */
#define ARC_REG_TIMER1_LIMIT	0x102	/* timer 1 limit */
#define ARC_REG_TIMER1_CTRL	0x101	/* timer 1 control */
#define ARC_REG_TIMER1_CNT	0x100	/* timer 1 count */

#define TIMER_CTRL_IE	(1 << 0) /* Interrupt when Count reaches limit */
#define TIMER_CTRL_NH	(1 << 1) /* Count only when CPU NOT halted */

#define ARC_TIMER_MAX	0xFFFFFFFF

static unsigned long arc_timer_freq;

static int noinline arc_get_timer_clk(struct device_node *node)
{
	struct clk *clk;
	int ret;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("timer missing clk");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("Couldn't enable parent clk\n");
		return ret;
	}

	arc_timer_freq = clk_get_rate(clk);

	return 0;
}

/********** Clock Source Device *********/

#ifdef CONFIG_ARC_HAS_GFRC

static cycle_t arc_read_gfrc(struct clocksource *cs)
{
	unsigned long flags;
	union {
#ifdef CONFIG_CPU_BIG_ENDIAN
		struct { u32 h, l; };
#else
		struct { u32 l, h; };
#endif
		cycle_t  full;
	} stamp;

	local_irq_save(flags);

	__mcip_cmd(CMD_GFRC_READ_LO, 0);
	stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);

	__mcip_cmd(CMD_GFRC_READ_HI, 0);
	stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);

	local_irq_restore(flags);

	return stamp.full;
}

static struct clocksource arc_counter_gfrc = {
	.name   = "ARConnect GFRC",
	.rating = 400,
	.read   = arc_read_gfrc,
	.mask   = CLOCKSOURCE_MASK(64),
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init arc_cs_setup_gfrc(struct device_node *node)
{
	int exists = cpuinfo_arc700[0].extn.gfrc;
	int ret;

	if (WARN(!exists, "Global-64-bit-Ctr clocksource not detected"))
		return -ENXIO;

	ret = arc_get_timer_clk(node);
	if (ret)
		return ret;

	return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
}
CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);

#endif

#ifdef CONFIG_ARC_HAS_RTC

#define AUX_RTC_CTRL	0x103
#define AUX_RTC_LOW	0x104
#define AUX_RTC_HIGH	0x105

static cycle_t arc_read_rtc(struct clocksource *cs)
{
	unsigned long status;
	union {
#ifdef CONFIG_CPU_BIG_ENDIAN
		struct { u32 high, low; };
#else
		struct { u32 low, high; };
#endif
		cycle_t  full;
	} stamp;


	__asm__ __volatile(
	"1:						\n"
	"	lr		%0, [AUX_RTC_LOW]	\n"
	"	lr		%1, [AUX_RTC_HIGH]	\n"
	"	lr		%2, [AUX_RTC_CTRL]	\n"
	"	bbit0.nt	%2, 31, 1b		\n"
	: "=r" (stamp.low), "=r" (stamp.high), "=r" (status));

	return stamp.full;
}

static struct clocksource arc_counter_rtc = {
	.name   = "ARCv2 RTC",
	.rating = 350,
	.read   = arc_read_rtc,
	.mask   = CLOCKSOURCE_MASK(64),
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init arc_cs_setup_rtc(struct device_node *node)
{
	int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc;
	int ret;

	if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected"))
		return -ENXIO;

	/* Local to CPU hence not usable in SMP */
	if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP"))
		return -EINVAL;

	ret = arc_get_timer_clk(node);
	if (ret)
		return ret;

	write_aux_reg(AUX_RTC_CTRL, 1);

	return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
}
CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);

#endif

/*
 * 32bit TIMER1 to keep counting monotonically and wraparound
 */

static cycle_t arc_read_timer1(struct clocksource *cs)
{
	return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
}

static struct clocksource arc_counter_timer1 = {
	.name   = "ARC Timer1",
	.rating = 300,
	.read   = arc_read_timer1,
	.mask   = CLOCKSOURCE_MASK(32),
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init arc_cs_setup_timer1(struct device_node *node)
{
	int ret;

	/* Local to CPU hence not usable in SMP */
	if (IS_ENABLED(CONFIG_SMP))
		return -EINVAL;

	ret = arc_get_timer_clk(node);
	if (ret)
		return ret;

	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
	write_aux_reg(ARC_REG_TIMER1_CNT, 0);
	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);

	return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
}

/********** Clock Event Device *********/

static int arc_timer_irq;

/*
 * Arm the timer to interrupt after @cycles
 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
 */
static void arc_timer_event_setup(unsigned int cycles)
{
	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
	write_aux_reg(ARC_REG_TIMER0_CNT, 0);	/* start from 0 */

	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
}


static int arc_clkevent_set_next_event(unsigned long delta,
				       struct clock_event_device *dev)
{
	arc_timer_event_setup(delta);
	return 0;
}

static int arc_clkevent_set_periodic(struct clock_event_device *dev)
{
	/*
	 * At X Hz, 1 sec = 1000ms -> X cycles;
	 *		      10ms -> X / 100 cycles
	 */
	arc_timer_event_setup(arc_timer_freq / HZ);
	return 0;
}

static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
	.name			= "ARC Timer0",
	.features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_PERIODIC,
	.rating			= 300,
	.set_next_event		= arc_clkevent_set_next_event,
	.set_state_periodic	= arc_clkevent_set_periodic,
};

static irqreturn_t timer_irq_handler(int irq, void *dev_id)
{
	/*
	 * Note that generic IRQ core could have passed @evt for @dev_id if
	 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
	 */
	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
	int irq_reenable = clockevent_state_periodic(evt);

	/*
	 * Any write to CTRL reg ACks the interrupt, we rewrite the
	 * Count when [N]ot [H]alted bit.
	 * And re-arm it if perioid by [I]nterrupt [E]nable bit
	 */
	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static int arc_timer_cpu_notify(struct notifier_block *self,
				unsigned long action, void *hcpu)
{
	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);

	evt->cpumask = cpumask_of(smp_processor_id());

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		clockevents_config_and_register(evt, arc_timer_freq,
						0, ULONG_MAX);
		enable_percpu_irq(arc_timer_irq, 0);
		break;
	case CPU_DYING:
		disable_percpu_irq(arc_timer_irq);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block arc_timer_cpu_nb = {
	.notifier_call = arc_timer_cpu_notify,
};

/*
 * clockevent setup for boot CPU
 */
static int __init arc_clockevent_setup(struct device_node *node)
{
	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
	int ret;

	ret = register_cpu_notifier(&arc_timer_cpu_nb);
	if (ret) {
		pr_err("Failed to register cpu notifier");
		return ret;
	}

	arc_timer_irq = irq_of_parse_and_map(node, 0);
	if (arc_timer_irq <= 0) {
		pr_err("clockevent: missing irq");
		return -EINVAL;
	}

	ret = arc_get_timer_clk(node);
	if (ret) {
		pr_err("clockevent: missing clk");
		return ret;
	}

	evt->irq = arc_timer_irq;
	evt->cpumask = cpumask_of(smp_processor_id());
	clockevents_config_and_register(evt, arc_timer_freq,
					0, ARC_TIMER_MAX);

	/* Needs apriori irq_set_percpu_devid() done in intc map function */
	ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
				 "Timer0 (per-cpu-tick)", evt);
	if (ret) {
		pr_err("clockevent: unable to request irq\n");
		return ret;
	}

	enable_percpu_irq(arc_timer_irq, 0);

	return 0;
}

static int __init arc_of_timer_init(struct device_node *np)
{
	static int init_count = 0;
	int ret;

	if (!init_count) {
		init_count = 1;
		ret = arc_clockevent_setup(np);
	} else {
		ret = arc_cs_setup_timer1(np);
	}

	return ret;
}
CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);

/*
 * Called from start_kernel() - boot CPU only
 */
void __init time_init(void)
{
	of_clk_init(NULL);
	clocksource_probe();
}
Commit	Line	Data
d8005e6b VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* vineetg: Jan 1011
	9	* -sched_clock( ) no longer jiffies based. Uses the same clocksource
	10	* as gtod
	11	*
	12	* Rajeshwarr/Vineetg: Mar 2008
	13	* -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
	14	* for arch independent gettimeofday()
	15	* -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
	16	*
	17	* Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
	18	*/
	19
	20	/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
	21	* Each can programmed to go from @count to @limit and optionally
	22	* interrupt when that happens.
	23	* A write to Control Register clears the Interrupt
	24	*
	25	* We've designated TIMER0 for events (clockevents)
	26	* while TIMER1 for free running (clocksource)
	27	*
	28	* Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
565a9b49	29	* which however is currently broken
d8005e6b VG	30	*/
d8005e6b VG	31
d8005e6b	32	#include <linux/interrupt.h>
69fbd098 NC	33	#include <linux/clk.h>
69fbd098 NC	34	#include <linux/clk-provider.h>
d8005e6b VG	35	#include <linux/clocksource.h>
d8005e6b VG	36	#include <linux/clockchips.h>
eec3c58e	37	#include <linux/cpu.h>
77c8d0d6 VG	38	#include <linux/of.h>
77c8d0d6 VG	39	#include <linux/of_irq.h>
d8005e6b VG	40	#include <asm/irq.h>
d8005e6b VG	41	#include <asm/arcregs.h>
d8005e6b	42
72d72880 VG	43	#include <asm/mcip.h>
72d72880 VG	44
da1677b0 VG	45	/* Timer related Aux registers */
	46	#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
	47	#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
	48	#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
	49	#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
	50	#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
	51	#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
	52
7423cc0c AB	53	#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
7423cc0c AB	54	#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
da1677b0	55
d8005e6b VG	56	#define ARC_TIMER_MAX 0xFFFFFFFF
d8005e6b VG	57
77c8d0d6 VG	58	static unsigned long arc_timer_freq;
	59
	60	static int noinline arc_get_timer_clk(struct device_node *node)
	61	{
	62	struct clk *clk;
	63	int ret;
	64
	65	clk = of_clk_get(node, 0);
	66	if (IS_ERR(clk)) {
	67	pr_err("timer missing clk");
	68	return PTR_ERR(clk);
	69	}
	70
	71	ret = clk_prepare_enable(clk);
	72	if (ret) {
	73	pr_err("Couldn't enable parent clk\n");
	74	return ret;
	75	}
	76
	77	arc_timer_freq = clk_get_rate(clk);
	78
	79	return 0;
	80	}
	81
d8005e6b VG	82	/******** Clock Source Device *******/
d8005e6b VG	83
d584f0fb	84	#ifdef CONFIG_ARC_HAS_GFRC
72d72880	85
e608b53e	86	static cycle_t arc_read_gfrc(struct clocksource *cs)
72d72880 VG	87	{
	88	unsigned long flags;
	89	union {
	90	#ifdef CONFIG_CPU_BIG_ENDIAN
	91	struct { u32 h, l; };
	92	#else
	93	struct { u32 l, h; };
	94	#endif
	95	cycle_t full;
	96	} stamp;
	97
	98	local_irq_save(flags);
	99
d584f0fb	100	__mcip_cmd(CMD_GFRC_READ_LO, 0);
72d72880 VG	101	stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
72d72880 VG	102
d584f0fb	103	__mcip_cmd(CMD_GFRC_READ_HI, 0);
72d72880 VG	104	stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
	105
	106	local_irq_restore(flags);
	107
	108	return stamp.full;
	109	}
	110
e608b53e	111	static struct clocksource arc_counter_gfrc = {
d584f0fb	112	.name = "ARConnect GFRC",
72d72880	113	.rating = 400,
e608b53e	114	.read = arc_read_gfrc,
72d72880 VG	115	.mask = CLOCKSOURCE_MASK(64),
	116	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	117	};
	118
43d75604	119	static int __init arc_cs_setup_gfrc(struct device_node *node)
e608b53e VG	120	{
	121	int exists = cpuinfo_arc700[0].extn.gfrc;
	122	int ret;
	123
	124	if (WARN(!exists, "Global-64-bit-Ctr clocksource not detected"))
43d75604	125	return -ENXIO;
e608b53e VG	126
	127	ret = arc_get_timer_clk(node);
	128	if (ret)
43d75604	129	return ret;
e608b53e	130
43d75604	131	return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
e608b53e	132	}
177cf6e5	133	CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
e608b53e VG	134
e608b53e VG	135	#endif
72d72880	136
aa93e8ef VG	137	#ifdef CONFIG_ARC_HAS_RTC
	138
	139	#define AUX_RTC_CTRL 0x103
	140	#define AUX_RTC_LOW 0x104
	141	#define AUX_RTC_HIGH 0x105
	142
e608b53e	143	static cycle_t arc_read_rtc(struct clocksource *cs)
aa93e8ef VG	144	{
	145	unsigned long status;
	146	union {
	147	#ifdef CONFIG_CPU_BIG_ENDIAN
	148	struct { u32 high, low; };
	149	#else
	150	struct { u32 low, high; };
	151	#endif
	152	cycle_t full;
	153	} stamp;
	154
	155
	156	__asm__ __volatile(
	157	"1: \n"
	158	" lr %0, [AUX_RTC_LOW] \n"
	159	" lr %1, [AUX_RTC_HIGH] \n"
	160	" lr %2, [AUX_RTC_CTRL] \n"
	161	" bbit0.nt %2, 31, 1b \n"
	162	: "=r" (stamp.low), "=r" (stamp.high), "=r" (status));
	163
	164	return stamp.full;
	165	}
	166
e608b53e	167	static struct clocksource arc_counter_rtc = {
aa93e8ef VG	168	.name = "ARCv2 RTC",
aa93e8ef VG	169	.rating = 350,
e608b53e	170	.read = arc_read_rtc,
aa93e8ef VG	171	.mask = CLOCKSOURCE_MASK(64),
	172	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	173	};
	174
43d75604	175	static int __init arc_cs_setup_rtc(struct device_node *node)
d8005e6b	176	{
e608b53e VG	177	int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc;
	178	int ret;
	179
	180	if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected"))
43d75604	181	return -ENXIO;
e608b53e VG	182
	183	/* Local to CPU hence not usable in SMP */
	184	if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP"))
43d75604	185	return -EINVAL;
e608b53e VG	186
	187	ret = arc_get_timer_clk(node);
	188	if (ret)
43d75604	189	return ret;
d8005e6b	190
e608b53e VG	191	write_aux_reg(AUX_RTC_CTRL, 1);
e608b53e VG	192
43d75604	193	return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
d8005e6b	194	}
177cf6e5	195	CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
e608b53e VG	196
e608b53e VG	197	#endif
d8005e6b	198
e608b53e VG	199	/*
	200	* 32bit TIMER1 to keep counting monotonically and wraparound
	201	*/
	202
	203	static cycle_t arc_read_timer1(struct clocksource *cs)
d8005e6b VG	204	{
	205	return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
	206	}
	207
e608b53e	208	static struct clocksource arc_counter_timer1 = {
d8005e6b VG	209	.name = "ARC Timer1",
d8005e6b VG	210	.rating = 300,
e608b53e	211	.read = arc_read_timer1,
d8005e6b VG	212	.mask = CLOCKSOURCE_MASK(32),
	213	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	214	};
	215
43d75604	216	static int __init arc_cs_setup_timer1(struct device_node *node)
e608b53e VG	217	{
	218	int ret;
	219
	220	/* Local to CPU hence not usable in SMP */
	221	if (IS_ENABLED(CONFIG_SMP))
43d75604	222	return -EINVAL;
e608b53e VG	223
	224	ret = arc_get_timer_clk(node);
	225	if (ret)
43d75604	226	return ret;
e608b53e VG	227
	228	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
	229	write_aux_reg(ARC_REG_TIMER1_CNT, 0);
	230	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
	231
43d75604	232	return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
e608b53e	233	}
aa93e8ef	234
d8005e6b VG	235	/******** Clock Event Device *******/
d8005e6b VG	236
77c8d0d6	237	static int arc_timer_irq;
eec3c58e	238
d8005e6b	239	/*
c9a98e18	240	* Arm the timer to interrupt after @cycles
d8005e6b VG	241	* The distinction for oneshot/periodic is done in arc_event_timer_ack() below
d8005e6b VG	242	*/
c9a98e18	243	static void arc_timer_event_setup(unsigned int cycles)
d8005e6b	244	{
c9a98e18	245	write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
d8005e6b VG	246	write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
	247
	248	write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE \| TIMER_CTRL_NH);
	249	}
	250
d8005e6b VG	251
	252	static int arc_clkevent_set_next_event(unsigned long delta,
	253	struct clock_event_device *dev)
	254	{
	255	arc_timer_event_setup(delta);
	256	return 0;
	257	}
	258
aeec6cda	259	static int arc_clkevent_set_periodic(struct clock_event_device *dev)
d8005e6b	260	{
aeec6cda VK	261	/*
	262	* At X Hz, 1 sec = 1000ms -> X cycles;
	263	* 10ms -> X / 100 cycles
	264	*/
77c8d0d6	265	arc_timer_event_setup(arc_timer_freq / HZ);
aeec6cda	266	return 0;
d8005e6b VG	267	}
	268
	269	static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
aeec6cda VK	270	.name = "ARC Timer0",
	271	.features = CLOCK_EVT_FEAT_ONESHOT \|
	272	CLOCK_EVT_FEAT_PERIODIC,
	273	.rating = 300,
aeec6cda VK	274	.set_next_event = arc_clkevent_set_next_event,
aeec6cda VK	275	.set_state_periodic = arc_clkevent_set_periodic,
d8005e6b VG	276	};
	277
	278	static irqreturn_t timer_irq_handler(int irq, void *dev_id)
	279	{
f8b34c3f VG	280	/*
	281	* Note that generic IRQ core could have passed @evt for @dev_id if
	282	* irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
	283	*/
	284	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
aeec6cda	285	int irq_reenable = clockevent_state_periodic(evt);
f8b34c3f VG	286
	287	/*
	288	* Any write to CTRL reg ACks the interrupt, we rewrite the
	289	* Count when [N]ot [H]alted bit.
	290	* And re-arm it if perioid by [I]nterrupt [E]nable bit
	291	*/
	292	write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable \| TIMER_CTRL_NH);
	293
	294	evt->event_handler(evt);
d8005e6b	295
d8005e6b VG	296	return IRQ_HANDLED;
	297	}
	298
eec3c58e NC	299	static int arc_timer_cpu_notify(struct notifier_block *self,
	300	unsigned long action, void *hcpu)
	301	{
	302	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
	303
	304	evt->cpumask = cpumask_of(smp_processor_id());
	305
	306	switch (action & ~CPU_TASKS_FROZEN) {
	307	case CPU_STARTING:
77c8d0d6	308	clockevents_config_and_register(evt, arc_timer_freq,
eec3c58e NC	309	0, ULONG_MAX);
	310	enable_percpu_irq(arc_timer_irq, 0);
	311	break;
	312	case CPU_DYING:
	313	disable_percpu_irq(arc_timer_irq);
	314	break;
	315	}
	316
	317	return NOTIFY_OK;
	318	}
	319
	320	static struct notifier_block arc_timer_cpu_nb = {
	321	.notifier_call = arc_timer_cpu_notify,
	322	};
	323
d8005e6b	324	/*
eec3c58e	325	* clockevent setup for boot CPU
d8005e6b	326	*/
43d75604	327	static int __init arc_clockevent_setup(struct device_node *node)
d8005e6b	328	{
2d4899f6	329	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
eec3c58e	330	int ret;
d8005e6b	331
43d75604 DL	332	ret = register_cpu_notifier(&arc_timer_cpu_nb);
	333	if (ret) {
	334	pr_err("Failed to register cpu notifier");
	335	return ret;
	336	}
eec3c58e	337
77c8d0d6	338	arc_timer_irq = irq_of_parse_and_map(node, 0);
43d75604 DL	339	if (arc_timer_irq <= 0) {
	340	pr_err("clockevent: missing irq");
	341	return -EINVAL;
	342	}
77c8d0d6 VG	343
77c8d0d6 VG	344	ret = arc_get_timer_clk(node);
43d75604 DL	345	if (ret) {
	346	pr_err("clockevent: missing clk");
	347	return ret;
	348	}
77c8d0d6 VG	349
77c8d0d6 VG	350	evt->irq = arc_timer_irq;
eec3c58e	351	evt->cpumask = cpumask_of(smp_processor_id());
77c8d0d6	352	clockevents_config_and_register(evt, arc_timer_freq,
55c2e262	353	0, ARC_TIMER_MAX);
d8005e6b	354
eec3c58e NC	355	/* Needs apriori irq_set_percpu_devid() done in intc map function */
	356	ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
	357	"Timer0 (per-cpu-tick)", evt);
43d75604 DL	358	if (ret) {
	359	pr_err("clockevent: unable to request irq\n");
	360	return ret;
	361	}
56957940	362
eec3c58e	363	enable_percpu_irq(arc_timer_irq, 0);
43d75604 DL	364
43d75604 DL	365	return 0;
d8005e6b	366	}
e608b53e	367
43d75604	368	static int __init arc_of_timer_init(struct device_node *np)
e608b53e VG	369	{
e608b53e VG	370	static int init_count = 0;
43d75604	371	int ret;
e608b53e VG	372
	373	if (!init_count) {
	374	init_count = 1;
43d75604	375	ret = arc_clockevent_setup(np);
e608b53e	376	} else {
43d75604	377	ret = arc_cs_setup_timer1(np);
e608b53e	378	}
43d75604 DL	379
43d75604 DL	380	return ret;
e608b53e	381	}
177cf6e5	382	CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
d8005e6b VG	383
	384	/*
	385	* Called from start_kernel() - boot CPU only
d8005e6b VG	386	*/
	387	void __init time_init(void)
	388	{
69fbd098 NC	389	of_clk_init(NULL);
69fbd098 NC	390	clocksource_probe();
d8005e6b	391	}