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d8005e6b VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * vineetg: Jan 1011 | |
9 | * -sched_clock( ) no longer jiffies based. Uses the same clocksource | |
10 | * as gtod | |
11 | * | |
12 | * Rajeshwarr/Vineetg: Mar 2008 | |
13 | * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code) | |
14 | * for arch independent gettimeofday() | |
15 | * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers | |
16 | * | |
17 | * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c | |
18 | */ | |
19 | ||
20 | /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1 | |
21 | * Each can programmed to go from @count to @limit and optionally | |
22 | * interrupt when that happens. | |
23 | * A write to Control Register clears the Interrupt | |
24 | * | |
25 | * We've designated TIMER0 for events (clockevents) | |
26 | * while TIMER1 for free running (clocksource) | |
27 | * | |
28 | * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1 | |
29 | */ | |
30 | ||
31 | #include <linux/spinlock.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/kernel.h> | |
d8005e6b VG |
36 | #include <linux/time.h> |
37 | #include <linux/init.h> | |
38 | #include <linux/timex.h> | |
39 | #include <linux/profile.h> | |
40 | #include <linux/clocksource.h> | |
41 | #include <linux/clockchips.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/arcregs.h> | |
44 | #include <asm/clk.h> | |
03a6d28c | 45 | #include <asm/mach_desc.h> |
d8005e6b | 46 | |
da1677b0 VG |
47 | /* Timer related Aux registers */ |
48 | #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ | |
49 | #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ | |
50 | #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ | |
51 | #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ | |
52 | #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ | |
53 | #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ | |
54 | ||
55 | #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */ | |
56 | #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ | |
57 | ||
d8005e6b VG |
58 | #define ARC_TIMER_MAX 0xFFFFFFFF |
59 | ||
60 | /********** Clock Source Device *********/ | |
61 | ||
62 | #ifdef CONFIG_ARC_HAS_RTSC | |
63 | ||
ce759956 | 64 | int arc_counter_setup(void) |
d8005e6b VG |
65 | { |
66 | /* RTSC insn taps into cpu clk, needs no setup */ | |
67 | ||
68 | /* For SMP, only allowed if cross-core-sync, hence usable as cs */ | |
69 | return 1; | |
70 | } | |
71 | ||
72 | static cycle_t arc_counter_read(struct clocksource *cs) | |
73 | { | |
74 | unsigned long flags; | |
75 | union { | |
76 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
77 | struct { u32 high, low; }; | |
78 | #else | |
79 | struct { u32 low, high; }; | |
80 | #endif | |
81 | cycle_t full; | |
82 | } stamp; | |
83 | ||
84 | flags = arch_local_irq_save(); | |
85 | ||
86 | __asm__ __volatile( | |
87 | " .extCoreRegister tsch, 58, r, cannot_shortcut \n" | |
88 | " rtsc %0, 0 \n" | |
1e266629 | 89 | " mov %1, 0 \n" |
d8005e6b VG |
90 | : "=r" (stamp.low), "=r" (stamp.high)); |
91 | ||
92 | arch_local_irq_restore(flags); | |
93 | ||
94 | return stamp.full; | |
95 | } | |
96 | ||
97 | static struct clocksource arc_counter = { | |
98 | .name = "ARC RTSC", | |
99 | .rating = 300, | |
100 | .read = arc_counter_read, | |
1e266629 | 101 | .mask = CLOCKSOURCE_MASK(32), |
d8005e6b VG |
102 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
103 | }; | |
104 | ||
105 | #else /* !CONFIG_ARC_HAS_RTSC */ | |
106 | ||
107 | static bool is_usable_as_clocksource(void) | |
108 | { | |
109 | #ifdef CONFIG_SMP | |
110 | return 0; | |
111 | #else | |
112 | return 1; | |
113 | #endif | |
114 | } | |
115 | ||
116 | /* | |
117 | * set 32bit TIMER1 to keep counting monotonically and wraparound | |
118 | */ | |
ce759956 | 119 | int arc_counter_setup(void) |
d8005e6b VG |
120 | { |
121 | write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); | |
122 | write_aux_reg(ARC_REG_TIMER1_CNT, 0); | |
123 | write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); | |
124 | ||
125 | return is_usable_as_clocksource(); | |
126 | } | |
127 | ||
128 | static cycle_t arc_counter_read(struct clocksource *cs) | |
129 | { | |
130 | return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); | |
131 | } | |
132 | ||
133 | static struct clocksource arc_counter = { | |
134 | .name = "ARC Timer1", | |
135 | .rating = 300, | |
136 | .read = arc_counter_read, | |
137 | .mask = CLOCKSOURCE_MASK(32), | |
138 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
139 | }; | |
140 | ||
141 | #endif | |
142 | ||
143 | /********** Clock Event Device *********/ | |
144 | ||
145 | /* | |
146 | * Arm the timer to interrupt after @limit cycles | |
147 | * The distinction for oneshot/periodic is done in arc_event_timer_ack() below | |
148 | */ | |
149 | static void arc_timer_event_setup(unsigned int limit) | |
150 | { | |
151 | write_aux_reg(ARC_REG_TIMER0_LIMIT, limit); | |
152 | write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ | |
153 | ||
154 | write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); | |
155 | } | |
156 | ||
157 | /* | |
158 | * Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic) | |
159 | * -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted) | |
160 | * -Rearming is done by setting the IE bit | |
161 | * | |
162 | * Small optimisation: Normal code would have been | |
163 | * if (irq_reenable) | |
164 | * CTRL_REG = (IE | NH); | |
165 | * else | |
166 | * CTRL_REG = NH; | |
167 | * However since IE is BIT0 we can fold the branch | |
168 | */ | |
169 | static void arc_timer_event_ack(unsigned int irq_reenable) | |
170 | { | |
171 | write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); | |
172 | } | |
173 | ||
174 | static int arc_clkevent_set_next_event(unsigned long delta, | |
175 | struct clock_event_device *dev) | |
176 | { | |
177 | arc_timer_event_setup(delta); | |
178 | return 0; | |
179 | } | |
180 | ||
181 | static void arc_clkevent_set_mode(enum clock_event_mode mode, | |
182 | struct clock_event_device *dev) | |
183 | { | |
184 | switch (mode) { | |
185 | case CLOCK_EVT_MODE_PERIODIC: | |
186 | arc_timer_event_setup(arc_get_core_freq() / HZ); | |
187 | break; | |
188 | case CLOCK_EVT_MODE_ONESHOT: | |
189 | break; | |
190 | default: | |
191 | break; | |
192 | } | |
193 | ||
194 | return; | |
195 | } | |
196 | ||
197 | static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { | |
198 | .name = "ARC Timer0", | |
199 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | |
200 | .mode = CLOCK_EVT_MODE_UNUSED, | |
201 | .rating = 300, | |
202 | .irq = TIMER0_IRQ, /* hardwired, no need for resources */ | |
203 | .set_next_event = arc_clkevent_set_next_event, | |
204 | .set_mode = arc_clkevent_set_mode, | |
205 | }; | |
206 | ||
207 | static irqreturn_t timer_irq_handler(int irq, void *dev_id) | |
208 | { | |
209 | struct clock_event_device *clk = &__get_cpu_var(arc_clockevent_device); | |
210 | ||
211 | arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC); | |
212 | clk->event_handler(clk); | |
213 | return IRQ_HANDLED; | |
214 | } | |
215 | ||
216 | static struct irqaction arc_timer_irq = { | |
217 | .name = "Timer0 (clock-evt-dev)", | |
218 | .flags = IRQF_TIMER | IRQF_PERCPU, | |
219 | .handler = timer_irq_handler, | |
220 | }; | |
221 | ||
222 | /* | |
223 | * Setup the local event timer for @cpu | |
224 | * N.B. weak so that some exotic ARC SoCs can completely override it | |
225 | */ | |
ce759956 | 226 | void __attribute__((weak)) arc_local_timer_setup(unsigned int cpu) |
d8005e6b VG |
227 | { |
228 | struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu); | |
229 | ||
d8005e6b | 230 | clk->cpumask = cpumask_of(cpu); |
55c2e262 UKK |
231 | clockevents_config_and_register(clk, arc_get_core_freq(), |
232 | 0, ARC_TIMER_MAX); | |
d8005e6b VG |
233 | |
234 | /* | |
235 | * setup the per-cpu timer IRQ handler - for all cpus | |
236 | * For non boot CPU explicitly unmask at intc | |
237 | * setup_irq() -> .. -> irq_startup() already does this on boot-cpu | |
238 | */ | |
239 | if (!cpu) | |
240 | setup_irq(TIMER0_IRQ, &arc_timer_irq); | |
241 | else | |
242 | arch_unmask_irq(TIMER0_IRQ); | |
243 | } | |
244 | ||
245 | /* | |
246 | * Called from start_kernel() - boot CPU only | |
247 | * | |
248 | * -Sets up h/w timers as applicable on boot cpu | |
249 | * -Also sets up any global state needed for timer subsystem: | |
250 | * - for "counting" timer, registers a clocksource, usable across CPUs | |
251 | * (provided that underlying counter h/w is synchronized across cores) | |
252 | * - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic) | |
253 | */ | |
254 | void __init time_init(void) | |
255 | { | |
256 | /* | |
257 | * sets up the timekeeping free-flowing counter which also returns | |
258 | * whether the counter is usable as clocksource | |
259 | */ | |
260 | if (arc_counter_setup()) | |
261 | /* | |
262 | * CLK upto 4.29 GHz can be safely represented in 32 bits | |
263 | * because Max 32 bit number is 4,294,967,295 | |
264 | */ | |
265 | clocksource_register_hz(&arc_counter, arc_get_core_freq()); | |
266 | ||
267 | /* sets up the periodic event timer */ | |
268 | arc_local_timer_setup(smp_processor_id()); | |
03a6d28c VG |
269 | |
270 | if (machine_desc->init_time) | |
271 | machine_desc->init_time(); | |
d8005e6b | 272 | } |