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1162b070 VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * DMA Coherent API Notes | |
11 | * | |
12 | * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is | |
13 | * implemented by accessintg it using a kernel virtual address, with | |
14 | * Cache bit off in the TLB entry. | |
15 | * | |
16 | * The default DMA address == Phy address which is 0x8000_0000 based. | |
1162b070 VG |
17 | */ |
18 | ||
19 | #include <linux/dma-mapping.h> | |
f2b0b25a | 20 | #include <asm/cache.h> |
1162b070 VG |
21 | #include <asm/cacheflush.h> |
22 | ||
052c96db CH |
23 | |
24 | static void *arc_dma_alloc(struct device *dev, size_t size, | |
25 | dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs) | |
1162b070 | 26 | { |
d98a15a5 VG |
27 | unsigned long order = get_order(size); |
28 | struct page *page; | |
29 | phys_addr_t paddr; | |
30 | void *kvaddr; | |
6b700393 | 31 | int need_coh = 1, need_kvaddr = 0; |
1162b070 | 32 | |
d98a15a5 VG |
33 | page = alloc_pages(gfp, order); |
34 | if (!page) | |
1162b070 VG |
35 | return NULL; |
36 | ||
f2b0b25a AB |
37 | /* |
38 | * IOC relies on all data (even coherent DMA data) being in cache | |
39 | * Thus allocate normal cached memory | |
40 | * | |
41 | * The gains with IOC are two pronged: | |
6b700393 | 42 | * -For streaming data, elides need for cache maintenance, saving |
f2b0b25a AB |
43 | * cycles in flush code, and bus bandwidth as all the lines of a |
44 | * buffer need to be flushed out to memory | |
45 | * -For coherent data, Read/Write to buffers terminate early in cache | |
46 | * (vs. always going to memory - thus are faster) | |
47 | */ | |
052c96db CH |
48 | if ((is_isa_arcv2() && ioc_exists) || |
49 | dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) | |
6b700393 VG |
50 | need_coh = 0; |
51 | ||
52 | /* | |
53 | * - A coherent buffer needs MMU mapping to enforce non-cachability | |
54 | * - A highmem page needs a virtual handle (hence MMU mapping) | |
55 | * independent of cachability | |
56 | */ | |
57 | if (PageHighMem(page) || need_coh) | |
58 | need_kvaddr = 1; | |
59 | ||
60 | /* This is linear addr (0x8000_0000 based) */ | |
61 | paddr = page_to_phys(page); | |
62 | ||
63 | /* For now bus address is exactly same as paddr */ | |
64 | *dma_handle = paddr; | |
1162b070 VG |
65 | |
66 | /* This is kernel Virtual address (0x7000_0000 based) */ | |
6b700393 VG |
67 | if (need_kvaddr) { |
68 | kvaddr = ioremap_nocache((unsigned long)paddr, size); | |
69 | if (kvaddr == NULL) { | |
70 | __free_pages(page, order); | |
71 | return NULL; | |
72 | } | |
73 | } else { | |
74 | kvaddr = (void *)paddr; | |
d98a15a5 | 75 | } |
1162b070 | 76 | |
795f4558 VG |
77 | /* |
78 | * Evict any existing L1 and/or L2 lines for the backing page | |
79 | * in case it was used earlier as a normal "cached" page. | |
80 | * Yeah this bit us - STAR 9000898266 | |
81 | * | |
82 | * Although core does call flush_cache_vmap(), it gets kvaddr hence | |
83 | * can't be used to efficiently flush L1 and/or L2 which need paddr | |
84 | * Currently flush_cache_vmap nukes the L1 cache completely which | |
85 | * will be optimized as a separate commit | |
86 | */ | |
6b700393 VG |
87 | if (need_coh) |
88 | dma_cache_wback_inv((unsigned long)paddr, size); | |
795f4558 | 89 | |
1162b070 VG |
90 | return kvaddr; |
91 | } | |
1162b070 | 92 | |
052c96db CH |
93 | static void arc_dma_free(struct device *dev, size_t size, void *vaddr, |
94 | dma_addr_t dma_handle, struct dma_attrs *attrs) | |
1162b070 | 95 | { |
d98a15a5 | 96 | struct page *page = virt_to_page(dma_handle); |
6b700393 VG |
97 | int is_non_coh = 1; |
98 | ||
99 | is_non_coh = dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs) || | |
100 | (is_isa_arcv2() && ioc_exists); | |
d98a15a5 | 101 | |
6b700393 | 102 | if (PageHighMem(page) || !is_non_coh) |
052c96db | 103 | iounmap((void __force __iomem *)vaddr); |
1162b070 | 104 | |
d98a15a5 | 105 | __free_pages(page, get_order(size)); |
1162b070 | 106 | } |
1162b070 VG |
107 | |
108 | /* | |
052c96db CH |
109 | * streaming DMA Mapping API... |
110 | * CPU accesses page via normal paddr, thus needs to explicitly made | |
111 | * consistent before each use | |
1162b070 | 112 | */ |
052c96db CH |
113 | static void _dma_cache_sync(unsigned long paddr, size_t size, |
114 | enum dma_data_direction dir) | |
115 | { | |
116 | switch (dir) { | |
117 | case DMA_FROM_DEVICE: | |
118 | dma_cache_inv(paddr, size); | |
119 | break; | |
120 | case DMA_TO_DEVICE: | |
121 | dma_cache_wback(paddr, size); | |
122 | break; | |
123 | case DMA_BIDIRECTIONAL: | |
124 | dma_cache_wback_inv(paddr, size); | |
125 | break; | |
126 | default: | |
127 | pr_err("Invalid DMA dir [%d] for OP @ %lx\n", dir, paddr); | |
128 | } | |
129 | } | |
130 | ||
131 | static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page, | |
132 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
133 | struct dma_attrs *attrs) | |
134 | { | |
135 | unsigned long paddr = page_to_phys(page) + offset; | |
136 | _dma_cache_sync(paddr, size, dir); | |
137 | return (dma_addr_t)paddr; | |
138 | } | |
139 | ||
140 | static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg, | |
141 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
142 | { | |
143 | struct scatterlist *s; | |
144 | int i; | |
145 | ||
146 | for_each_sg(sg, s, nents, i) | |
147 | s->dma_address = dma_map_page(dev, sg_page(s), s->offset, | |
148 | s->length, dir); | |
149 | ||
150 | return nents; | |
151 | } | |
152 | ||
153 | static void arc_dma_sync_single_for_cpu(struct device *dev, | |
154 | dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) | |
155 | { | |
156 | _dma_cache_sync(dma_handle, size, DMA_FROM_DEVICE); | |
157 | } | |
158 | ||
159 | static void arc_dma_sync_single_for_device(struct device *dev, | |
160 | dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) | |
1162b070 | 161 | { |
052c96db | 162 | _dma_cache_sync(dma_handle, size, DMA_TO_DEVICE); |
1162b070 | 163 | } |
052c96db CH |
164 | |
165 | static void arc_dma_sync_sg_for_cpu(struct device *dev, | |
166 | struct scatterlist *sglist, int nelems, | |
167 | enum dma_data_direction dir) | |
168 | { | |
169 | int i; | |
170 | struct scatterlist *sg; | |
171 | ||
172 | for_each_sg(sglist, sg, nelems, i) | |
173 | _dma_cache_sync((unsigned int)sg_virt(sg), sg->length, dir); | |
174 | } | |
175 | ||
176 | static void arc_dma_sync_sg_for_device(struct device *dev, | |
177 | struct scatterlist *sglist, int nelems, | |
178 | enum dma_data_direction dir) | |
179 | { | |
180 | int i; | |
181 | struct scatterlist *sg; | |
182 | ||
183 | for_each_sg(sglist, sg, nelems, i) | |
184 | _dma_cache_sync((unsigned int)sg_virt(sg), sg->length, dir); | |
185 | } | |
186 | ||
187 | static int arc_dma_supported(struct device *dev, u64 dma_mask) | |
188 | { | |
189 | /* Support 32 bit DMA mask exclusively */ | |
190 | return dma_mask == DMA_BIT_MASK(32); | |
191 | } | |
192 | ||
193 | struct dma_map_ops arc_dma_ops = { | |
194 | .alloc = arc_dma_alloc, | |
195 | .free = arc_dma_free, | |
196 | .map_page = arc_dma_map_page, | |
197 | .map_sg = arc_dma_map_sg, | |
198 | .sync_single_for_device = arc_dma_sync_single_for_device, | |
199 | .sync_single_for_cpu = arc_dma_sync_single_for_cpu, | |
200 | .sync_sg_for_cpu = arc_dma_sync_sg_for_cpu, | |
201 | .sync_sg_for_device = arc_dma_sync_sg_for_device, | |
202 | .dma_supported = arc_dma_supported, | |
203 | }; | |
204 | EXPORT_SYMBOL(arc_dma_ops); |