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cc562d2e VG |
1 | /* |
2 | * TLB Exception Handling for ARC | |
3 | * | |
4 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Vineetg: April 2011 : | |
11 | * -MMU v1: moved out legacy code into a seperate file | |
12 | * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, | |
13 | * helps avoid a shift when preparing PD0 from PTE | |
14 | * | |
15 | * Vineetg: July 2009 | |
16 | * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB | |
17 | * entry, so that it doesn't knock out it's I-TLB entry | |
18 | * -Some more fine tuning: | |
19 | * bmsk instead of add, asl.cc instead of branch, delay slot utilise etc | |
20 | * | |
21 | * Vineetg: July 2009 | |
22 | * -Practically rewrote the I/D TLB Miss handlers | |
23 | * Now 40 and 135 instructions a peice as compared to 131 and 449 resp. | |
24 | * Hence Leaner by 1.5 K | |
25 | * Used Conditional arithmetic to replace excessive branching | |
26 | * Also used short instructions wherever possible | |
27 | * | |
28 | * Vineetg: Aug 13th 2008 | |
29 | * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing | |
30 | * more information in case of a Fatality | |
31 | * | |
32 | * Vineetg: March 25th Bug #92690 | |
33 | * -Added Debug Code to check if sw-ASID == hw-ASID | |
34 | ||
35 | * Rahul Trivedi, Amit Bhor: Codito Technologies 2004 | |
36 | */ | |
37 | ||
cc562d2e VG |
38 | #include <linux/linkage.h> |
39 | #include <asm/entry.h> | |
da1677b0 | 40 | #include <asm/mmu.h> |
cc562d2e VG |
41 | #include <asm/pgtable.h> |
42 | #include <asm/arcregs.h> | |
43 | #include <asm/cache.h> | |
44 | #include <asm/processor.h> | |
cc562d2e | 45 | #include <asm/tlb-mmu1.h> |
cc562d2e | 46 | |
4b06ff35 VG |
47 | ;----------------------------------------------------------------- |
48 | ; ARC700 Exception Handling doesn't auto-switch stack and it only provides | |
49 | ; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0" | |
50 | ; | |
51 | ; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a | |
52 | ; "global" is used to free-up FIRST core reg to be able to code the rest of | |
53 | ; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe). | |
54 | ; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3 | |
55 | ; need to be saved as well by extending the "global" to be 4 words. Hence | |
56 | ; ".size ex_saved_reg1, 16" | |
57 | ; [All of this dance is to avoid stack switching for each TLB Miss, since we | |
58 | ; only need to save only a handful of regs, as opposed to complete reg file] | |
59 | ; | |
60 | ; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST | |
61 | ; core reg as it will not be SMP safe. | |
62 | ; Thus scratch AUX reg is used (and no longer used to cache task PGD). | |
63 | ; To save the rest of 3 regs - per cpu, the global is made "per-cpu". | |
64 | ; Epilogue thus has to locate the "per-cpu" storage for regs. | |
65 | ; To avoid cache line bouncing the per-cpu global is aligned/sized per | |
66 | ; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence | |
67 | ; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)" | |
68 | ||
69 | ; As simple as that.... | |
cc562d2e VG |
70 | ;-------------------------------------------------------------------------- |
71 | ||
4b06ff35 | 72 | ; scratch memory to save [r0-r3] used to code TLB refill Handler |
8b5850f8 | 73 | ARCFP_DATA ex_saved_reg1 |
4b06ff35 | 74 | .align 1 << L1_CACHE_SHIFT |
cc562d2e | 75 | .type ex_saved_reg1, @object |
41195d23 VG |
76 | #ifdef CONFIG_SMP |
77 | .size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT) | |
78 | ex_saved_reg1: | |
79 | .zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT) | |
80 | #else | |
cc562d2e VG |
81 | .size ex_saved_reg1, 16 |
82 | ex_saved_reg1: | |
83 | .zero 16 | |
41195d23 | 84 | #endif |
cc562d2e | 85 | |
4b06ff35 VG |
86 | .macro TLBMISS_FREEUP_REGS |
87 | #ifdef CONFIG_SMP | |
88 | sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with | |
89 | GET_CPU_ID r0 ; get to per cpu scratch mem, | |
90 | lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu | |
91 | add r0, @ex_saved_reg1, r0 | |
92 | #else | |
93 | st r0, [@ex_saved_reg1] | |
94 | mov_s r0, @ex_saved_reg1 | |
95 | #endif | |
96 | st_s r1, [r0, 4] | |
97 | st_s r2, [r0, 8] | |
98 | st_s r3, [r0, 12] | |
99 | ||
100 | ; VERIFY if the ASID in MMU-PID Reg is same as | |
101 | ; one in Linux data structures | |
102 | ||
5bd87adf | 103 | tlb_paranoid_check_asm |
4b06ff35 VG |
104 | .endm |
105 | ||
106 | .macro TLBMISS_RESTORE_REGS | |
107 | #ifdef CONFIG_SMP | |
108 | GET_CPU_ID r0 ; get to per cpu scratch mem | |
109 | lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide | |
110 | add r0, @ex_saved_reg1, r0 | |
111 | ld_s r3, [r0,12] | |
112 | ld_s r2, [r0, 8] | |
113 | ld_s r1, [r0, 4] | |
114 | lr r0, [ARC_REG_SCRATCH_DATA0] | |
115 | #else | |
116 | mov_s r0, @ex_saved_reg1 | |
117 | ld_s r3, [r0,12] | |
118 | ld_s r2, [r0, 8] | |
119 | ld_s r1, [r0, 4] | |
120 | ld_s r0, [r0] | |
121 | #endif | |
122 | .endm | |
123 | ||
cc562d2e VG |
124 | ;============================================================================ |
125 | ; Troubleshooting Stuff | |
126 | ;============================================================================ | |
127 | ||
128 | ; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid | |
129 | ; When Creating TLB Entries, instead of doing 3 dependent loads from memory, | |
130 | ; we use the MMU PID Reg to get current ASID. | |
131 | ; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble. | |
132 | ; So we try to detect this in TLB Mis shandler | |
133 | ||
5bd87adf | 134 | .macro tlb_paranoid_check_asm |
cc562d2e VG |
135 | |
136 | #ifdef CONFIG_ARC_DBG_TLB_PARANOIA | |
137 | ||
cc562d2e VG |
138 | GET_CURR_TASK_ON_CPU r3 |
139 | ld r0, [r3, TASK_ACT_MM] | |
140 | ld r0, [r0, MM_CTXT+MM_CTXT_ASID] | |
947bf103 | 141 | breq r0, 0, 55f ; Error if no ASID allocated |
cc562d2e VG |
142 | |
143 | lr r1, [ARC_REG_PID] | |
144 | and r1, r1, 0xFF | |
5bd87adf | 145 | |
947bf103 VG |
146 | and r2, r0, 0xFF ; MMU PID bits only for comparison |
147 | breq r1, r2, 5f | |
cc562d2e | 148 | |
947bf103 | 149 | 55: |
cc562d2e | 150 | ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode |
5bd87adf VG |
151 | lr r2, [erstatus] |
152 | bbit0 r2, STATUS_U_BIT, 5f | |
cc562d2e VG |
153 | |
154 | ; We sure are in troubled waters, Flag the error, but to do so | |
155 | ; need to switch to kernel mode stack to call error routine | |
156 | GET_TSK_STACK_BASE r3, sp | |
157 | ||
158 | ; Call printk to shoutout aloud | |
5bd87adf | 159 | mov r2, 1 |
cc562d2e VG |
160 | j print_asid_mismatch |
161 | ||
5bd87adf | 162 | 5: ; ASIDs match so proceed normally |
cc562d2e VG |
163 | nop |
164 | ||
165 | #endif | |
166 | ||
167 | .endm | |
168 | ||
169 | ;============================================================================ | |
170 | ;TLB Miss handling Code | |
171 | ;============================================================================ | |
172 | ||
173 | ;----------------------------------------------------------------------------- | |
174 | ; This macro does the page-table lookup for the faulting address. | |
175 | ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address | |
176 | .macro LOAD_FAULT_PTE | |
177 | ||
178 | lr r2, [efa] | |
179 | ||
41195d23 | 180 | #ifndef CONFIG_SMP |
cc562d2e | 181 | lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd |
41195d23 VG |
182 | #else |
183 | GET_CURR_TASK_ON_CPU r1 | |
184 | ld r1, [r1, TASK_ACT_MM] | |
185 | ld r1, [r1, MM_PGD] | |
186 | #endif | |
cc562d2e VG |
187 | |
188 | lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD | |
189 | ld.as r1, [r1, r0] ; PGD entry corresp to faulting addr | |
190 | and.f r1, r1, PAGE_MASK ; Ignoring protection and other flags | |
191 | ; contains Ptr to Page Table | |
192 | bz.d do_slow_path_pf ; if no Page Table, do page fault | |
193 | ||
194 | ; Get the PTE entry: The idea is | |
195 | ; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr | |
196 | ; (2) y = x & (PTRS_PER_PTE - 1) -> to get index | |
197 | ; (3) z = pgtbl[y] | |
198 | ; To avoid the multiply by in end, we do the -2, <<2 below | |
199 | ||
200 | lsr r0, r2, (PAGE_SHIFT - 2) | |
201 | and r0, r0, ( (PTRS_PER_PTE - 1) << 2) | |
202 | ld.aw r0, [r1, r0] ; get PTE and PTE ptr for fault addr | |
0ef88a54 VG |
203 | #ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT |
204 | and.f 0, r0, _PAGE_PRESENT | |
205 | bz 1f | |
dc81df24 VG |
206 | ld r3, [num_pte_not_present] |
207 | add r3, r3, 1 | |
208 | st r3, [num_pte_not_present] | |
0ef88a54 VG |
209 | 1: |
210 | #endif | |
cc562d2e VG |
211 | |
212 | .endm | |
213 | ||
214 | ;----------------------------------------------------------------- | |
215 | ; Convert Linux PTE entry into TLB entry | |
216 | ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu | |
217 | ; IN: r0 = PTE, r1 = ptr to PTE | |
218 | ||
219 | .macro CONV_PTE_TO_TLB | |
64b703ef | 220 | and r3, r0, PTE_BITS_RWX ; r w x |
c9a98e18 | 221 | lsl r2, r3, 3 ; r w x 0 0 0 (GLOBAL, kernel only) |
64b703ef | 222 | and.f 0, r0, _PAGE_GLOBAL |
c9a98e18 | 223 | or.z r2, r2, r3 ; r w x r w x (!GLOBAL, user page) |
64b703ef VG |
224 | |
225 | and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE | |
226 | or r3, r3, r2 | |
227 | ||
228 | sr r3, [ARC_REG_TLBPD1] ; these go in PD1 | |
cc562d2e VG |
229 | |
230 | and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb | |
cc562d2e VG |
231 | |
232 | lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid | |
233 | ||
234 | or r3, r3, r2 ; S | vaddr | {sasid|asid} | |
235 | sr r3,[ARC_REG_TLBPD0] ; rewrite PD0 | |
236 | .endm | |
237 | ||
238 | ;----------------------------------------------------------------- | |
239 | ; Commit the TLB entry into MMU | |
240 | ||
241 | .macro COMMIT_ENTRY_TO_MMU | |
242 | ||
243 | /* Get free TLB slot: Set = computed from vaddr, way = random */ | |
244 | sr TLBGetIndex, [ARC_REG_TLBCOMMAND] | |
245 | ||
246 | /* Commit the Write */ | |
247 | #if (CONFIG_ARC_MMU_VER >= 2) /* introduced in v2 */ | |
248 | sr TLBWriteNI, [ARC_REG_TLBCOMMAND] | |
249 | #else | |
250 | sr TLBWrite, [ARC_REG_TLBCOMMAND] | |
251 | #endif | |
252 | .endm | |
253 | ||
cc562d2e | 254 | |
8b5850f8 | 255 | ARCFP_CODE ;Fast Path Code, candidate for ICCM |
cc562d2e VG |
256 | |
257 | ;----------------------------------------------------------------------------- | |
258 | ; I-TLB Miss Exception Handler | |
259 | ;----------------------------------------------------------------------------- | |
260 | ||
ec7ac6af | 261 | ENTRY(EV_TLBMissI) |
cc562d2e VG |
262 | |
263 | TLBMISS_FREEUP_REGS | |
264 | ||
0ef88a54 VG |
265 | #ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT |
266 | ld r0, [@numitlb] | |
267 | add r0, r0, 1 | |
268 | st r0, [@numitlb] | |
269 | #endif | |
270 | ||
cc562d2e | 271 | ;---------------------------------------------------------------- |
dc81df24 | 272 | ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA |
cc562d2e VG |
273 | LOAD_FAULT_PTE |
274 | ||
275 | ;---------------------------------------------------------------- | |
276 | ; VERIFY_PTE: Check if PTE permissions approp for executing code | |
277 | cmp_s r2, VMALLOC_START | |
64b703ef VG |
278 | mov_s r2, (_PAGE_PRESENT | _PAGE_EXECUTE) |
279 | or.hs r2, r2, _PAGE_GLOBAL | |
cc562d2e VG |
280 | |
281 | and r3, r0, r2 ; Mask out NON Flag bits from PTE | |
282 | xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test ) | |
283 | bnz do_slow_path_pf | |
284 | ||
285 | ; Let Linux VM know that the page was accessed | |
c3e757a7 VG |
286 | or r0, r0, _PAGE_ACCESSED ; set Accessed Bit |
287 | st_s r0, [r1] ; Write back PTE | |
cc562d2e VG |
288 | |
289 | CONV_PTE_TO_TLB | |
290 | COMMIT_ENTRY_TO_MMU | |
291 | TLBMISS_RESTORE_REGS | |
292 | rtie | |
293 | ||
ec7ac6af | 294 | END(EV_TLBMissI) |
cc562d2e VG |
295 | |
296 | ;----------------------------------------------------------------------------- | |
297 | ; D-TLB Miss Exception Handler | |
298 | ;----------------------------------------------------------------------------- | |
299 | ||
ec7ac6af | 300 | ENTRY(EV_TLBMissD) |
cc562d2e VG |
301 | |
302 | TLBMISS_FREEUP_REGS | |
303 | ||
0ef88a54 VG |
304 | #ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT |
305 | ld r0, [@numdtlb] | |
306 | add r0, r0, 1 | |
307 | st r0, [@numdtlb] | |
308 | #endif | |
309 | ||
cc562d2e VG |
310 | ;---------------------------------------------------------------- |
311 | ; Get the PTE corresponding to V-addr accessed | |
dc81df24 | 312 | ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA |
cc562d2e VG |
313 | LOAD_FAULT_PTE |
314 | ||
315 | ;---------------------------------------------------------------- | |
316 | ; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W) | |
317 | ||
64b703ef VG |
318 | cmp_s r2, VMALLOC_START |
319 | mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE | |
320 | or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only | |
321 | ||
322 | ; Linux PTE [RWX] bits are semantically overloaded: | |
323 | ; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc) | |
324 | ; -Otherwise they are user-mode permissions, and those are exactly | |
325 | ; same for kernel mode as well (e.g. copy_(to|from)_user) | |
326 | ||
cc562d2e VG |
327 | lr r3, [ecr] |
328 | btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access | |
64b703ef | 329 | or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE |
cc562d2e | 330 | btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access |
64b703ef VG |
331 | or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE |
332 | ; Above laddering takes care of XCHG access (both R and W) | |
cc562d2e VG |
333 | |
334 | ; By now, r2 setup with all the Flags we need to check in PTE | |
335 | and r3, r0, r2 ; Mask out NON Flag bits from PTE | |
336 | brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test) | |
337 | ||
338 | ;---------------------------------------------------------------- | |
339 | ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty | |
340 | lr r3, [ecr] | |
c3e757a7 | 341 | or r0, r0, _PAGE_ACCESSED ; Accessed bit always |
cc562d2e VG |
342 | btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; See if it was a Write Access ? |
343 | or.nz r0, r0, _PAGE_MODIFIED ; if Write, set Dirty bit as well | |
344 | st_s r0, [r1] ; Write back PTE | |
345 | ||
346 | CONV_PTE_TO_TLB | |
347 | ||
348 | #if (CONFIG_ARC_MMU_VER == 1) | |
349 | ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of | |
350 | ; memcpy where 3 parties contend for 2 ways, ensuing a livelock. | |
351 | ; But only for old MMU or one with Metal Fix | |
352 | TLB_WRITE_HEURISTICS | |
353 | #endif | |
354 | ||
355 | COMMIT_ENTRY_TO_MMU | |
356 | TLBMISS_RESTORE_REGS | |
357 | rtie | |
358 | ||
359 | ;-------- Common routine to call Linux Page Fault Handler ----------- | |
360 | do_slow_path_pf: | |
361 | ||
362 | ; Restore the 4-scratch regs saved by fast path miss handler | |
363 | TLBMISS_RESTORE_REGS | |
364 | ||
365 | ; Slow path TLB Miss handled as a regular ARC Exception | |
366 | ; (stack switching / save the complete reg-file). | |
a615b47d | 367 | b call_do_page_fault |
ec7ac6af | 368 | END(EV_TLBMissD) |