ARM: SAMSUNG: Make legacy MFC support code depend on SAMSUNG_ATAGS
[deliverable/linux.git] / arch / arm / Kconfig
CommitLineData
1da177e4
LT
1config ARM
2 bool
3 default y
b1b3f49c
RK
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7563bbf8 6 select ARCH_HAVE_CUSTOM_GPIO_H
3d06770e 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
b1b3f49c 8 select ARCH_WANT_IPC_PARSE_VERSION
ee951c63 9 select BUILDTIME_EXTABLE_SORT if MMU
b1b3f49c 10 select CPU_PM if (SUSPEND || CPU_IDLE)
39b175a0 11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
a41297a0 12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
b1b3f49c
RK
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
b1b3f49c
RK
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
f7b861b7 18 select GENERIC_IDLE_POLL_SETUP
b1b3f49c
RK
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
22 select HAVE_AOUT
09f05d85 23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
5cbad0eb 24 select HAVE_ARCH_KGDB
4095ccc3 25 select HAVE_ARCH_SECCOMP_FILTER
0693bf68 26 select HAVE_ARCH_TRACEHOOK
b1b3f49c
RK
27 select HAVE_BPF_JIT
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_ATTRS
32 select HAVE_DMA_CONTIGUOUS if MMU
80be7a7f 33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
b1b3f49c 34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
0e341af8 35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
b1b3f49c 36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
1fe53268 37 select HAVE_GENERIC_DMA_COHERENT
b1b3f49c
RK
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
87c46b6c 41 select HAVE_IRQ_TIME_ACCOUNTING
e7db7b42 42 select HAVE_KERNEL_GZIP
6e8699f7 43 select HAVE_KERNEL_LZMA
b1b3f49c 44 select HAVE_KERNEL_LZO
a7f464f3 45 select HAVE_KERNEL_XZ
b1b3f49c
RK
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_MEMBLOCK
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
7ada189f 50 select HAVE_PERF_EVENTS
e513f8bf 51 select HAVE_REGS_AND_STACK_ACCESS_API
b1b3f49c 52 select HAVE_SYSCALL_TRACEPOINTS
af1839eb 53 select HAVE_UID16
3d92a71a 54 select KTIME_SCALAR
b1b3f49c
RK
55 select PERF_USE_VMALLOC
56 select RTC_LIB
57 select SYS_SUPPORTS_APM_EMULATION
786d35d4
DH
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
38a61b6b 60 select CLONE_BACKWARDS
b68fec24 61 select OLD_SIGSUSPEND3
50bcb7e4 62 select OLD_SIGACTION
b0088480 63 select HAVE_CONTEXT_TRACKING
1da177e4
LT
64 help
65 The ARM series is a line of low-power-consumption RISC chip designs
f6c8965a 66 licensed by ARM Ltd and targeted at embedded applications and
1da177e4 67 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
f6c8965a 68 manufactured, but legacy ARM-based PC hardware remains popular in
1da177e4
LT
69 Europe. There is an ARM Linux project with a web page at
70 <http://www.arm.linux.org.uk/>.
71
74facffe
RK
72config ARM_HAS_SG_CHAIN
73 bool
74
4ce63fcd
MS
75config NEED_SG_DMA_LENGTH
76 bool
77
78config ARM_DMA_USE_IOMMU
4ce63fcd 79 bool
b1b3f49c
RK
80 select ARM_HAS_SG_CHAIN
81 select NEED_SG_DMA_LENGTH
4ce63fcd 82
60460abf
SWK
83if ARM_DMA_USE_IOMMU
84
85config ARM_DMA_IOMMU_ALIGNMENT
86 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
87 range 4 9
88 default 8
89 help
90 DMA mapping framework by default aligns all buffers to the smallest
91 PAGE_SIZE order which is greater than or equal to the requested buffer
92 size. This works well for buffers up to a few hundreds kilobytes, but
93 for larger buffers it just a waste of address space. Drivers which has
94 relatively small addressing window (like 64Mib) might run out of
95 virtual space with just a few allocations.
96
97 With this parameter you can specify the maximum PAGE_SIZE order for
98 DMA IOMMU buffers. Larger buffers will be aligned only to this
99 specified order. The order is expressed as a power of two multiplied
100 by the PAGE_SIZE.
101
102endif
103
1a189b97
RK
104config HAVE_PWM
105 bool
106
0b05da72
HUK
107config MIGHT_HAVE_PCI
108 bool
109
75e7153a
RB
110config SYS_SUPPORTS_APM_EMULATION
111 bool
112
bc581770
LW
113config HAVE_TCM
114 bool
115 select GENERIC_ALLOCATOR
116
e119bfff
RK
117config HAVE_PROC_CPU
118 bool
119
5ea81769
AV
120config NO_IOPORT
121 bool
5ea81769 122
1da177e4
LT
123config EISA
124 bool
125 ---help---
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
128
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
133
134 Say Y here if you are building a kernel for an EISA-based machine.
135
136 Otherwise, say N.
137
138config SBUS
139 bool
140
f16fb1ec
RK
141config STACKTRACE_SUPPORT
142 bool
143 default y
144
f76e9154
NP
145config HAVE_LATENCYTOP_SUPPORT
146 bool
147 depends on !SMP
148 default y
149
f16fb1ec
RK
150config LOCKDEP_SUPPORT
151 bool
152 default y
153
7ad1bcb2
RK
154config TRACE_IRQFLAGS_SUPPORT
155 bool
156 default y
157
1da177e4
LT
158config RWSEM_GENERIC_SPINLOCK
159 bool
160 default y
161
162config RWSEM_XCHGADD_ALGORITHM
163 bool
164
f0d1b0b3
DH
165config ARCH_HAS_ILOG2_U32
166 bool
f0d1b0b3
DH
167
168config ARCH_HAS_ILOG2_U64
169 bool
f0d1b0b3 170
89c52ed4
BD
171config ARCH_HAS_CPUFREQ
172 bool
173 help
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
176 it.
177
b89c3b16
AM
178config GENERIC_HWEIGHT
179 bool
180 default y
181
1da177e4
LT
182config GENERIC_CALIBRATE_DELAY
183 bool
184 default y
185
a08b6b79
Z
186config ARCH_MAY_HAVE_PC_FDC
187 bool
188
5ac6da66
CL
189config ZONE_DMA
190 bool
5ac6da66 191
ccd7ab7f
FT
192config NEED_DMA_MAP_STATE
193 def_bool y
194
58af4a24
RH
195config ARCH_HAS_DMA_SET_COHERENT_MASK
196 bool
197
1da177e4
LT
198config GENERIC_ISA_DMA
199 bool
200
1da177e4
LT
201config FIQ
202 bool
203
13a5045d
RH
204config NEED_RET_TO_USER
205 bool
206
034d2f5a
AV
207config ARCH_MTD_XIP
208 bool
209
c760fc19
HC
210config VECTORS_BASE
211 hex
6afd6fae 212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
c760fc19
HC
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
214 default 0x00000000
215 help
216 The base address of exception vectors.
217
dc21af99 218config ARM_PATCH_PHYS_VIRT
c1becedc
RK
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
220 default y
b511d75d 221 depends on !XIP_KERNEL && MMU
dc21af99
RK
222 depends on !ARCH_REALVIEW || !SPARSEMEM
223 help
111e9a5c
RK
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
dc21af99 227
111e9a5c 228 This can only be used with non-XIP MMU kernels where the base
daece596 229 of physical memory is at a 16MB boundary.
dc21af99 230
c1becedc
RK
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
dc21af99 234
01464226
RH
235config NEED_MACH_GPIO_H
236 bool
237 help
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
241
c334bc15
RH
242config NEED_MACH_IO_H
243 bool
244 help
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
248
0cdc8b92 249config NEED_MACH_MEMORY_H
1b9f95f8
NP
250 bool
251 help
0cdc8b92
NP
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
dc21af99 255
1b9f95f8 256config PHYS_OFFSET
974c0724 257 hex "Physical address of main memory" if MMU
0cdc8b92 258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
974c0724 259 default DRAM_BASE if !MMU
111e9a5c 260 help
1b9f95f8
NP
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
cada3c08 263
87e040b6
SG
264config GENERIC_BUG
265 def_bool y
266 depends on BUG
267
1da177e4
LT
268source "init/Kconfig"
269
dc52ddc0
MH
270source "kernel/Kconfig.freezer"
271
1da177e4
LT
272menu "System Type"
273
3c427975
HC
274config MMU
275 bool "MMU-based Paged Memory Management Support"
276 default y
277 help
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
280
ccf50e23
RK
281#
282# The "ARM system type" choice list is ordered alphabetically by option
283# text. Please add new entries in the option alphabetic order.
284#
1da177e4
LT
285choice
286 prompt "ARM system type"
1420b22b
AB
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
1da177e4 289
387798b3
RH
290config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
b1b3f49c 292 depends on MMU
387798b3
RH
293 select ARM_PATCH_PHYS_VIRT
294 select AUTO_ZRELADDR
66314223 295 select COMMON_CLK
387798b3 296 select MULTI_IRQ_HANDLER
66314223
DN
297 select SPARSE_IRQ
298 select USE_OF
66314223 299
4af6fee1
DS
300config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
89c52ed4 302 select ARCH_HAS_CPUFREQ
b1b3f49c 303 select ARM_AMBA
a613163d 304 select COMMON_CLK
f9a6aa43 305 select COMMON_CLK_VERSATILE
b1b3f49c 306 select GENERIC_CLOCKEVENTS
9904f793 307 select HAVE_TCM
c5a0adb5 308 select ICST
b1b3f49c
RK
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
f4b8b319 311 select PLAT_VERSATILE
695436e3 312 select SPARSE_IRQ
2389d501 313 select VERSATILE_FPGA_IRQ
4af6fee1
DS
314 help
315 Support for ARM's Integrator platform.
316
317config ARCH_REALVIEW
318 bool "ARM Ltd. RealView family"
b1b3f49c 319 select ARCH_WANT_OPTIONAL_GPIOLIB
4af6fee1 320 select ARM_AMBA
b1b3f49c 321 select ARM_TIMER_SP804
f9a6aa43
LW
322 select COMMON_CLK
323 select COMMON_CLK_VERSATILE
ae30ceac 324 select GENERIC_CLOCKEVENTS
b56ba8aa 325 select GPIO_PL061 if GPIOLIB
b1b3f49c 326 select ICST
0cdc8b92 327 select NEED_MACH_MEMORY_H
b1b3f49c
RK
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
4af6fee1
DS
330 help
331 This enables support for ARM Ltd RealView boards.
332
333config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
b1b3f49c 335 select ARCH_WANT_OPTIONAL_GPIOLIB
4af6fee1 336 select ARM_AMBA
b1b3f49c 337 select ARM_TIMER_SP804
4af6fee1 338 select ARM_VIC
6d803ba7 339 select CLKDEV_LOOKUP
b1b3f49c 340 select GENERIC_CLOCKEVENTS
aa3831cf 341 select HAVE_MACH_CLKDEV
c5a0adb5 342 select ICST
f4b8b319 343 select PLAT_VERSATILE
3414ba8c 344 select PLAT_VERSATILE_CLCD
b1b3f49c 345 select PLAT_VERSATILE_CLOCK
2389d501 346 select VERSATILE_FPGA_IRQ
4af6fee1
DS
347 help
348 This enables support for ARM Ltd Versatile board.
349
8fc5ffa0
AV
350config ARCH_AT91
351 bool "Atmel AT91"
f373e8c0 352 select ARCH_REQUIRE_GPIOLIB
bd602995 353 select CLKDEV_LOOKUP
b1b3f49c 354 select HAVE_CLK
e261501d 355 select IRQ_DOMAIN
01464226 356 select NEED_MACH_GPIO_H
1ac02d79 357 select NEED_MACH_IO_H if PCCARD
6732ae5c
JCPV
358 select PINCTRL
359 select PINCTRL_AT91 if USE_OF
4af6fee1 360 help
929e994f
NF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
4af6fee1 363
93e22567
RK
364config ARCH_CLPS711X
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
a3b8d4a5 366 select ARCH_REQUIRE_GPIOLIB
ea7d1bc9 367 select AUTO_ZRELADDR
93e22567
RK
368 select CLKDEV_LOOKUP
369 select COMMON_CLK
370 select CPU_ARM720T
4a8355c4 371 select GENERIC_CLOCKEVENTS
99f04c8f 372 select MULTI_IRQ_HANDLER
93e22567 373 select NEED_MACH_MEMORY_H
0d8be81c 374 select SPARSE_IRQ
93e22567
RK
375 help
376 Support for Cirrus Logic 711x/721x/731x based boards.
377
788c9700
RK
378config ARCH_GEMINI
379 bool "Cortina Systems Gemini"
788c9700 380 select ARCH_REQUIRE_GPIOLIB
5cfc8ee0 381 select ARCH_USES_GETTIMEOFFSET
662146b1 382 select NEED_MACH_GPIO_H
b1b3f49c 383 select CPU_FA526
788c9700
RK
384 help
385 Support for the Cortina Systems Gemini family SoCs
386
1da177e4
LT
387config ARCH_EBSA110
388 bool "EBSA-110"
b1b3f49c 389 select ARCH_USES_GETTIMEOFFSET
c750815e 390 select CPU_SA110
f7e68bbf 391 select ISA
c334bc15 392 select NEED_MACH_IO_H
0cdc8b92 393 select NEED_MACH_MEMORY_H
b1b3f49c 394 select NO_IOPORT
1da177e4
LT
395 help
396 This is an evaluation board for the StrongARM processor available
f6c8965a 397 from Digital. It has limited hardware on-board, including an
1da177e4
LT
398 Ethernet interface, two PCMCIA sockets, two serial ports and a
399 parallel port.
400
e7736d47
LB
401config ARCH_EP93XX
402 bool "EP93xx-based"
b1b3f49c
RK
403 select ARCH_HAS_HOLES_MEMORYMODEL
404 select ARCH_REQUIRE_GPIOLIB
405 select ARCH_USES_GETTIMEOFFSET
e7736d47
LB
406 select ARM_AMBA
407 select ARM_VIC
6d803ba7 408 select CLKDEV_LOOKUP
b1b3f49c 409 select CPU_ARM920T
5725aeae 410 select NEED_MACH_MEMORY_H
e7736d47
LB
411 help
412 This enables support for the Cirrus EP93xx series of CPUs.
413
1da177e4
LT
414config ARCH_FOOTBRIDGE
415 bool "FootBridge"
c750815e 416 select CPU_SA110
1da177e4 417 select FOOTBRIDGE
4e8d7637 418 select GENERIC_CLOCKEVENTS
d0ee9f40 419 select HAVE_IDE
8ef6e620 420 select NEED_MACH_IO_H if !MMU
0cdc8b92 421 select NEED_MACH_MEMORY_H
f999b8bd
MM
422 help
423 Support for systems based on the DC21285 companion chip
424 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
1da177e4 425
4af6fee1
DS
426config ARCH_NETX
427 bool "Hilscher NetX based"
b1b3f49c 428 select ARM_VIC
234b6ced 429 select CLKSRC_MMIO
c750815e 430 select CPU_ARM926T
2fcfe6b8 431 select GENERIC_CLOCKEVENTS
f999b8bd 432 help
4af6fee1
DS
433 This enables support for systems based on the Hilscher NetX Soc
434
3b938be6
RK
435config ARCH_IOP13XX
436 bool "IOP13xx-based"
437 depends on MMU
3b938be6 438 select ARCH_SUPPORTS_MSI
b1b3f49c 439 select CPU_XSC3
0cdc8b92 440 select NEED_MACH_MEMORY_H
13a5045d 441 select NEED_RET_TO_USER
b1b3f49c
RK
442 select PCI
443 select PLAT_IOP
444 select VMSPLIT_1G
3b938be6
RK
445 help
446 Support for Intel's IOP13XX (XScale) family of processors.
447
3f7e5815
LB
448config ARCH_IOP32X
449 bool "IOP32x-based"
a4f7e763 450 depends on MMU
b1b3f49c 451 select ARCH_REQUIRE_GPIOLIB
c750815e 452 select CPU_XSCALE
01464226 453 select NEED_MACH_GPIO_H
13a5045d 454 select NEED_RET_TO_USER
f7e68bbf 455 select PCI
b1b3f49c 456 select PLAT_IOP
f999b8bd 457 help
3f7e5815
LB
458 Support for Intel's 80219 and IOP32X (XScale) family of
459 processors.
460
461config ARCH_IOP33X
462 bool "IOP33x-based"
463 depends on MMU
b1b3f49c 464 select ARCH_REQUIRE_GPIOLIB
c750815e 465 select CPU_XSCALE
01464226 466 select NEED_MACH_GPIO_H
13a5045d 467 select NEED_RET_TO_USER
3f7e5815 468 select PCI
b1b3f49c 469 select PLAT_IOP
3f7e5815
LB
470 help
471 Support for Intel's IOP33X (XScale) family of processors.
1da177e4 472
3b938be6
RK
473config ARCH_IXP4XX
474 bool "IXP4xx-based"
a4f7e763 475 depends on MMU
58af4a24 476 select ARCH_HAS_DMA_SET_COHERENT_MASK
b1b3f49c 477 select ARCH_REQUIRE_GPIOLIB
234b6ced 478 select CLKSRC_MMIO
c750815e 479 select CPU_XSCALE
b1b3f49c 480 select DMABOUNCE if PCI
3b938be6 481 select GENERIC_CLOCKEVENTS
0b05da72 482 select MIGHT_HAVE_PCI
c334bc15 483 select NEED_MACH_IO_H
9296d94d
FF
484 select USB_EHCI_BIG_ENDIAN_MMIO
485 select USB_EHCI_BIG_ENDIAN_DESC
c4713074 486 help
3b938be6 487 Support for Intel's IXP4XX (XScale) family of processors.
c4713074 488
edabd38e
SB
489config ARCH_DOVE
490 bool "Marvell Dove"
edabd38e 491 select ARCH_REQUIRE_GPIOLIB
756b2531 492 select CPU_PJ4
edabd38e 493 select GENERIC_CLOCKEVENTS
0f81bd43 494 select MIGHT_HAVE_PCI
9139acd1
SH
495 select PINCTRL
496 select PINCTRL_DOVE
abcda1dc 497 select PLAT_ORION_LEGACY
0f81bd43 498 select USB_ARCH_HAS_EHCI
7d554902 499 select MVEBU_MBUS
edabd38e
SB
500 help
501 Support for the Marvell Dove SoC 88AP510
502
651c74c7
SB
503config ARCH_KIRKWOOD
504 bool "Marvell Kirkwood"
a8865655 505 select ARCH_REQUIRE_GPIOLIB
b1b3f49c 506 select CPU_FEROCEON
651c74c7 507 select GENERIC_CLOCKEVENTS
b1b3f49c 508 select PCI
1dc831bf 509 select PCI_QUIRKS
f9e75922
AL
510 select PINCTRL
511 select PINCTRL_KIRKWOOD
abcda1dc 512 select PLAT_ORION_LEGACY
5cc0673a 513 select MVEBU_MBUS
651c74c7
SB
514 help
515 Support for the following Marvell Kirkwood series SoCs:
516 88F6180, 88F6192 and 88F6281.
517
794d15b2
SS
518config ARCH_MV78XX0
519 bool "Marvell MV78xx0"
a8865655 520 select ARCH_REQUIRE_GPIOLIB
b1b3f49c 521 select CPU_FEROCEON
794d15b2 522 select GENERIC_CLOCKEVENTS
b1b3f49c 523 select PCI
abcda1dc 524 select PLAT_ORION_LEGACY
95b80e0a 525 select MVEBU_MBUS
794d15b2
SS
526 help
527 Support for the following Marvell MV78xx0 series SoCs:
528 MV781x0, MV782x0.
529
9dd0b194 530config ARCH_ORION5X
585cf175
TP
531 bool "Marvell Orion"
532 depends on MMU
a8865655 533 select ARCH_REQUIRE_GPIOLIB
b1b3f49c 534 select CPU_FEROCEON
51cbff1d 535 select GENERIC_CLOCKEVENTS
b1b3f49c 536 select PCI
abcda1dc 537 select PLAT_ORION_LEGACY
5d1190ea 538 select MVEBU_MBUS
585cf175 539 help
9dd0b194 540 Support for the following Marvell Orion 5x series SoCs:
d2b2a6bb 541 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
d323ade1 542 Orion-2 (5281), Orion-1-90 (6183).
585cf175 543
788c9700 544config ARCH_MMP
2f7e8fae 545 bool "Marvell PXA168/910/MMP2"
788c9700 546 depends on MMU
788c9700 547 select ARCH_REQUIRE_GPIOLIB
6d803ba7 548 select CLKDEV_LOOKUP
b1b3f49c 549 select GENERIC_ALLOCATOR
788c9700 550 select GENERIC_CLOCKEVENTS
157d2644 551 select GPIO_PXA
c24b3114 552 select IRQ_DOMAIN
b1b3f49c 553 select NEED_MACH_GPIO_H
7c8f86a4 554 select PINCTRL
788c9700 555 select PLAT_PXA
0bd86961 556 select SPARSE_IRQ
788c9700 557 help
2f7e8fae 558 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
788c9700
RK
559
560config ARCH_KS8695
561 bool "Micrel/Kendin KS8695"
98830bc9 562 select ARCH_REQUIRE_GPIOLIB
c7e783d6 563 select CLKSRC_MMIO
b1b3f49c 564 select CPU_ARM922T
c7e783d6 565 select GENERIC_CLOCKEVENTS
b1b3f49c 566 select NEED_MACH_MEMORY_H
788c9700
RK
567 help
568 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
569 System-on-Chip devices.
570
788c9700
RK
571config ARCH_W90X900
572 bool "Nuvoton W90X900 CPU"
c52d3d68 573 select ARCH_REQUIRE_GPIOLIB
6d803ba7 574 select CLKDEV_LOOKUP
6fa5d5f7 575 select CLKSRC_MMIO
b1b3f49c 576 select CPU_ARM926T
58b5369e 577 select GENERIC_CLOCKEVENTS
788c9700 578 help
a8bc4ead 579 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
580 At present, the w90x900 has been renamed nuc900, regarding
581 the ARM series product line, you can login the following
582 link address to know more.
583
584 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
585 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
788c9700 586
93e22567
RK
587config ARCH_LPC32XX
588 bool "NXP LPC32XX"
589 select ARCH_REQUIRE_GPIOLIB
590 select ARM_AMBA
591 select CLKDEV_LOOKUP
592 select CLKSRC_MMIO
593 select CPU_ARM926T
594 select GENERIC_CLOCKEVENTS
595 select HAVE_IDE
596 select HAVE_PWM
597 select USB_ARCH_HAS_OHCI
598 select USE_OF
599 help
600 Support for the NXP LPC32XX family of processors
601
1da177e4 602config ARCH_PXA
2c8086a5 603 bool "PXA2xx/PXA3xx-based"
a4f7e763 604 depends on MMU
89c52ed4 605 select ARCH_HAS_CPUFREQ
b1b3f49c
RK
606 select ARCH_MTD_XIP
607 select ARCH_REQUIRE_GPIOLIB
608 select ARM_CPU_SUSPEND if PM
609 select AUTO_ZRELADDR
6d803ba7 610 select CLKDEV_LOOKUP
234b6ced 611 select CLKSRC_MMIO
981d0f39 612 select GENERIC_CLOCKEVENTS
157d2644 613 select GPIO_PXA
d0ee9f40 614 select HAVE_IDE
b1b3f49c 615 select MULTI_IRQ_HANDLER
01464226 616 select NEED_MACH_GPIO_H
b1b3f49c
RK
617 select PLAT_PXA
618 select SPARSE_IRQ
f999b8bd 619 help
2c8086a5 620 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
1da177e4 621
788c9700
RK
622config ARCH_MSM
623 bool "Qualcomm MSM"
923a081c 624 select ARCH_REQUIRE_GPIOLIB
bd32344a 625 select CLKDEV_LOOKUP
b1b3f49c
RK
626 select GENERIC_CLOCKEVENTS
627 select HAVE_CLK
49cbe786 628 help
4b53eb4f
DW
629 Support for Qualcomm MSM/QSD based systems. This runs on the
630 apps processor of the MSM/QSD and depends on a shared memory
631 interface to the modem processor which runs the baseband
632 stack and controls some vital subsystems
633 (clock and power control, etc).
49cbe786 634
c793c1b0 635config ARCH_SHMOBILE
6d72ad35 636 bool "Renesas SH-Mobile / R-Mobile"
5e93c6b4 637 select CLKDEV_LOOKUP
b1b3f49c 638 select GENERIC_CLOCKEVENTS
4c3ffffd
SB
639 select HAVE_ARM_SCU if SMP
640 select HAVE_ARM_TWD if LOCAL_TIMERS
b1b3f49c 641 select HAVE_CLK
aa3831cf 642 select HAVE_MACH_CLKDEV
3b55658a 643 select HAVE_SMP
ce5ea9f3 644 select MIGHT_HAVE_CACHE_L2X0
60f1435c 645 select MULTI_IRQ_HANDLER
0cdc8b92 646 select NEED_MACH_MEMORY_H
b1b3f49c 647 select NO_IOPORT
6722f6cb 648 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
b1b3f49c
RK
649 select PM_GENERIC_DOMAINS if PM
650 select SPARSE_IRQ
c793c1b0 651 help
6d72ad35 652 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
c793c1b0 653
1da177e4
LT
654config ARCH_RPC
655 bool "RiscPC"
656 select ARCH_ACORN
a08b6b79 657 select ARCH_MAY_HAVE_PC_FDC
07f841b7 658 select ARCH_SPARSEMEM_ENABLE
5cfc8ee0 659 select ARCH_USES_GETTIMEOFFSET
b1b3f49c 660 select FIQ
d0ee9f40 661 select HAVE_IDE
b1b3f49c
RK
662 select HAVE_PATA_PLATFORM
663 select ISA_DMA_API
c334bc15 664 select NEED_MACH_IO_H
0cdc8b92 665 select NEED_MACH_MEMORY_H
b1b3f49c 666 select NO_IOPORT
b4811bac 667 select VIRT_TO_BUS
1da177e4
LT
668 help
669 On the Acorn Risc-PC, Linux can support the internal IDE disk and
670 CD-ROM interface, serial and parallel port, and the floppy drive.
671
672config ARCH_SA1100
673 bool "SA1100-based"
89c52ed4 674 select ARCH_HAS_CPUFREQ
b1b3f49c
RK
675 select ARCH_MTD_XIP
676 select ARCH_REQUIRE_GPIOLIB
677 select ARCH_SPARSEMEM_ENABLE
678 select CLKDEV_LOOKUP
679 select CLKSRC_MMIO
1937f5b9 680 select CPU_FREQ
b1b3f49c 681 select CPU_SA1100
3e238be2 682 select GENERIC_CLOCKEVENTS
d0ee9f40 683 select HAVE_IDE
b1b3f49c 684 select ISA
01464226 685 select NEED_MACH_GPIO_H
0cdc8b92 686 select NEED_MACH_MEMORY_H
375dec92 687 select SPARSE_IRQ
f999b8bd
MM
688 help
689 Support for StrongARM 11x0 based boards.
1da177e4 690
b130d5c2
KK
691config ARCH_S3C24XX
692 bool "Samsung S3C24XX SoCs"
9d56c02a 693 select ARCH_HAS_CPUFREQ
53650430 694 select ARCH_REQUIRE_GPIOLIB
b1b3f49c 695 select CLKDEV_LOOKUP
7f78b6eb
RN
696 select CLKSRC_MMIO
697 select GENERIC_CLOCKEVENTS
880cf071 698 select GPIO_SAMSUNG
b1b3f49c 699 select HAVE_CLK
20676c15 700 select HAVE_S3C2410_I2C if I2C
b130d5c2 701 select HAVE_S3C2410_WATCHDOG if WATCHDOG
b1b3f49c 702 select HAVE_S3C_RTC if RTC_CLASS
17453dd2 703 select MULTI_IRQ_HANDLER
01464226 704 select NEED_MACH_GPIO_H
c334bc15 705 select NEED_MACH_IO_H
cd8dc7ae 706 select SAMSUNG_ATAGS
1da177e4 707 help
b130d5c2
KK
708 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
709 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
710 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
711 Samsung SMDK2410 development board (and derivatives).
63b1f51b 712
a08ab637
BD
713config ARCH_S3C64XX
714 bool "Samsung S3C64XX"
b1b3f49c
RK
715 select ARCH_HAS_CPUFREQ
716 select ARCH_REQUIRE_GPIOLIB
89f0ce72 717 select ARM_VIC
b1b3f49c 718 select CLKDEV_LOOKUP
04a49b71 719 select CLKSRC_MMIO
b1b3f49c 720 select CPU_V6
04a49b71 721 select GENERIC_CLOCKEVENTS
880cf071 722 select GPIO_SAMSUNG
a08ab637 723 select HAVE_CLK
b1b3f49c
RK
724 select HAVE_S3C2410_I2C if I2C
725 select HAVE_S3C2410_WATCHDOG if WATCHDOG
6700397a 726 select HAVE_TCM
b1b3f49c 727 select NEED_MACH_GPIO_H
89f0ce72 728 select NO_IOPORT
b1b3f49c
RK
729 select PLAT_SAMSUNG
730 select S3C_DEV_NAND
731 select S3C_GPIO_TRACK
cd8dc7ae 732 select SAMSUNG_ATAGS
89f0ce72 733 select SAMSUNG_CLKSRC
b1b3f49c 734 select SAMSUNG_GPIOLIB_4BIT
89f0ce72 735 select SAMSUNG_IRQ_VIC_TIMER
89f0ce72 736 select USB_ARCH_HAS_OHCI
a08ab637
BD
737 help
738 Samsung S3C64XX series based systems
739
49b7a491
KK
740config ARCH_S5P64X0
741 bool "Samsung S5P6440 S5P6450"
d8b22d25 742 select CLKDEV_LOOKUP
0665ccc4 743 select CLKSRC_MMIO
b1b3f49c 744 select CPU_V6
9e65bbf2 745 select GENERIC_CLOCKEVENTS
880cf071 746 select GPIO_SAMSUNG
b1b3f49c 747 select HAVE_CLK
20676c15 748 select HAVE_S3C2410_I2C if I2C
b1b3f49c 749 select HAVE_S3C2410_WATCHDOG if WATCHDOG
754961a8 750 select HAVE_S3C_RTC if RTC_CLASS
01464226 751 select NEED_MACH_GPIO_H
cd8dc7ae 752 select SAMSUNG_ATAGS
c4ffccdd 753 help
49b7a491
KK
754 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
755 SMDK6450.
c4ffccdd 756
acc84707
MS
757config ARCH_S5PC100
758 bool "Samsung S5PC100"
53650430 759 select ARCH_REQUIRE_GPIOLIB
29e8eb0f 760 select CLKDEV_LOOKUP
6a5a2e3b 761 select CLKSRC_MMIO
5a7652f2 762 select CPU_V7
6a5a2e3b 763 select GENERIC_CLOCKEVENTS
880cf071 764 select GPIO_SAMSUNG
b1b3f49c 765 select HAVE_CLK
20676c15 766 select HAVE_S3C2410_I2C if I2C
c39d8d55 767 select HAVE_S3C2410_WATCHDOG if WATCHDOG
b1b3f49c 768 select HAVE_S3C_RTC if RTC_CLASS
01464226 769 select NEED_MACH_GPIO_H
cd8dc7ae 770 select SAMSUNG_ATAGS
5a7652f2 771 help
acc84707 772 Samsung S5PC100 series based systems
5a7652f2 773
170f4e42
KK
774config ARCH_S5PV210
775 bool "Samsung S5PV210/S5PC110"
b1b3f49c 776 select ARCH_HAS_CPUFREQ
0f75a96b 777 select ARCH_HAS_HOLES_MEMORYMODEL
b1b3f49c 778 select ARCH_SPARSEMEM_ENABLE
b2a9dd46 779 select CLKDEV_LOOKUP
0665ccc4 780 select CLKSRC_MMIO
b1b3f49c 781 select CPU_V7
9e65bbf2 782 select GENERIC_CLOCKEVENTS
880cf071 783 select GPIO_SAMSUNG
b1b3f49c 784 select HAVE_CLK
20676c15 785 select HAVE_S3C2410_I2C if I2C
c39d8d55 786 select HAVE_S3C2410_WATCHDOG if WATCHDOG
b1b3f49c 787 select HAVE_S3C_RTC if RTC_CLASS
01464226 788 select NEED_MACH_GPIO_H
0cdc8b92 789 select NEED_MACH_MEMORY_H
cd8dc7ae 790 select SAMSUNG_ATAGS
170f4e42
KK
791 help
792 Samsung S5PV210/S5PC110 series based systems
793
83014579 794config ARCH_EXYNOS
93e22567 795 bool "Samsung EXYNOS"
b1b3f49c 796 select ARCH_HAS_CPUFREQ
0f75a96b 797 select ARCH_HAS_HOLES_MEMORYMODEL
e245f969 798 select ARCH_REQUIRE_GPIOLIB
b1b3f49c 799 select ARCH_SPARSEMEM_ENABLE
e245f969 800 select ARM_GIC
badc4f2d 801 select CLKDEV_LOOKUP
340fcb5c 802 select COMMON_CLK
b1b3f49c 803 select CPU_V7
cc0e72b8 804 select GENERIC_CLOCKEVENTS
b1b3f49c 805 select HAVE_CLK
20676c15 806 select HAVE_S3C2410_I2C if I2C
c39d8d55 807 select HAVE_S3C2410_WATCHDOG if WATCHDOG
b1b3f49c 808 select HAVE_S3C_RTC if RTC_CLASS
0cdc8b92 809 select NEED_MACH_MEMORY_H
f8b1ac01 810 select USE_OF
cc0e72b8 811 help
83014579 812 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
cc0e72b8 813
1da177e4
LT
814config ARCH_SHARK
815 bool "Shark"
b1b3f49c 816 select ARCH_USES_GETTIMEOFFSET
c750815e 817 select CPU_SA110
f7e68bbf
RK
818 select ISA
819 select ISA_DMA
0cdc8b92 820 select NEED_MACH_MEMORY_H
b1b3f49c 821 select PCI
b4811bac 822 select VIRT_TO_BUS
b1b3f49c 823 select ZONE_DMA
f999b8bd
MM
824 help
825 Support for the StrongARM based Digital DNARD machine, also known
826 as "Shark" (<http://www.shark-linux.de/shark.html>).
1da177e4 827
d98aac75
LW
828config ARCH_U300
829 bool "ST-Ericsson U300 Series"
830 depends on MMU
b1b3f49c 831 select ARCH_REQUIRE_GPIOLIB
d98aac75 832 select ARM_AMBA
5485c1e0 833 select ARM_PATCH_PHYS_VIRT
d98aac75 834 select ARM_VIC
6d803ba7 835 select CLKDEV_LOOKUP
b1b3f49c 836 select CLKSRC_MMIO
50667d63 837 select COMMON_CLK
b1b3f49c
RK
838 select CPU_ARM926T
839 select GENERIC_CLOCKEVENTS
b1b3f49c 840 select HAVE_TCM
a4fe292f 841 select SPARSE_IRQ
d98aac75
LW
842 help
843 Support for ST-Ericsson U300 series mobile platforms.
844
7c6337e2
KH
845config ARCH_DAVINCI
846 bool "TI DaVinci"
b1b3f49c 847 select ARCH_HAS_HOLES_MEMORYMODEL
dce1115b 848 select ARCH_REQUIRE_GPIOLIB
6d803ba7 849 select CLKDEV_LOOKUP
20e9969b 850 select GENERIC_ALLOCATOR
b1b3f49c 851 select GENERIC_CLOCKEVENTS
dc7ad3b3 852 select GENERIC_IRQ_CHIP
b1b3f49c 853 select HAVE_IDE
01464226 854 select NEED_MACH_GPIO_H
689e331f 855 select USE_OF
b1b3f49c 856 select ZONE_DMA
7c6337e2
KH
857 help
858 Support for TI's DaVinci platform.
859
a0694861
TL
860config ARCH_OMAP1
861 bool "TI OMAP1"
00a36698 862 depends on MMU
89c52ed4 863 select ARCH_HAS_CPUFREQ
9af915da 864 select ARCH_HAS_HOLES_MEMORYMODEL
a0694861 865 select ARCH_OMAP
21f47fbc 866 select ARCH_REQUIRE_GPIOLIB
b1b3f49c 867 select CLKDEV_LOOKUP
d6e15d78 868 select CLKSRC_MMIO
b1b3f49c 869 select GENERIC_CLOCKEVENTS
a0694861 870 select GENERIC_IRQ_CHIP
e9a91de7 871 select HAVE_CLK
a0694861
TL
872 select HAVE_IDE
873 select IRQ_DOMAIN
874 select NEED_MACH_IO_H if PCCARD
875 select NEED_MACH_MEMORY_H
21f47fbc 876 help
a0694861 877 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
02c981c0 878
1da177e4
LT
879endchoice
880
387798b3
RH
881menu "Multiple platform selection"
882 depends on ARCH_MULTIPLATFORM
883
884comment "CPU Core family selection"
885
886config ARCH_MULTI_V4
887 bool "ARMv4 based platforms (FA526, StrongARM)"
387798b3 888 depends on !ARCH_MULTI_V6_V7
b1b3f49c 889 select ARCH_MULTI_V4_V5
387798b3
RH
890
891config ARCH_MULTI_V4T
892 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
387798b3 893 depends on !ARCH_MULTI_V6_V7
b1b3f49c 894 select ARCH_MULTI_V4_V5
387798b3
RH
895
896config ARCH_MULTI_V5
897 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
387798b3 898 depends on !ARCH_MULTI_V6_V7
b1b3f49c 899 select ARCH_MULTI_V4_V5
387798b3
RH
900
901config ARCH_MULTI_V4_V5
902 bool
903
904config ARCH_MULTI_V6
8dda05cc 905 bool "ARMv6 based platforms (ARM11)"
387798b3 906 select ARCH_MULTI_V6_V7
b1b3f49c 907 select CPU_V6
387798b3
RH
908
909config ARCH_MULTI_V7
8dda05cc 910 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
387798b3
RH
911 default y
912 select ARCH_MULTI_V6_V7
b1b3f49c 913 select CPU_V7
387798b3
RH
914
915config ARCH_MULTI_V6_V7
916 bool
917
918config ARCH_MULTI_CPU_AUTO
919 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
920 select ARCH_MULTI_V5
921
922endmenu
923
ccf50e23
RK
924#
925# This is sorted alphabetically by mach-* pathname. However, plat-*
926# Kconfigs may be included either alphabetically (according to the
927# plat- suffix) or along side the corresponding mach-* source.
928#
3e93a22b
GC
929source "arch/arm/mach-mvebu/Kconfig"
930
95b8f20f
RK
931source "arch/arm/mach-at91/Kconfig"
932
8ac49e04
CD
933source "arch/arm/mach-bcm/Kconfig"
934
f1ac922d
SW
935source "arch/arm/mach-bcm2835/Kconfig"
936
1da177e4
LT
937source "arch/arm/mach-clps711x/Kconfig"
938
d94f944e
AV
939source "arch/arm/mach-cns3xxx/Kconfig"
940
95b8f20f
RK
941source "arch/arm/mach-davinci/Kconfig"
942
943source "arch/arm/mach-dove/Kconfig"
944
e7736d47
LB
945source "arch/arm/mach-ep93xx/Kconfig"
946
1da177e4
LT
947source "arch/arm/mach-footbridge/Kconfig"
948
59d3a193
PZ
949source "arch/arm/mach-gemini/Kconfig"
950
387798b3
RH
951source "arch/arm/mach-highbank/Kconfig"
952
1da177e4
LT
953source "arch/arm/mach-integrator/Kconfig"
954
3f7e5815
LB
955source "arch/arm/mach-iop32x/Kconfig"
956
957source "arch/arm/mach-iop33x/Kconfig"
1da177e4 958
285f5fa7
DW
959source "arch/arm/mach-iop13xx/Kconfig"
960
1da177e4
LT
961source "arch/arm/mach-ixp4xx/Kconfig"
962
95b8f20f
RK
963source "arch/arm/mach-kirkwood/Kconfig"
964
965source "arch/arm/mach-ks8695/Kconfig"
966
95b8f20f
RK
967source "arch/arm/mach-msm/Kconfig"
968
794d15b2
SS
969source "arch/arm/mach-mv78xx0/Kconfig"
970
3995eb82 971source "arch/arm/mach-imx/Kconfig"
1da177e4 972
1d3f33d5
SG
973source "arch/arm/mach-mxs/Kconfig"
974
95b8f20f 975source "arch/arm/mach-netx/Kconfig"
49cbe786 976
95b8f20f 977source "arch/arm/mach-nomadik/Kconfig"
95b8f20f 978
d48af15e
TL
979source "arch/arm/plat-omap/Kconfig"
980
981source "arch/arm/mach-omap1/Kconfig"
1da177e4 982
1dbae815
TL
983source "arch/arm/mach-omap2/Kconfig"
984
9dd0b194 985source "arch/arm/mach-orion5x/Kconfig"
585cf175 986
387798b3
RH
987source "arch/arm/mach-picoxcell/Kconfig"
988
95b8f20f
RK
989source "arch/arm/mach-pxa/Kconfig"
990source "arch/arm/plat-pxa/Kconfig"
585cf175 991
95b8f20f
RK
992source "arch/arm/mach-mmp/Kconfig"
993
994source "arch/arm/mach-realview/Kconfig"
995
996source "arch/arm/mach-sa1100/Kconfig"
edabd38e 997
cf383678 998source "arch/arm/plat-samsung/Kconfig"
a21765a7 999
387798b3
RH
1000source "arch/arm/mach-socfpga/Kconfig"
1001
a7ed099f 1002source "arch/arm/mach-spear/Kconfig"
a21765a7 1003
85fd6d63 1004source "arch/arm/mach-s3c24xx/Kconfig"
1da177e4 1005
a08ab637 1006if ARCH_S3C64XX
431107ea 1007source "arch/arm/mach-s3c64xx/Kconfig"
a08ab637
BD
1008endif
1009
49b7a491 1010source "arch/arm/mach-s5p64x0/Kconfig"
c4ffccdd 1011
5a7652f2 1012source "arch/arm/mach-s5pc100/Kconfig"
5a7652f2 1013
170f4e42
KK
1014source "arch/arm/mach-s5pv210/Kconfig"
1015
83014579 1016source "arch/arm/mach-exynos/Kconfig"
cc0e72b8 1017
882d01f9 1018source "arch/arm/mach-shmobile/Kconfig"
52c543f9 1019
3b52634f
MR
1020source "arch/arm/mach-sunxi/Kconfig"
1021
156a0997
BS
1022source "arch/arm/mach-prima2/Kconfig"
1023
c5f80065
EG
1024source "arch/arm/mach-tegra/Kconfig"
1025
95b8f20f 1026source "arch/arm/mach-u300/Kconfig"
1da177e4 1027
95b8f20f 1028source "arch/arm/mach-ux500/Kconfig"
1da177e4
LT
1029
1030source "arch/arm/mach-versatile/Kconfig"
1031
ceade897 1032source "arch/arm/mach-vexpress/Kconfig"
420c34e4 1033source "arch/arm/plat-versatile/Kconfig"
ceade897 1034
2a0ba738
MZ
1035source "arch/arm/mach-virt/Kconfig"
1036
6f35f9a9
TP
1037source "arch/arm/mach-vt8500/Kconfig"
1038
7ec80ddf 1039source "arch/arm/mach-w90x900/Kconfig"
1040
9a45eb69
JC
1041source "arch/arm/mach-zynq/Kconfig"
1042
1da177e4
LT
1043# Definitions to make life easier
1044config ARCH_ACORN
1045 bool
1046
7ae1f7ec
LB
1047config PLAT_IOP
1048 bool
469d3044 1049 select GENERIC_CLOCKEVENTS
7ae1f7ec 1050
69b02f6a
LB
1051config PLAT_ORION
1052 bool
bfe45e0b 1053 select CLKSRC_MMIO
b1b3f49c 1054 select COMMON_CLK
dc7ad3b3 1055 select GENERIC_IRQ_CHIP
278b45b0 1056 select IRQ_DOMAIN
69b02f6a 1057
abcda1dc
TP
1058config PLAT_ORION_LEGACY
1059 bool
1060 select PLAT_ORION
1061
bd5ce433
EM
1062config PLAT_PXA
1063 bool
1064
f4b8b319
RK
1065config PLAT_VERSATILE
1066 bool
1067
e3887714
RK
1068config ARM_TIMER_SP804
1069 bool
bfe45e0b 1070 select CLKSRC_MMIO
7a0eca71 1071 select CLKSRC_OF if OF
e3887714 1072
1da177e4
LT
1073source arch/arm/mm/Kconfig
1074
958cab0f
RK
1075config ARM_NR_BANKS
1076 int
1077 default 16 if ARCH_EP93XX
1078 default 8
1079
afe4b25e 1080config IWMMXT
698613b6 1081 bool "Enable iWMMXt support" if !CPU_PJ4
ef6c8445 1082 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
698613b6 1083 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
afe4b25e
LB
1084 help
1085 Enable support for iWMMXt context switching at run time if
1086 running on a CPU that supports it.
1087
1da177e4
LT
1088config XSCALE_PMU
1089 bool
bfc994b5 1090 depends on CPU_XSCALE
1da177e4
LT
1091 default y
1092
52108641 1093config MULTI_IRQ_HANDLER
1094 bool
1095 help
1096 Allow each machine to specify it's own IRQ handler at run time.
1097
3b93e7b0
HC
1098if !MMU
1099source "arch/arm/Kconfig-nommu"
1100endif
1101
f0c4b8d6
WD
1102config ARM_ERRATA_326103
1103 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1104 depends on CPU_V6
1105 help
1106 Executing a SWP instruction to read-only memory does not set bit 11
1107 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1108 treat the access as a read, preventing a COW from occurring and
1109 causing the faulting task to livelock.
1110
9cba3ccc
CM
1111config ARM_ERRATA_411920
1112 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
e399b1a4 1113 depends on CPU_V6 || CPU_V6K
9cba3ccc
CM
1114 help
1115 Invalidation of the Instruction Cache operation can
1116 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1117 It does not affect the MPCore. This option enables the ARM Ltd.
1118 recommended workaround.
1119
7ce236fc
CM
1120config ARM_ERRATA_430973
1121 bool "ARM errata: Stale prediction on replaced interworking branch"
1122 depends on CPU_V7
1123 help
1124 This option enables the workaround for the 430973 Cortex-A8
1125 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1126 interworking branch is replaced with another code sequence at the
1127 same virtual address, whether due to self-modifying code or virtual
1128 to physical address re-mapping, Cortex-A8 does not recover from the
1129 stale interworking branch prediction. This results in Cortex-A8
1130 executing the new code sequence in the incorrect ARM or Thumb state.
1131 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1132 and also flushes the branch target cache at every context switch.
1133 Note that setting specific bits in the ACTLR register may not be
1134 available in non-secure mode.
1135
855c551f
CM
1136config ARM_ERRATA_458693
1137 bool "ARM errata: Processor deadlock when a false hazard is created"
1138 depends on CPU_V7
62e4d357 1139 depends on !ARCH_MULTIPLATFORM
855c551f
CM
1140 help
1141 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1142 erratum. For very specific sequences of memory operations, it is
1143 possible for a hazard condition intended for a cache line to instead
1144 be incorrectly associated with a different cache line. This false
1145 hazard might then cause a processor deadlock. The workaround enables
1146 the L1 caching of the NEON accesses and disables the PLD instruction
1147 in the ACTLR register. Note that setting specific bits in the ACTLR
1148 register may not be available in non-secure mode.
1149
0516e464
CM
1150config ARM_ERRATA_460075
1151 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1152 depends on CPU_V7
62e4d357 1153 depends on !ARCH_MULTIPLATFORM
0516e464
CM
1154 help
1155 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1156 erratum. Any asynchronous access to the L2 cache may encounter a
1157 situation in which recent store transactions to the L2 cache are lost
1158 and overwritten with stale memory contents from external memory. The
1159 workaround disables the write-allocate mode for the L2 cache via the
1160 ACTLR register. Note that setting specific bits in the ACTLR register
1161 may not be available in non-secure mode.
1162
9f05027c
WD
1163config ARM_ERRATA_742230
1164 bool "ARM errata: DMB operation may be faulty"
1165 depends on CPU_V7 && SMP
62e4d357 1166 depends on !ARCH_MULTIPLATFORM
9f05027c
WD
1167 help
1168 This option enables the workaround for the 742230 Cortex-A9
1169 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1170 between two write operations may not ensure the correct visibility
1171 ordering of the two writes. This workaround sets a specific bit in
1172 the diagnostic register of the Cortex-A9 which causes the DMB
1173 instruction to behave as a DSB, ensuring the correct behaviour of
1174 the two writes.
1175
a672e99b
WD
1176config ARM_ERRATA_742231
1177 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1178 depends on CPU_V7 && SMP
62e4d357 1179 depends on !ARCH_MULTIPLATFORM
a672e99b
WD
1180 help
1181 This option enables the workaround for the 742231 Cortex-A9
1182 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1183 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1184 accessing some data located in the same cache line, may get corrupted
1185 data due to bad handling of the address hazard when the line gets
1186 replaced from one of the CPUs at the same time as another CPU is
1187 accessing it. This workaround sets specific bits in the diagnostic
1188 register of the Cortex-A9 which reduces the linefill issuing
1189 capabilities of the processor.
1190
9e65582a 1191config PL310_ERRATA_588369
fa0ce403 1192 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
2839e06c 1193 depends on CACHE_L2X0
9e65582a
SS
1194 help
1195 The PL310 L2 cache controller implements three types of Clean &
1196 Invalidate maintenance operations: by Physical Address
1197 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1198 They are architecturally defined to behave as the execution of a
1199 clean operation followed immediately by an invalidate operation,
1200 both performing to the same memory location. This functionality
1201 is not correctly implemented in PL310 as clean lines are not
2839e06c 1202 invalidated as a result of these operations.
cdf357f1
WD
1203
1204config ARM_ERRATA_720789
1205 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
e66dc745 1206 depends on CPU_V7
cdf357f1
WD
1207 help
1208 This option enables the workaround for the 720789 Cortex-A9 (prior to
1209 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1210 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1211 As a consequence of this erratum, some TLB entries which should be
1212 invalidated are not, resulting in an incoherency in the system page
1213 tables. The workaround changes the TLB flushing routines to invalidate
1214 entries regardless of the ASID.
475d92fc 1215
1f0090a1 1216config PL310_ERRATA_727915
fa0ce403 1217 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1f0090a1
RK
1218 depends on CACHE_L2X0
1219 help
1220 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1221 operation (offset 0x7FC). This operation runs in background so that
1222 PL310 can handle normal accesses while it is in progress. Under very
1223 rare circumstances, due to this erratum, write data can be lost when
1224 PL310 treats a cacheable write transaction during a Clean &
1225 Invalidate by Way operation.
1226
475d92fc
WD
1227config ARM_ERRATA_743622
1228 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1229 depends on CPU_V7
62e4d357 1230 depends on !ARCH_MULTIPLATFORM
475d92fc
WD
1231 help
1232 This option enables the workaround for the 743622 Cortex-A9
efbc74ac 1233 (r2p*) erratum. Under very rare conditions, a faulty
475d92fc
WD
1234 optimisation in the Cortex-A9 Store Buffer may lead to data
1235 corruption. This workaround sets a specific bit in the diagnostic
1236 register of the Cortex-A9 which disables the Store Buffer
1237 optimisation, preventing the defect from occurring. This has no
1238 visible impact on the overall performance or power consumption of the
1239 processor.
1240
9a27c27c
WD
1241config ARM_ERRATA_751472
1242 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
ba90c516 1243 depends on CPU_V7
62e4d357 1244 depends on !ARCH_MULTIPLATFORM
9a27c27c
WD
1245 help
1246 This option enables the workaround for the 751472 Cortex-A9 (prior
1247 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1248 completion of a following broadcasted operation if the second
1249 operation is received by a CPU before the ICIALLUIS has completed,
1250 potentially leading to corrupted entries in the cache or TLB.
1251
fa0ce403
WD
1252config PL310_ERRATA_753970
1253 bool "PL310 errata: cache sync operation may be faulty"
885028e4
SK
1254 depends on CACHE_PL310
1255 help
1256 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1257
1258 Under some condition the effect of cache sync operation on
1259 the store buffer still remains when the operation completes.
1260 This means that the store buffer is always asked to drain and
1261 this prevents it from merging any further writes. The workaround
1262 is to replace the normal offset of cache sync operation (0x730)
1263 by another offset targeting an unmapped PL310 register 0x740.
1264 This has the same effect as the cache sync operation: store buffer
1265 drain and waiting for all buffers empty.
1266
fcbdc5fe
WD
1267config ARM_ERRATA_754322
1268 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1269 depends on CPU_V7
1270 help
1271 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1272 r3p*) erratum. A speculative memory access may cause a page table walk
1273 which starts prior to an ASID switch but completes afterwards. This
1274 can populate the micro-TLB with a stale entry which may be hit with
1275 the new ASID. This workaround places two dsb instructions in the mm
1276 switching code so that no page table walks can cross the ASID switch.
1277
5dab26af
WD
1278config ARM_ERRATA_754327
1279 bool "ARM errata: no automatic Store Buffer drain"
1280 depends on CPU_V7 && SMP
1281 help
1282 This option enables the workaround for the 754327 Cortex-A9 (prior to
1283 r2p0) erratum. The Store Buffer does not have any automatic draining
1284 mechanism and therefore a livelock may occur if an external agent
1285 continuously polls a memory location waiting to observe an update.
1286 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1287 written polling loops from denying visibility of updates to memory.
1288
145e10e1
CM
1289config ARM_ERRATA_364296
1290 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1291 depends on CPU_V6 && !SMP
1292 help
1293 This options enables the workaround for the 364296 ARM1136
1294 r0p2 erratum (possible cache data corruption with
1295 hit-under-miss enabled). It sets the undocumented bit 31 in
1296 the auxiliary control register and the FI bit in the control
1297 register, thus disabling hit-under-miss without putting the
1298 processor into full low interrupt latency mode. ARM11MPCore
1299 is not affected.
1300
f630c1bd
WD
1301config ARM_ERRATA_764369
1302 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1303 depends on CPU_V7 && SMP
1304 help
1305 This option enables the workaround for erratum 764369
1306 affecting Cortex-A9 MPCore with two or more processors (all
1307 current revisions). Under certain timing circumstances, a data
1308 cache line maintenance operation by MVA targeting an Inner
1309 Shareable memory region may fail to proceed up to either the
1310 Point of Coherency or to the Point of Unification of the
1311 system. This workaround adds a DSB instruction before the
1312 relevant cache maintenance functions and sets a specific bit
1313 in the diagnostic control register of the SCU.
1314
11ed0ba1
WD
1315config PL310_ERRATA_769419
1316 bool "PL310 errata: no automatic Store Buffer drain"
1317 depends on CACHE_L2X0
1318 help
1319 On revisions of the PL310 prior to r3p2, the Store Buffer does
1320 not automatically drain. This can cause normal, non-cacheable
1321 writes to be retained when the memory system is idle, leading
1322 to suboptimal I/O performance for drivers using coherent DMA.
1323 This option adds a write barrier to the cpu_idle loop so that,
1324 on systems with an outer cache, the store buffer is drained
1325 explicitly.
1326
7253b85c
SH
1327config ARM_ERRATA_775420
1328 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1329 depends on CPU_V7
1330 help
1331 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1332 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1333 operation aborts with MMU exception, it might cause the processor
1334 to deadlock. This workaround puts DSB before executing ISB if
1335 an abort may occur on cache maintenance.
1336
93dc6887
CM
1337config ARM_ERRATA_798181
1338 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1339 depends on CPU_V7 && SMP
1340 help
1341 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1342 adequately shooting down all use of the old entries. This
1343 option enables the Linux kernel workaround for this erratum
1344 which sends an IPI to the CPUs that are running the same ASID
1345 as the one being invalidated.
1346
1da177e4
LT
1347endmenu
1348
1349source "arch/arm/common/Kconfig"
1350
1da177e4
LT
1351menu "Bus support"
1352
1353config ARM_AMBA
1354 bool
1355
1356config ISA
1357 bool
1da177e4
LT
1358 help
1359 Find out whether you have ISA slots on your motherboard. ISA is the
1360 name of a bus system, i.e. the way the CPU talks to the other stuff
1361 inside your box. Other bus systems are PCI, EISA, MicroChannel
1362 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1363 newer boards don't support it. If you have ISA, say Y, otherwise N.
1364
065909b9 1365# Select ISA DMA controller support
1da177e4
LT
1366config ISA_DMA
1367 bool
065909b9 1368 select ISA_DMA_API
1da177e4 1369
065909b9 1370# Select ISA DMA interface
5cae841b
AV
1371config ISA_DMA_API
1372 bool
5cae841b 1373
1da177e4 1374config PCI
0b05da72 1375 bool "PCI support" if MIGHT_HAVE_PCI
1da177e4
LT
1376 help
1377 Find out whether you have a PCI motherboard. PCI is the name of a
1378 bus system, i.e. the way the CPU talks to the other stuff inside
1379 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1380 VESA. If you have PCI, say Y, otherwise N.
1381
52882173
AV
1382config PCI_DOMAINS
1383 bool
1384 depends on PCI
1385
b080ac8a
MRJ
1386config PCI_NANOENGINE
1387 bool "BSE nanoEngine PCI support"
1388 depends on SA1100_NANOENGINE
1389 help
1390 Enable PCI on the BSE nanoEngine board.
1391
36e23590
MW
1392config PCI_SYSCALL
1393 def_bool PCI
1394
1da177e4
LT
1395# Select the host bridge type
1396config PCI_HOST_VIA82C505
1397 bool
1398 depends on PCI && ARCH_SHARK
1399 default y
1400
a0113a99
MR
1401config PCI_HOST_ITE8152
1402 bool
1403 depends on PCI && MACH_ARMCORE
1404 default y
1405 select DMABOUNCE
1406
1da177e4
LT
1407source "drivers/pci/Kconfig"
1408
1409source "drivers/pcmcia/Kconfig"
1410
1411endmenu
1412
1413menu "Kernel Features"
1414
3b55658a
DM
1415config HAVE_SMP
1416 bool
1417 help
1418 This option should be selected by machines which have an SMP-
1419 capable CPU.
1420
1421 The only effect of this option is to make the SMP-related
1422 options available to the user for configuration.
1423
1da177e4 1424config SMP
bb2d8130 1425 bool "Symmetric Multi-Processing"
fbb4ddac 1426 depends on CPU_V6K || CPU_V7
bc28248e 1427 depends on GENERIC_CLOCKEVENTS
3b55658a 1428 depends on HAVE_SMP
9934ebb8 1429 depends on MMU
b1b3f49c 1430 select USE_GENERIC_SMP_HELPERS
1da177e4
LT
1431 help
1432 This enables support for systems with more than one CPU. If you have
1433 a system with only one CPU, like most personal computers, say N. If
1434 you have a system with more than one CPU, say Y.
1435
1436 If you say N here, the kernel will run on single and multiprocessor
1437 machines, but will use only one CPU of a multiprocessor machine. If
1438 you say Y here, the kernel will run on many, but not all, single
1439 processor machines. On a single processor machine, the kernel will
1440 run faster if you say N here.
1441
395cf969 1442 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1da177e4 1443 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
50a23e6e 1444 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1da177e4
LT
1445
1446 If you don't know what to do here, say N.
1447
f00ec48f
RK
1448config SMP_ON_UP
1449 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
4d2692a7 1450 depends on SMP && !XIP_KERNEL
f00ec48f
RK
1451 default y
1452 help
1453 SMP kernels contain instructions which fail on non-SMP processors.
1454 Enabling this option allows the kernel to modify itself to make
1455 these instructions safe. Disabling it allows about 1K of space
1456 savings.
1457
1458 If you don't know what to do here, say Y.
1459
c9018aab
VG
1460config ARM_CPU_TOPOLOGY
1461 bool "Support cpu topology definition"
1462 depends on SMP && CPU_V7
1463 default y
1464 help
1465 Support ARM cpu topology definition. The MPIDR register defines
1466 affinity between processors which is then used to describe the cpu
1467 topology of an ARM System.
1468
1469config SCHED_MC
1470 bool "Multi-core scheduler support"
1471 depends on ARM_CPU_TOPOLOGY
1472 help
1473 Multi-core scheduler support improves the CPU scheduler's decision
1474 making when dealing with multi-core CPU chips at a cost of slightly
1475 increased overhead in some places. If unsure say N here.
1476
1477config SCHED_SMT
1478 bool "SMT scheduler support"
1479 depends on ARM_CPU_TOPOLOGY
1480 help
1481 Improves the CPU scheduler's decision making when dealing with
1482 MultiThreading at a cost of slightly increased overhead in some
1483 places. If unsure say N here.
1484
a8cbcd92
RK
1485config HAVE_ARM_SCU
1486 bool
a8cbcd92
RK
1487 help
1488 This option enables support for the ARM system coherency unit
1489
8a4da6e3 1490config HAVE_ARM_ARCH_TIMER
022c03a2
MZ
1491 bool "Architected timer support"
1492 depends on CPU_V7
8a4da6e3 1493 select ARM_ARCH_TIMER
022c03a2
MZ
1494 help
1495 This option enables support for the ARM architected timer
1496
f32f4ce2
RK
1497config HAVE_ARM_TWD
1498 bool
1499 depends on SMP
da4a686a 1500 select CLKSRC_OF if OF
f32f4ce2
RK
1501 help
1502 This options enables support for the ARM timer and watchdog unit
1503
e8db288e
NP
1504config MCPM
1505 bool "Multi-Cluster Power Management"
1506 depends on CPU_V7 && SMP
1507 help
1508 This option provides the common power management infrastructure
1509 for (multi-)cluster based systems, such as big.LITTLE based
1510 systems.
1511
8d5796d2
LB
1512choice
1513 prompt "Memory split"
1514 default VMSPLIT_3G
1515 help
1516 Select the desired split between kernel and user memory.
1517
1518 If you are not absolutely sure what you are doing, leave this
1519 option alone!
1520
1521 config VMSPLIT_3G
1522 bool "3G/1G user/kernel split"
1523 config VMSPLIT_2G
1524 bool "2G/2G user/kernel split"
1525 config VMSPLIT_1G
1526 bool "1G/3G user/kernel split"
1527endchoice
1528
1529config PAGE_OFFSET
1530 hex
1531 default 0x40000000 if VMSPLIT_1G
1532 default 0x80000000 if VMSPLIT_2G
1533 default 0xC0000000
1534
1da177e4
LT
1535config NR_CPUS
1536 int "Maximum number of CPUs (2-32)"
1537 range 2 32
1538 depends on SMP
1539 default "4"
1540
a054a811 1541config HOTPLUG_CPU
00b7dede
RK
1542 bool "Support for hot-pluggable CPUs"
1543 depends on SMP && HOTPLUG
a054a811
RK
1544 help
1545 Say Y here to experiment with turning CPUs off and on. CPUs
1546 can be controlled through /sys/devices/system/cpu.
1547
2bdd424f
WD
1548config ARM_PSCI
1549 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1550 depends on CPU_V7
1551 help
1552 Say Y here if you want Linux to communicate with system firmware
1553 implementing the PSCI specification for CPU-centric power
1554 management operations described in ARM document number ARM DEN
1555 0022A ("Power State Coordination Interface System Software on
1556 ARM processors").
1557
37ee16ae
RK
1558config LOCAL_TIMERS
1559 bool "Use local timer interrupts"
971acb9b 1560 depends on SMP
37ee16ae
RK
1561 default y
1562 help
1563 Enable support for local timers on SMP platforms, rather then the
1564 legacy IPI broadcast method. Local timers allows the system
1565 accounting to be spread across the timer interval, preventing a
1566 "thundering herd" at every timer tick.
1567
2a6ad871
MR
1568# The GPIO number here must be sorted by descending number. In case of
1569# a multiplatform kernel, we just want the highest value required by the
1570# selected platforms.
44986ab0
PDSN
1571config ARCH_NR_GPIO
1572 int
3dea19e8 1573 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
39f47d9f 1574 default 512 if SOC_OMAP5
06b851e5 1575 default 392 if ARCH_U8500
01bb914c
TP
1576 default 352 if ARCH_VT8500
1577 default 288 if ARCH_SUNXI
2a6ad871 1578 default 264 if MACH_H4700
44986ab0
PDSN
1579 default 0
1580 help
1581 Maximum number of GPIOs in the system.
1582
1583 If unsure, leave the default value.
1584
d45a398f 1585source kernel/Kconfig.preempt
1da177e4 1586
f8065813
RK
1587config HZ
1588 int
b130d5c2 1589 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
a73ddc61 1590 ARCH_S5PV210 || ARCH_EXYNOS4
5248c657 1591 default AT91_TIMER_HZ if ARCH_AT91
5da3e714 1592 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
f8065813
RK
1593 default 100
1594
b28748fb
RK
1595config SCHED_HRTICK
1596 def_bool HIGH_RES_TIMERS
1597
16c79651 1598config THUMB2_KERNEL
bc7dea00 1599 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
00b7dede 1600 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
bc7dea00 1601 default y if CPU_THUMBONLY
16c79651
CM
1602 select AEABI
1603 select ARM_ASM_UNIFIED
89bace65 1604 select ARM_UNWIND
16c79651
CM
1605 help
1606 By enabling this option, the kernel will be compiled in
1607 Thumb-2 mode. A compiler/assembler that understand the unified
1608 ARM-Thumb syntax is needed.
1609
1610 If unsure, say N.
1611
6f685c5c
DM
1612config THUMB2_AVOID_R_ARM_THM_JUMP11
1613 bool "Work around buggy Thumb-2 short branch relocations in gas"
1614 depends on THUMB2_KERNEL && MODULES
1615 default y
1616 help
1617 Various binutils versions can resolve Thumb-2 branches to
1618 locally-defined, preemptible global symbols as short-range "b.n"
1619 branch instructions.
1620
1621 This is a problem, because there's no guarantee the final
1622 destination of the symbol, or any candidate locations for a
1623 trampoline, are within range of the branch. For this reason, the
1624 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1625 relocation in modules at all, and it makes little sense to add
1626 support.
1627
1628 The symptom is that the kernel fails with an "unsupported
1629 relocation" error when loading some modules.
1630
1631 Until fixed tools are available, passing
1632 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1633 code which hits this problem, at the cost of a bit of extra runtime
1634 stack usage in some cases.
1635
1636 The problem is described in more detail at:
1637 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1638
1639 Only Thumb-2 kernels are affected.
1640
1641 Unless you are sure your tools don't have this problem, say Y.
1642
0becb088
CM
1643config ARM_ASM_UNIFIED
1644 bool
1645
704bdda0
NP
1646config AEABI
1647 bool "Use the ARM EABI to compile the kernel"
1648 help
1649 This option allows for the kernel to be compiled using the latest
1650 ARM ABI (aka EABI). This is only useful if you are using a user
1651 space environment that is also compiled with EABI.
1652
1653 Since there are major incompatibilities between the legacy ABI and
1654 EABI, especially with regard to structure member alignment, this
1655 option also changes the kernel syscall calling convention to
1656 disambiguate both ABIs and allow for backward compatibility support
1657 (selected with CONFIG_OABI_COMPAT).
1658
1659 To use this you need GCC version 4.0.0 or later.
1660
6c90c872 1661config OABI_COMPAT
a73a3ff1 1662 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
d6f94fa0 1663 depends on AEABI && !THUMB2_KERNEL
6c90c872
NP
1664 default y
1665 help
1666 This option preserves the old syscall interface along with the
1667 new (ARM EABI) one. It also provides a compatibility layer to
1668 intercept syscalls that have structure arguments which layout
1669 in memory differs between the legacy ABI and the new ARM EABI
1670 (only for non "thumb" binaries). This option adds a tiny
1671 overhead to all syscalls and produces a slightly larger kernel.
1672 If you know you'll be using only pure EABI user space then you
1673 can say N here. If this option is not selected and you attempt
1674 to execute a legacy ABI binary then the result will be
1675 UNPREDICTABLE (in fact it can be predicted that it won't work
1676 at all). If in doubt say Y.
1677
eb33575c 1678config ARCH_HAS_HOLES_MEMORYMODEL
e80d6a24 1679 bool
e80d6a24 1680
05944d74
RK
1681config ARCH_SPARSEMEM_ENABLE
1682 bool
1683
07a2f737
RK
1684config ARCH_SPARSEMEM_DEFAULT
1685 def_bool ARCH_SPARSEMEM_ENABLE
1686
05944d74 1687config ARCH_SELECT_MEMORY_MODEL
be370302 1688 def_bool ARCH_SPARSEMEM_ENABLE
c80d79d7 1689
7b7bf499
WD
1690config HAVE_ARCH_PFN_VALID
1691 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1692
053a96ca 1693config HIGHMEM
e8db89a2
RK
1694 bool "High Memory Support"
1695 depends on MMU
053a96ca
NP
1696 help
1697 The address space of ARM processors is only 4 Gigabytes large
1698 and it has to accommodate user address space, kernel address
1699 space as well as some memory mapped IO. That means that, if you
1700 have a large amount of physical memory and/or IO, not all of the
1701 memory can be "permanently mapped" by the kernel. The physical
1702 memory that is not permanently mapped is called "high memory".
1703
1704 Depending on the selected kernel/user memory split, minimum
1705 vmalloc space and actual amount of RAM, you may not need this
1706 option which should result in a slightly faster kernel.
1707
1708 If unsure, say n.
1709
65cec8e3
RK
1710config HIGHPTE
1711 bool "Allocate 2nd-level pagetables from highmem"
1712 depends on HIGHMEM
65cec8e3 1713
1b8873a0
JI
1714config HW_PERF_EVENTS
1715 bool "Enable hardware performance counter support for perf events"
f0d1bc47 1716 depends on PERF_EVENTS
1b8873a0
JI
1717 default y
1718 help
1719 Enable hardware performance counter support for perf events. If
1720 disabled, perf events will use software events only.
1721
3f22ab27
DH
1722source "mm/Kconfig"
1723
c1b2d970
MD
1724config FORCE_MAX_ZONEORDER
1725 int "Maximum zone order" if ARCH_SHMOBILE
1726 range 11 64 if ARCH_SHMOBILE
898f08e1 1727 default "12" if SOC_AM33XX
c1b2d970
MD
1728 default "9" if SA1111
1729 default "11"
1730 help
1731 The kernel memory allocator divides physically contiguous memory
1732 blocks into "zones", where each zone is a power of two number of
1733 pages. This option selects the largest power of two that the kernel
1734 keeps in the memory allocator. If you need to allocate very large
1735 blocks of physically contiguous memory, then you may need to
1736 increase this value.
1737
1738 This config option is actually maximum order plus one. For example,
1739 a value of 11 means that the largest free memory block is 2^10 pages.
1740
1da177e4
LT
1741config ALIGNMENT_TRAP
1742 bool
f12d0d7c 1743 depends on CPU_CP15_MMU
1da177e4 1744 default y if !ARCH_EBSA110
e119bfff 1745 select HAVE_PROC_CPU if PROC_FS
1da177e4 1746 help
84eb8d06 1747 ARM processors cannot fetch/store information which is not
1da177e4
LT
1748 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1749 address divisible by 4. On 32-bit ARM processors, these non-aligned
1750 fetch/store instructions will be emulated in software if you say
1751 here, which has a severe performance impact. This is necessary for
1752 correct operation of some network protocols. With an IP-only
1753 configuration it is safe to say N, otherwise say Y.
1754
39ec58f3 1755config UACCESS_WITH_MEMCPY
38ef2ad5
LW
1756 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1757 depends on MMU
39ec58f3
LB
1758 default y if CPU_FEROCEON
1759 help
1760 Implement faster copy_to_user and clear_user methods for CPU
1761 cores where a 8-word STM instruction give significantly higher
1762 memory write throughput than a sequence of individual 32bit stores.
1763
1764 A possible side effect is a slight increase in scheduling latency
1765 between threads sharing the same address space if they invoke
1766 such copy operations with large buffers.
1767
1768 However, if the CPU data cache is using a write-allocate mode,
1769 this option is unlikely to provide any performance gain.
1770
70c70d97
NP
1771config SECCOMP
1772 bool
1773 prompt "Enable seccomp to safely compute untrusted bytecode"
1774 ---help---
1775 This kernel feature is useful for number crunching applications
1776 that may need to compute untrusted bytecode during their
1777 execution. By using pipes or other transports made available to
1778 the process as file descriptors supporting the read/write
1779 syscalls, it's possible to isolate those applications in
1780 their own address space using seccomp. Once seccomp is
1781 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1782 and the task is only allowed to execute a few safe syscalls
1783 defined by each seccomp mode.
1784
c743f380
NP
1785config CC_STACKPROTECTOR
1786 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1787 help
1788 This option turns on the -fstack-protector GCC feature. This
1789 feature puts, at the beginning of functions, a canary value on
1790 the stack just before the return address, and validates
1791 the value just before actually returning. Stack based buffer
1792 overflows (that need to overwrite this return address) now also
1793 overwrite the canary, which gets detected and the attack is then
1794 neutralized via a kernel panic.
1795 This feature requires gcc version 4.2 or above.
1796
eff8d644
SS
1797config XEN_DOM0
1798 def_bool y
1799 depends on XEN
1800
1801config XEN
1802 bool "Xen guest support on ARM (EXPERIMENTAL)"
85323a99 1803 depends on ARM && AEABI && OF
f880b67d 1804 depends on CPU_V7 && !CPU_V6
85323a99 1805 depends on !GENERIC_ATOMIC64
17b7ab80 1806 select ARM_PSCI
eff8d644
SS
1807 help
1808 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1809
1da177e4
LT
1810endmenu
1811
1812menu "Boot options"
1813
9eb8f674
GL
1814config USE_OF
1815 bool "Flattened Device Tree support"
b1b3f49c 1816 select IRQ_DOMAIN
9eb8f674
GL
1817 select OF
1818 select OF_EARLY_FLATTREE
1819 help
1820 Include support for flattened device tree machine descriptions.
1821
bd51e2f5
NP
1822config ATAGS
1823 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1824 default y
1825 help
1826 This is the traditional way of passing data to the kernel at boot
1827 time. If you are solely relying on the flattened device tree (or
1828 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1829 to remove ATAGS support from your kernel binary. If unsure,
1830 leave this to y.
1831
1832config DEPRECATED_PARAM_STRUCT
1833 bool "Provide old way to pass kernel parameters"
1834 depends on ATAGS
1835 help
1836 This was deprecated in 2001 and announced to live on for 5 years.
1837 Some old boot loaders still use this way.
1838
1da177e4
LT
1839# Compressed boot loader in ROM. Yes, we really want to ask about
1840# TEXT and BSS so we preserve their values in the config files.
1841config ZBOOT_ROM_TEXT
1842 hex "Compressed ROM boot loader base address"
1843 default "0"
1844 help
1845 The physical address at which the ROM-able zImage is to be
1846 placed in the target. Platforms which normally make use of
1847 ROM-able zImage formats normally set this to a suitable
1848 value in their defconfig file.
1849
1850 If ZBOOT_ROM is not enabled, this has no effect.
1851
1852config ZBOOT_ROM_BSS
1853 hex "Compressed ROM boot loader BSS address"
1854 default "0"
1855 help
f8c440b2
DF
1856 The base address of an area of read/write memory in the target
1857 for the ROM-able zImage which must be available while the
1858 decompressor is running. It must be large enough to hold the
1859 entire decompressed kernel plus an additional 128 KiB.
1860 Platforms which normally make use of ROM-able zImage formats
1861 normally set this to a suitable value in their defconfig file.
1da177e4
LT
1862
1863 If ZBOOT_ROM is not enabled, this has no effect.
1864
1865config ZBOOT_ROM
1866 bool "Compressed boot loader in ROM/flash"
1867 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1868 help
1869 Say Y here if you intend to execute your compressed kernel image
1870 (zImage) directly from ROM or flash. If unsure, say N.
1871
090ab3ff
SH
1872choice
1873 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
d6f94fa0 1874 depends on ZBOOT_ROM && ARCH_SH7372
090ab3ff
SH
1875 default ZBOOT_ROM_NONE
1876 help
1877 Include experimental SD/MMC loading code in the ROM-able zImage.
59bf8964 1878 With this enabled it is possible to write the ROM-able zImage
090ab3ff
SH
1879 kernel image to an MMC or SD card and boot the kernel straight
1880 from the reset vector. At reset the processor Mask ROM will load
59bf8964 1881 the first part of the ROM-able zImage which in turn loads the
090ab3ff
SH
1882 rest the kernel image to RAM.
1883
1884config ZBOOT_ROM_NONE
1885 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1886 help
1887 Do not load image from SD or MMC
1888
f45b1149
SH
1889config ZBOOT_ROM_MMCIF
1890 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
f45b1149 1891 help
090ab3ff
SH
1892 Load image from MMCIF hardware block.
1893
1894config ZBOOT_ROM_SH_MOBILE_SDHI
1895 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1896 help
1897 Load image from SDHI hardware block
1898
1899endchoice
f45b1149 1900
e2a6a3aa
JB
1901config ARM_APPENDED_DTB
1902 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
d6f94fa0 1903 depends on OF && !ZBOOT_ROM
e2a6a3aa
JB
1904 help
1905 With this option, the boot code will look for a device tree binary
1906 (DTB) appended to zImage
1907 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1908
1909 This is meant as a backward compatibility convenience for those
1910 systems with a bootloader that can't be upgraded to accommodate
1911 the documented boot protocol using a device tree.
1912
1913 Beware that there is very little in terms of protection against
1914 this option being confused by leftover garbage in memory that might
1915 look like a DTB header after a reboot if no actual DTB is appended
1916 to zImage. Do not leave this option active in a production kernel
1917 if you don't intend to always append a DTB. Proper passing of the
1918 location into r2 of a bootloader provided DTB is always preferable
1919 to this option.
1920
b90b9a38
NP
1921config ARM_ATAG_DTB_COMPAT
1922 bool "Supplement the appended DTB with traditional ATAG information"
1923 depends on ARM_APPENDED_DTB
1924 help
1925 Some old bootloaders can't be updated to a DTB capable one, yet
1926 they provide ATAGs with memory configuration, the ramdisk address,
1927 the kernel cmdline string, etc. Such information is dynamically
1928 provided by the bootloader and can't always be stored in a static
1929 DTB. To allow a device tree enabled kernel to be used with such
1930 bootloaders, this option allows zImage to extract the information
1931 from the ATAG list and store it at run time into the appended DTB.
1932
d0f34a11
GR
1933choice
1934 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1935 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1936
1937config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1938 bool "Use bootloader kernel arguments if available"
1939 help
1940 Uses the command-line options passed by the boot loader instead of
1941 the device tree bootargs property. If the boot loader doesn't provide
1942 any, the device tree bootargs property will be used.
1943
1944config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1945 bool "Extend with bootloader kernel arguments"
1946 help
1947 The command-line arguments provided by the boot loader will be
1948 appended to the the device tree bootargs property.
1949
1950endchoice
1951
1da177e4
LT
1952config CMDLINE
1953 string "Default kernel command string"
1954 default ""
1955 help
1956 On some architectures (EBSA110 and CATS), there is currently no way
1957 for the boot loader to pass arguments to the kernel. For these
1958 architectures, you should supply some command-line options at build
1959 time by entering them here. As a minimum, you should specify the
1960 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1961
4394c124
VB
1962choice
1963 prompt "Kernel command line type" if CMDLINE != ""
1964 default CMDLINE_FROM_BOOTLOADER
bd51e2f5 1965 depends on ATAGS
4394c124
VB
1966
1967config CMDLINE_FROM_BOOTLOADER
1968 bool "Use bootloader kernel arguments if available"
1969 help
1970 Uses the command-line options passed by the boot loader. If
1971 the boot loader doesn't provide any, the default kernel command
1972 string provided in CMDLINE will be used.
1973
1974config CMDLINE_EXTEND
1975 bool "Extend bootloader kernel arguments"
1976 help
1977 The command-line arguments provided by the boot loader will be
1978 appended to the default kernel command string.
1979
92d2040d
AH
1980config CMDLINE_FORCE
1981 bool "Always use the default kernel command string"
92d2040d
AH
1982 help
1983 Always use the default kernel command string, even if the boot
1984 loader passes other arguments to the kernel.
1985 This is useful if you cannot or don't want to change the
1986 command-line options your boot loader passes to the kernel.
4394c124 1987endchoice
92d2040d 1988
1da177e4
LT
1989config XIP_KERNEL
1990 bool "Kernel Execute-In-Place from ROM"
387798b3 1991 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
1da177e4
LT
1992 help
1993 Execute-In-Place allows the kernel to run from non-volatile storage
1994 directly addressable by the CPU, such as NOR flash. This saves RAM
1995 space since the text section of the kernel is not loaded from flash
1996 to RAM. Read-write sections, such as the data section and stack,
1997 are still copied to RAM. The XIP kernel is not compressed since
1998 it has to run directly from flash, so it will take more space to
1999 store it. The flash address used to link the kernel object files,
2000 and for storing it, is configuration dependent. Therefore, if you
2001 say Y here, you must know the proper physical address where to
2002 store the kernel image depending on your own flash memory usage.
2003
2004 Also note that the make target becomes "make xipImage" rather than
2005 "make zImage" or "make Image". The final kernel binary to put in
2006 ROM memory will be arch/arm/boot/xipImage.
2007
2008 If unsure, say N.
2009
2010config XIP_PHYS_ADDR
2011 hex "XIP Kernel Physical Location"
2012 depends on XIP_KERNEL
2013 default "0x00080000"
2014 help
2015 This is the physical address in your flash memory the kernel will
2016 be linked for and stored to. This address is dependent on your
2017 own flash usage.
2018
c587e4a6
RP
2019config KEXEC
2020 bool "Kexec system call (EXPERIMENTAL)"
d6f94fa0 2021 depends on (!SMP || HOTPLUG_CPU)
c587e4a6
RP
2022 help
2023 kexec is a system call that implements the ability to shutdown your
2024 current kernel, and to start another kernel. It is like a reboot
01dd2fbf 2025 but it is independent of the system firmware. And like a reboot
c587e4a6
RP
2026 you can start any kernel with it, not just Linux.
2027
2028 It is an ongoing process to be certain the hardware in a machine
2029 is properly shutdown, so do not be surprised if this code does not
2030 initially work for you. It may help to enable device hotplugging
2031 support.
2032
4cd9d6f7
RP
2033config ATAGS_PROC
2034 bool "Export atags in procfs"
bd51e2f5 2035 depends on ATAGS && KEXEC
b98d7291 2036 default y
4cd9d6f7
RP
2037 help
2038 Should the atags used to boot the kernel be exported in an "atags"
2039 file in procfs. Useful with kexec.
2040
cb5d39b3
MW
2041config CRASH_DUMP
2042 bool "Build kdump crash kernel (EXPERIMENTAL)"
cb5d39b3
MW
2043 help
2044 Generate crash dump after being started by kexec. This should
2045 be normally only set in special crash dump kernels which are
2046 loaded in the main kernel with kexec-tools into a specially
2047 reserved region and then later executed after a crash by
2048 kdump/kexec. The crash dump kernel must be compiled to a
2049 memory address not used by the main kernel
2050
2051 For more details see Documentation/kdump/kdump.txt
2052
e69edc79
EM
2053config AUTO_ZRELADDR
2054 bool "Auto calculation of the decompressed kernel image address"
2055 depends on !ZBOOT_ROM && !ARCH_U300
2056 help
2057 ZRELADDR is the physical address where the decompressed kernel
2058 image will be placed. If AUTO_ZRELADDR is selected, the address
2059 will be determined at run-time by masking the current IP with
2060 0xf8000000. This assumes the zImage being placed in the first 128MB
2061 from start of memory.
2062
1da177e4
LT
2063endmenu
2064
ac9d7efc 2065menu "CPU Power Management"
1da177e4 2066
89c52ed4 2067if ARCH_HAS_CPUFREQ
1da177e4
LT
2068source "drivers/cpufreq/Kconfig"
2069
9d56c02a
BD
2070config CPU_FREQ_S3C
2071 bool
2072 help
2073 Internal configuration node for common cpufreq on Samsung SoC
2074
2075config CPU_FREQ_S3C24XX
4a50bfe3 2076 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
d6f94fa0 2077 depends on ARCH_S3C24XX && CPU_FREQ
9d56c02a
BD
2078 select CPU_FREQ_S3C
2079 help
2080 This enables the CPUfreq driver for the Samsung S3C24XX family
2081 of CPUs.
2082
2083 For details, take a look at <file:Documentation/cpu-freq>.
2084
2085 If in doubt, say N.
2086
2087config CPU_FREQ_S3C24XX_PLL
4a50bfe3 2088 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
d6f94fa0 2089 depends on CPU_FREQ_S3C24XX
9d56c02a
BD
2090 help
2091 Compile in support for changing the PLL frequency from the
2092 S3C24XX series CPUfreq driver. The PLL takes time to settle
2093 after a frequency change, so by default it is not enabled.
2094
2095 This also means that the PLL tables for the selected CPU(s) will
2096 be built which may increase the size of the kernel image.
2097
2098config CPU_FREQ_S3C24XX_DEBUG
2099 bool "Debug CPUfreq Samsung driver core"
2100 depends on CPU_FREQ_S3C24XX
2101 help
2102 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2103
2104config CPU_FREQ_S3C24XX_IODEBUG
2105 bool "Debug CPUfreq Samsung driver IO timing"
2106 depends on CPU_FREQ_S3C24XX
2107 help
2108 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2109
e6d197a6
BD
2110config CPU_FREQ_S3C24XX_DEBUGFS
2111 bool "Export debugfs for CPUFreq"
2112 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2113 help
2114 Export status information via debugfs.
2115
1da177e4
LT
2116endif
2117
ac9d7efc
RK
2118source "drivers/cpuidle/Kconfig"
2119
2120endmenu
2121
1da177e4
LT
2122menu "Floating point emulation"
2123
2124comment "At least one emulation must be selected"
2125
2126config FPE_NWFPE
2127 bool "NWFPE math emulation"
593c252a 2128 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1da177e4
LT
2129 ---help---
2130 Say Y to include the NWFPE floating point emulator in the kernel.
2131 This is necessary to run most binaries. Linux does not currently
2132 support floating point hardware so you need to say Y here even if
2133 your machine has an FPA or floating point co-processor podule.
2134
2135 You may say N here if you are going to load the Acorn FPEmulator
2136 early in the bootup.
2137
2138config FPE_NWFPE_XP
2139 bool "Support extended precision"
bedf142b 2140 depends on FPE_NWFPE
1da177e4
LT
2141 help
2142 Say Y to include 80-bit support in the kernel floating-point
2143 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2144 Note that gcc does not generate 80-bit operations by default,
2145 so in most cases this option only enlarges the size of the
2146 floating point emulator without any good reason.
2147
2148 You almost surely want to say N here.
2149
2150config FPE_FASTFPE
2151 bool "FastFPE math emulation (EXPERIMENTAL)"
d6f94fa0 2152 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1da177e4
LT
2153 ---help---
2154 Say Y here to include the FAST floating point emulator in the kernel.
2155 This is an experimental much faster emulator which now also has full
2156 precision for the mantissa. It does not support any exceptions.
2157 It is very simple, and approximately 3-6 times faster than NWFPE.
2158
2159 It should be sufficient for most programs. It may be not suitable
2160 for scientific calculations, but you have to check this for yourself.
2161 If you do not feel you need a faster FP emulation you should better
2162 choose NWFPE.
2163
2164config VFP
2165 bool "VFP-format floating point maths"
e399b1a4 2166 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1da177e4
LT
2167 help
2168 Say Y to include VFP support code in the kernel. This is needed
2169 if your hardware includes a VFP unit.
2170
2171 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2172 release notes and additional status information.
2173
2174 Say N if your target does not have VFP hardware.
2175
25ebee02
CM
2176config VFPv3
2177 bool
2178 depends on VFP
2179 default y if CPU_V7
2180
b5872db4
CM
2181config NEON
2182 bool "Advanced SIMD (NEON) Extension support"
2183 depends on VFPv3 && CPU_V7
2184 help
2185 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2186 Extension.
2187
1da177e4
LT
2188endmenu
2189
2190menu "Userspace binary formats"
2191
2192source "fs/Kconfig.binfmt"
2193
2194config ARTHUR
2195 tristate "RISC OS personality"
704bdda0 2196 depends on !AEABI
1da177e4
LT
2197 help
2198 Say Y here to include the kernel code necessary if you want to run
2199 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2200 experimental; if this sounds frightening, say N and sleep in peace.
2201 You can also say M here to compile this support as a module (which
2202 will be called arthur).
2203
2204endmenu
2205
2206menu "Power management options"
2207
eceab4ac 2208source "kernel/power/Kconfig"
1da177e4 2209
f4cb5700 2210config ARCH_SUSPEND_POSSIBLE
4b1082ca 2211 depends on !ARCH_S5PC100
6a786182 2212 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
3f5d0819 2213 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
f4cb5700
JB
2214 def_bool y
2215
15e0d9e3
AB
2216config ARM_CPU_SUSPEND
2217 def_bool PM_SLEEP
2218
1da177e4
LT
2219endmenu
2220
d5950b43
SR
2221source "net/Kconfig"
2222
ac25150f 2223source "drivers/Kconfig"
1da177e4
LT
2224
2225source "fs/Kconfig"
2226
1da177e4
LT
2227source "arch/arm/Kconfig.debug"
2228
2229source "security/Kconfig"
2230
2231source "crypto/Kconfig"
2232
2233source "lib/Kconfig"
749cf76c
CD
2234
2235source "arch/arm/kvm/Kconfig"
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