Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
b1b3f49c RK |
4 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE |
5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE | |
3d06770e | 6 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 7 | select ARCH_HAVE_CUSTOM_GPIO_H |
957e3fac | 8 | select ARCH_HAS_GCOV_PROFILE_ALL |
d7018848 | 9 | select ARCH_MIGHT_HAVE_PC_PARPORT |
4badad35 | 10 | select ARCH_SUPPORTS_ATOMIC_RMW |
017f161a | 11 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 12 | select ARCH_USE_CMPXCHG_LOCKREF |
b1b3f49c | 13 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 14 | select BUILDTIME_EXTABLE_SORT if MMU |
171b3f0d | 15 | select CLONE_BACKWARDS |
b1b3f49c | 16 | select CPU_PM if (SUSPEND || CPU_IDLE) |
dce5c9e3 | 17 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
36d0fd21 | 18 | select GENERIC_ALLOCATOR |
4477ca45 | 19 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c | 20 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
171b3f0d | 21 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
22 | select GENERIC_IRQ_PROBE |
23 | select GENERIC_IRQ_SHOW | |
b1b3f49c | 24 | select GENERIC_PCI_IOMAP |
38ff87f7 | 25 | select GENERIC_SCHED_CLOCK |
b1b3f49c RK |
26 | select GENERIC_SMP_IDLE_THREAD |
27 | select GENERIC_STRNCPY_FROM_USER | |
28 | select GENERIC_STRNLEN_USER | |
a71b092a | 29 | select HANDLE_DOMAIN_IRQ |
b1b3f49c | 30 | select HARDIRQS_SW_RESEND |
7a017721 | 31 | select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) |
0b7857db | 32 | select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 |
09f05d85 | 33 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL |
5cbad0eb | 34 | select HAVE_ARCH_KGDB |
91702175 | 35 | select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) |
0693bf68 | 36 | select HAVE_ARCH_TRACEHOOK |
b1b3f49c | 37 | select HAVE_BPF_JIT |
51aaf81f | 38 | select HAVE_CC_STACKPROTECTOR |
171b3f0d | 39 | select HAVE_CONTEXT_TRACKING |
b1b3f49c RK |
40 | select HAVE_C_RECORDMCOUNT |
41 | select HAVE_DEBUG_KMEMLEAK | |
42 | select HAVE_DMA_API_DEBUG | |
43 | select HAVE_DMA_ATTRS | |
44 | select HAVE_DMA_CONTIGUOUS if MMU | |
80be7a7f | 45 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) |
dce5c9e3 | 46 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
b1b3f49c | 47 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 48 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 49 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
1fe53268 | 50 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
51 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
52 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 53 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 54 | select HAVE_KERNEL_GZIP |
f9b493ac | 55 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 56 | select HAVE_KERNEL_LZMA |
b1b3f49c | 57 | select HAVE_KERNEL_LZO |
a7f464f3 | 58 | select HAVE_KERNEL_XZ |
b1b3f49c RK |
59 | select HAVE_KPROBES if !XIP_KERNEL |
60 | select HAVE_KRETPROBES if (HAVE_KPROBES) | |
61 | select HAVE_MEMBLOCK | |
171b3f0d | 62 | select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND |
b1b3f49c | 63 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
0dc016db | 64 | select HAVE_OPTPROBES if !THUMB2_KERNEL |
7ada189f | 65 | select HAVE_PERF_EVENTS |
49863894 WD |
66 | select HAVE_PERF_REGS |
67 | select HAVE_PERF_USER_STACK_DUMP | |
a0ad5496 | 68 | select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) |
e513f8bf | 69 | select HAVE_REGS_AND_STACK_ACCESS_API |
b1b3f49c | 70 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 71 | select HAVE_UID16 |
31c1fc81 | 72 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 73 | select IRQ_FORCED_THREADING |
171b3f0d | 74 | select MODULES_USE_ELF_REL |
84f452b1 | 75 | select NO_BOOTMEM |
171b3f0d RK |
76 | select OLD_SIGACTION |
77 | select OLD_SIGSUSPEND3 | |
b1b3f49c RK |
78 | select PERF_USE_VMALLOC |
79 | select RTC_LIB | |
80 | select SYS_SUPPORTS_APM_EMULATION | |
171b3f0d RK |
81 | # Above selects are sorted alphabetically; please add new ones |
82 | # according to that. Thanks. | |
1da177e4 LT |
83 | help |
84 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 85 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 86 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 87 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
88 | Europe. There is an ARM Linux project with a web page at |
89 | <http://www.arm.linux.org.uk/>. | |
90 | ||
74facffe | 91 | config ARM_HAS_SG_CHAIN |
308c09f1 | 92 | select ARCH_HAS_SG_CHAIN |
74facffe RK |
93 | bool |
94 | ||
4ce63fcd MS |
95 | config NEED_SG_DMA_LENGTH |
96 | bool | |
97 | ||
98 | config ARM_DMA_USE_IOMMU | |
4ce63fcd | 99 | bool |
b1b3f49c RK |
100 | select ARM_HAS_SG_CHAIN |
101 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 102 | |
60460abf SWK |
103 | if ARM_DMA_USE_IOMMU |
104 | ||
105 | config ARM_DMA_IOMMU_ALIGNMENT | |
106 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
107 | range 4 9 | |
108 | default 8 | |
109 | help | |
110 | DMA mapping framework by default aligns all buffers to the smallest | |
111 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
112 | size. This works well for buffers up to a few hundreds kilobytes, but | |
113 | for larger buffers it just a waste of address space. Drivers which has | |
114 | relatively small addressing window (like 64Mib) might run out of | |
115 | virtual space with just a few allocations. | |
116 | ||
117 | With this parameter you can specify the maximum PAGE_SIZE order for | |
118 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
119 | specified order. The order is expressed as a power of two multiplied | |
120 | by the PAGE_SIZE. | |
121 | ||
122 | endif | |
123 | ||
0b05da72 HUK |
124 | config MIGHT_HAVE_PCI |
125 | bool | |
126 | ||
75e7153a RB |
127 | config SYS_SUPPORTS_APM_EMULATION |
128 | bool | |
129 | ||
bc581770 LW |
130 | config HAVE_TCM |
131 | bool | |
132 | select GENERIC_ALLOCATOR | |
133 | ||
e119bfff RK |
134 | config HAVE_PROC_CPU |
135 | bool | |
136 | ||
ce816fa8 | 137 | config NO_IOPORT_MAP |
5ea81769 | 138 | bool |
5ea81769 | 139 | |
1da177e4 LT |
140 | config EISA |
141 | bool | |
142 | ---help--- | |
143 | The Extended Industry Standard Architecture (EISA) bus was | |
144 | developed as an open alternative to the IBM MicroChannel bus. | |
145 | ||
146 | The EISA bus provided some of the features of the IBM MicroChannel | |
147 | bus while maintaining backward compatibility with cards made for | |
148 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
149 | 1995 when it was made obsolete by the PCI bus. | |
150 | ||
151 | Say Y here if you are building a kernel for an EISA-based machine. | |
152 | ||
153 | Otherwise, say N. | |
154 | ||
155 | config SBUS | |
156 | bool | |
157 | ||
f16fb1ec RK |
158 | config STACKTRACE_SUPPORT |
159 | bool | |
160 | default y | |
161 | ||
f76e9154 NP |
162 | config HAVE_LATENCYTOP_SUPPORT |
163 | bool | |
164 | depends on !SMP | |
165 | default y | |
166 | ||
f16fb1ec RK |
167 | config LOCKDEP_SUPPORT |
168 | bool | |
169 | default y | |
170 | ||
7ad1bcb2 RK |
171 | config TRACE_IRQFLAGS_SUPPORT |
172 | bool | |
173 | default y | |
174 | ||
1da177e4 LT |
175 | config RWSEM_XCHGADD_ALGORITHM |
176 | bool | |
8a87411b | 177 | default y |
1da177e4 | 178 | |
f0d1b0b3 DH |
179 | config ARCH_HAS_ILOG2_U32 |
180 | bool | |
f0d1b0b3 DH |
181 | |
182 | config ARCH_HAS_ILOG2_U64 | |
183 | bool | |
f0d1b0b3 | 184 | |
4a1b5733 EV |
185 | config ARCH_HAS_BANDGAP |
186 | bool | |
187 | ||
b89c3b16 AM |
188 | config GENERIC_HWEIGHT |
189 | bool | |
190 | default y | |
191 | ||
1da177e4 LT |
192 | config GENERIC_CALIBRATE_DELAY |
193 | bool | |
194 | default y | |
195 | ||
a08b6b79 Z |
196 | config ARCH_MAY_HAVE_PC_FDC |
197 | bool | |
198 | ||
5ac6da66 CL |
199 | config ZONE_DMA |
200 | bool | |
5ac6da66 | 201 | |
ccd7ab7f FT |
202 | config NEED_DMA_MAP_STATE |
203 | def_bool y | |
204 | ||
c7edc9e3 DL |
205 | config ARCH_SUPPORTS_UPROBES |
206 | def_bool y | |
207 | ||
58af4a24 RH |
208 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
209 | bool | |
210 | ||
1da177e4 LT |
211 | config GENERIC_ISA_DMA |
212 | bool | |
213 | ||
1da177e4 LT |
214 | config FIQ |
215 | bool | |
216 | ||
13a5045d RH |
217 | config NEED_RET_TO_USER |
218 | bool | |
219 | ||
034d2f5a AV |
220 | config ARCH_MTD_XIP |
221 | bool | |
222 | ||
c760fc19 HC |
223 | config VECTORS_BASE |
224 | hex | |
6afd6fae | 225 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
226 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
227 | default 0x00000000 | |
228 | help | |
19accfd3 RK |
229 | The base address of exception vectors. This must be two pages |
230 | in size. | |
c760fc19 | 231 | |
dc21af99 | 232 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
233 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
234 | default y | |
b511d75d | 235 | depends on !XIP_KERNEL && MMU |
dc21af99 RK |
236 | depends on !ARCH_REALVIEW || !SPARSEMEM |
237 | help | |
111e9a5c RK |
238 | Patch phys-to-virt and virt-to-phys translation functions at |
239 | boot and module load time according to the position of the | |
240 | kernel in system memory. | |
dc21af99 | 241 | |
111e9a5c | 242 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 243 | of physical memory is at a 16MB boundary. |
dc21af99 | 244 | |
c1becedc RK |
245 | Only disable this option if you know that you do not require |
246 | this feature (eg, building a kernel for a single machine) and | |
247 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 248 | |
c334bc15 RH |
249 | config NEED_MACH_IO_H |
250 | bool | |
251 | help | |
252 | Select this when mach/io.h is required to provide special | |
253 | definitions for this platform. The need for mach/io.h should | |
254 | be avoided when possible. | |
255 | ||
0cdc8b92 | 256 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
257 | bool |
258 | help | |
0cdc8b92 NP |
259 | Select this when mach/memory.h is required to provide special |
260 | definitions for this platform. The need for mach/memory.h should | |
261 | be avoided when possible. | |
dc21af99 | 262 | |
1b9f95f8 | 263 | config PHYS_OFFSET |
974c0724 | 264 | hex "Physical address of main memory" if MMU |
c6f54a9b | 265 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 266 | default DRAM_BASE if !MMU |
c6f54a9b UKK |
267 | default 0x00000000 if ARCH_EBSA110 || \ |
268 | EP93XX_SDCE3_SYNC_PHYS_OFFSET || \ | |
269 | ARCH_FOOTBRIDGE || \ | |
270 | ARCH_INTEGRATOR || \ | |
271 | ARCH_IOP13XX || \ | |
272 | ARCH_KS8695 || \ | |
273 | (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) | |
274 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC | |
275 | default 0x20000000 if ARCH_S5PV210 | |
276 | default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET | |
277 | default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100 | |
278 | default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET | |
279 | default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET | |
280 | default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET | |
111e9a5c | 281 | help |
1b9f95f8 NP |
282 | Please provide the physical address corresponding to the |
283 | location of main memory in your system. | |
cada3c08 | 284 | |
87e040b6 SG |
285 | config GENERIC_BUG |
286 | def_bool y | |
287 | depends on BUG | |
288 | ||
1da177e4 LT |
289 | source "init/Kconfig" |
290 | ||
dc52ddc0 MH |
291 | source "kernel/Kconfig.freezer" |
292 | ||
1da177e4 LT |
293 | menu "System Type" |
294 | ||
3c427975 HC |
295 | config MMU |
296 | bool "MMU-based Paged Memory Management Support" | |
297 | default y | |
298 | help | |
299 | Select if you want MMU-based virtualised addressing space | |
300 | support by paged memory management. If unsure, say 'Y'. | |
301 | ||
ccf50e23 RK |
302 | # |
303 | # The "ARM system type" choice list is ordered alphabetically by option | |
304 | # text. Please add new entries in the option alphabetic order. | |
305 | # | |
1da177e4 LT |
306 | choice |
307 | prompt "ARM system type" | |
1420b22b AB |
308 | default ARCH_VERSATILE if !MMU |
309 | default ARCH_MULTIPLATFORM if MMU | |
1da177e4 | 310 | |
387798b3 RH |
311 | config ARCH_MULTIPLATFORM |
312 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 313 | depends on MMU |
ddb902cc | 314 | select ARCH_WANT_OPTIONAL_GPIOLIB |
42dc836d | 315 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
316 | select ARM_PATCH_PHYS_VIRT |
317 | select AUTO_ZRELADDR | |
6d0add40 | 318 | select CLKSRC_OF |
66314223 | 319 | select COMMON_CLK |
ddb902cc | 320 | select GENERIC_CLOCKEVENTS |
08d38beb | 321 | select MIGHT_HAVE_PCI |
387798b3 | 322 | select MULTI_IRQ_HANDLER |
66314223 DN |
323 | select SPARSE_IRQ |
324 | select USE_OF | |
66314223 | 325 | |
4af6fee1 DS |
326 | config ARCH_REALVIEW |
327 | bool "ARM Ltd. RealView family" | |
b1b3f49c | 328 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 329 | select ARM_AMBA |
b1b3f49c | 330 | select ARM_TIMER_SP804 |
f9a6aa43 LW |
331 | select COMMON_CLK |
332 | select COMMON_CLK_VERSATILE | |
ae30ceac | 333 | select GENERIC_CLOCKEVENTS |
b56ba8aa | 334 | select GPIO_PL061 if GPIOLIB |
b1b3f49c | 335 | select ICST |
0cdc8b92 | 336 | select NEED_MACH_MEMORY_H |
b1b3f49c | 337 | select PLAT_VERSATILE |
81cc3f86 | 338 | select PLAT_VERSATILE_SCHED_CLOCK |
4af6fee1 DS |
339 | help |
340 | This enables support for ARM Ltd RealView boards. | |
341 | ||
342 | config ARCH_VERSATILE | |
343 | bool "ARM Ltd. Versatile family" | |
b1b3f49c | 344 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 345 | select ARM_AMBA |
b1b3f49c | 346 | select ARM_TIMER_SP804 |
4af6fee1 | 347 | select ARM_VIC |
6d803ba7 | 348 | select CLKDEV_LOOKUP |
b1b3f49c | 349 | select GENERIC_CLOCKEVENTS |
aa3831cf | 350 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 351 | select ICST |
f4b8b319 | 352 | select PLAT_VERSATILE |
b1b3f49c | 353 | select PLAT_VERSATILE_CLOCK |
81cc3f86 | 354 | select PLAT_VERSATILE_SCHED_CLOCK |
2389d501 | 355 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
356 | help |
357 | This enables support for ARM Ltd Versatile board. | |
358 | ||
93e22567 RK |
359 | config ARCH_CLPS711X |
360 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" | |
a3b8d4a5 | 361 | select ARCH_REQUIRE_GPIOLIB |
ea7d1bc9 | 362 | select AUTO_ZRELADDR |
c99f72ad | 363 | select CLKSRC_MMIO |
93e22567 RK |
364 | select COMMON_CLK |
365 | select CPU_ARM720T | |
4a8355c4 | 366 | select GENERIC_CLOCKEVENTS |
6597619f | 367 | select MFD_SYSCON |
e4e3a37d | 368 | select SOC_BUS |
93e22567 RK |
369 | help |
370 | Support for Cirrus Logic 711x/721x/731x based boards. | |
371 | ||
788c9700 RK |
372 | config ARCH_GEMINI |
373 | bool "Cortina Systems Gemini" | |
788c9700 | 374 | select ARCH_REQUIRE_GPIOLIB |
f3372c01 | 375 | select CLKSRC_MMIO |
b1b3f49c | 376 | select CPU_FA526 |
f3372c01 | 377 | select GENERIC_CLOCKEVENTS |
788c9700 RK |
378 | help |
379 | Support for the Cortina Systems Gemini family SoCs | |
380 | ||
1da177e4 LT |
381 | config ARCH_EBSA110 |
382 | bool "EBSA-110" | |
b1b3f49c | 383 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 384 | select CPU_SA110 |
f7e68bbf | 385 | select ISA |
c334bc15 | 386 | select NEED_MACH_IO_H |
0cdc8b92 | 387 | select NEED_MACH_MEMORY_H |
ce816fa8 | 388 | select NO_IOPORT_MAP |
1da177e4 LT |
389 | help |
390 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 391 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
392 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
393 | parallel port. | |
394 | ||
6d85e2b0 UKK |
395 | config ARCH_EFM32 |
396 | bool "Energy Micro efm32" | |
397 | depends on !MMU | |
398 | select ARCH_REQUIRE_GPIOLIB | |
399 | select ARM_NVIC | |
51aaf81f | 400 | select AUTO_ZRELADDR |
6d85e2b0 UKK |
401 | select CLKSRC_OF |
402 | select COMMON_CLK | |
403 | select CPU_V7M | |
404 | select GENERIC_CLOCKEVENTS | |
405 | select NO_DMA | |
ce816fa8 | 406 | select NO_IOPORT_MAP |
6d85e2b0 UKK |
407 | select SPARSE_IRQ |
408 | select USE_OF | |
409 | help | |
410 | Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko | |
411 | processors. | |
412 | ||
e7736d47 LB |
413 | config ARCH_EP93XX |
414 | bool "EP93xx-based" | |
b1b3f49c RK |
415 | select ARCH_HAS_HOLES_MEMORYMODEL |
416 | select ARCH_REQUIRE_GPIOLIB | |
417 | select ARCH_USES_GETTIMEOFFSET | |
e7736d47 LB |
418 | select ARM_AMBA |
419 | select ARM_VIC | |
6d803ba7 | 420 | select CLKDEV_LOOKUP |
b1b3f49c | 421 | select CPU_ARM920T |
e7736d47 LB |
422 | help |
423 | This enables support for the Cirrus EP93xx series of CPUs. | |
424 | ||
1da177e4 LT |
425 | config ARCH_FOOTBRIDGE |
426 | bool "FootBridge" | |
c750815e | 427 | select CPU_SA110 |
1da177e4 | 428 | select FOOTBRIDGE |
4e8d7637 | 429 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 430 | select HAVE_IDE |
8ef6e620 | 431 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 432 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
433 | help |
434 | Support for systems based on the DC21285 companion chip | |
435 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 436 | |
4af6fee1 DS |
437 | config ARCH_NETX |
438 | bool "Hilscher NetX based" | |
b1b3f49c | 439 | select ARM_VIC |
234b6ced | 440 | select CLKSRC_MMIO |
c750815e | 441 | select CPU_ARM926T |
2fcfe6b8 | 442 | select GENERIC_CLOCKEVENTS |
f999b8bd | 443 | help |
4af6fee1 DS |
444 | This enables support for systems based on the Hilscher NetX Soc |
445 | ||
3b938be6 RK |
446 | config ARCH_IOP13XX |
447 | bool "IOP13xx-based" | |
448 | depends on MMU | |
b1b3f49c | 449 | select CPU_XSC3 |
0cdc8b92 | 450 | select NEED_MACH_MEMORY_H |
13a5045d | 451 | select NEED_RET_TO_USER |
b1b3f49c RK |
452 | select PCI |
453 | select PLAT_IOP | |
454 | select VMSPLIT_1G | |
37ebbcff | 455 | select SPARSE_IRQ |
3b938be6 RK |
456 | help |
457 | Support for Intel's IOP13XX (XScale) family of processors. | |
458 | ||
3f7e5815 LB |
459 | config ARCH_IOP32X |
460 | bool "IOP32x-based" | |
a4f7e763 | 461 | depends on MMU |
b1b3f49c | 462 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 463 | select CPU_XSCALE |
e9004f50 | 464 | select GPIO_IOP |
13a5045d | 465 | select NEED_RET_TO_USER |
f7e68bbf | 466 | select PCI |
b1b3f49c | 467 | select PLAT_IOP |
f999b8bd | 468 | help |
3f7e5815 LB |
469 | Support for Intel's 80219 and IOP32X (XScale) family of |
470 | processors. | |
471 | ||
472 | config ARCH_IOP33X | |
473 | bool "IOP33x-based" | |
474 | depends on MMU | |
b1b3f49c | 475 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 476 | select CPU_XSCALE |
e9004f50 | 477 | select GPIO_IOP |
13a5045d | 478 | select NEED_RET_TO_USER |
3f7e5815 | 479 | select PCI |
b1b3f49c | 480 | select PLAT_IOP |
3f7e5815 LB |
481 | help |
482 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 483 | |
3b938be6 RK |
484 | config ARCH_IXP4XX |
485 | bool "IXP4xx-based" | |
a4f7e763 | 486 | depends on MMU |
58af4a24 | 487 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
b1b3f49c | 488 | select ARCH_REQUIRE_GPIOLIB |
51aaf81f | 489 | select ARCH_SUPPORTS_BIG_ENDIAN |
234b6ced | 490 | select CLKSRC_MMIO |
c750815e | 491 | select CPU_XSCALE |
b1b3f49c | 492 | select DMABOUNCE if PCI |
3b938be6 | 493 | select GENERIC_CLOCKEVENTS |
0b05da72 | 494 | select MIGHT_HAVE_PCI |
c334bc15 | 495 | select NEED_MACH_IO_H |
9296d94d | 496 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 497 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 498 | help |
3b938be6 | 499 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 500 | |
edabd38e SB |
501 | config ARCH_DOVE |
502 | bool "Marvell Dove" | |
edabd38e | 503 | select ARCH_REQUIRE_GPIOLIB |
756b2531 | 504 | select CPU_PJ4 |
edabd38e | 505 | select GENERIC_CLOCKEVENTS |
0f81bd43 | 506 | select MIGHT_HAVE_PCI |
171b3f0d | 507 | select MVEBU_MBUS |
9139acd1 SH |
508 | select PINCTRL |
509 | select PINCTRL_DOVE | |
abcda1dc | 510 | select PLAT_ORION_LEGACY |
edabd38e SB |
511 | help |
512 | Support for the Marvell Dove SoC 88AP510 | |
513 | ||
794d15b2 SS |
514 | config ARCH_MV78XX0 |
515 | bool "Marvell MV78xx0" | |
a8865655 | 516 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 517 | select CPU_FEROCEON |
794d15b2 | 518 | select GENERIC_CLOCKEVENTS |
171b3f0d | 519 | select MVEBU_MBUS |
b1b3f49c | 520 | select PCI |
abcda1dc | 521 | select PLAT_ORION_LEGACY |
794d15b2 SS |
522 | help |
523 | Support for the following Marvell MV78xx0 series SoCs: | |
524 | MV781x0, MV782x0. | |
525 | ||
9dd0b194 | 526 | config ARCH_ORION5X |
585cf175 TP |
527 | bool "Marvell Orion" |
528 | depends on MMU | |
a8865655 | 529 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 530 | select CPU_FEROCEON |
51cbff1d | 531 | select GENERIC_CLOCKEVENTS |
171b3f0d | 532 | select MVEBU_MBUS |
b1b3f49c | 533 | select PCI |
abcda1dc | 534 | select PLAT_ORION_LEGACY |
585cf175 | 535 | help |
9dd0b194 | 536 | Support for the following Marvell Orion 5x series SoCs: |
d2b2a6bb | 537 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
d323ade1 | 538 | Orion-2 (5281), Orion-1-90 (6183). |
585cf175 | 539 | |
788c9700 | 540 | config ARCH_MMP |
2f7e8fae | 541 | bool "Marvell PXA168/910/MMP2" |
788c9700 | 542 | depends on MMU |
788c9700 | 543 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 544 | select CLKDEV_LOOKUP |
b1b3f49c | 545 | select GENERIC_ALLOCATOR |
788c9700 | 546 | select GENERIC_CLOCKEVENTS |
157d2644 | 547 | select GPIO_PXA |
c24b3114 | 548 | select IRQ_DOMAIN |
0f374561 | 549 | select MULTI_IRQ_HANDLER |
7c8f86a4 | 550 | select PINCTRL |
788c9700 | 551 | select PLAT_PXA |
0bd86961 | 552 | select SPARSE_IRQ |
788c9700 | 553 | help |
2f7e8fae | 554 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. |
788c9700 RK |
555 | |
556 | config ARCH_KS8695 | |
557 | bool "Micrel/Kendin KS8695" | |
98830bc9 | 558 | select ARCH_REQUIRE_GPIOLIB |
c7e783d6 | 559 | select CLKSRC_MMIO |
b1b3f49c | 560 | select CPU_ARM922T |
c7e783d6 | 561 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 562 | select NEED_MACH_MEMORY_H |
788c9700 RK |
563 | help |
564 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
565 | System-on-Chip devices. | |
566 | ||
788c9700 RK |
567 | config ARCH_W90X900 |
568 | bool "Nuvoton W90X900 CPU" | |
c52d3d68 | 569 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 570 | select CLKDEV_LOOKUP |
6fa5d5f7 | 571 | select CLKSRC_MMIO |
b1b3f49c | 572 | select CPU_ARM926T |
58b5369e | 573 | select GENERIC_CLOCKEVENTS |
788c9700 | 574 | help |
a8bc4ead | 575 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
576 | At present, the w90x900 has been renamed nuc900, regarding | |
577 | the ARM series product line, you can login the following | |
578 | link address to know more. | |
579 | ||
580 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
581 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 582 | |
93e22567 RK |
583 | config ARCH_LPC32XX |
584 | bool "NXP LPC32XX" | |
585 | select ARCH_REQUIRE_GPIOLIB | |
586 | select ARM_AMBA | |
587 | select CLKDEV_LOOKUP | |
588 | select CLKSRC_MMIO | |
589 | select CPU_ARM926T | |
590 | select GENERIC_CLOCKEVENTS | |
591 | select HAVE_IDE | |
93e22567 RK |
592 | select USE_OF |
593 | help | |
594 | Support for the NXP LPC32XX family of processors | |
595 | ||
1da177e4 | 596 | config ARCH_PXA |
2c8086a5 | 597 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 598 | depends on MMU |
b1b3f49c RK |
599 | select ARCH_MTD_XIP |
600 | select ARCH_REQUIRE_GPIOLIB | |
601 | select ARM_CPU_SUSPEND if PM | |
602 | select AUTO_ZRELADDR | |
6d803ba7 | 603 | select CLKDEV_LOOKUP |
234b6ced | 604 | select CLKSRC_MMIO |
6f6caeaa | 605 | select CLKSRC_OF |
981d0f39 | 606 | select GENERIC_CLOCKEVENTS |
157d2644 | 607 | select GPIO_PXA |
d0ee9f40 | 608 | select HAVE_IDE |
b1b3f49c | 609 | select MULTI_IRQ_HANDLER |
b1b3f49c RK |
610 | select PLAT_PXA |
611 | select SPARSE_IRQ | |
f999b8bd | 612 | help |
2c8086a5 | 613 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 | 614 | |
8fc1b0f8 KG |
615 | config ARCH_MSM |
616 | bool "Qualcomm MSM (non-multiplatform)" | |
923a081c | 617 | select ARCH_REQUIRE_GPIOLIB |
8cc7f533 | 618 | select COMMON_CLK |
b1b3f49c | 619 | select GENERIC_CLOCKEVENTS |
49cbe786 | 620 | help |
4b53eb4f DW |
621 | Support for Qualcomm MSM/QSD based systems. This runs on the |
622 | apps processor of the MSM/QSD and depends on a shared memory | |
623 | interface to the modem processor which runs the baseband | |
624 | stack and controls some vital subsystems | |
625 | (clock and power control, etc). | |
49cbe786 | 626 | |
bf98c1ea | 627 | config ARCH_SHMOBILE_LEGACY |
0d9fd616 | 628 | bool "Renesas ARM SoCs (non-multiplatform)" |
bf98c1ea | 629 | select ARCH_SHMOBILE |
91942d17 | 630 | select ARM_PATCH_PHYS_VIRT if MMU |
5e93c6b4 | 631 | select CLKDEV_LOOKUP |
0ed82bc9 | 632 | select CPU_V7 |
b1b3f49c | 633 | select GENERIC_CLOCKEVENTS |
4c3ffffd | 634 | select HAVE_ARM_SCU if SMP |
a894fcc2 | 635 | select HAVE_ARM_TWD if SMP |
aa3831cf | 636 | select HAVE_MACH_CLKDEV |
3b55658a | 637 | select HAVE_SMP |
ce5ea9f3 | 638 | select MIGHT_HAVE_CACHE_L2X0 |
60f1435c | 639 | select MULTI_IRQ_HANDLER |
ce816fa8 | 640 | select NO_IOPORT_MAP |
2cd3c927 | 641 | select PINCTRL |
b1b3f49c | 642 | select PM_GENERIC_DOMAINS if PM |
0cdc23df | 643 | select SH_CLK_CPG |
b1b3f49c | 644 | select SPARSE_IRQ |
c793c1b0 | 645 | help |
0d9fd616 LP |
646 | Support for Renesas ARM SoC platforms using a non-multiplatform |
647 | kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car | |
648 | and RZ families. | |
c793c1b0 | 649 | |
1da177e4 LT |
650 | config ARCH_RPC |
651 | bool "RiscPC" | |
652 | select ARCH_ACORN | |
a08b6b79 | 653 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 654 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 655 | select ARCH_USES_GETTIMEOFFSET |
fa04e209 | 656 | select CPU_SA110 |
b1b3f49c | 657 | select FIQ |
d0ee9f40 | 658 | select HAVE_IDE |
b1b3f49c RK |
659 | select HAVE_PATA_PLATFORM |
660 | select ISA_DMA_API | |
c334bc15 | 661 | select NEED_MACH_IO_H |
0cdc8b92 | 662 | select NEED_MACH_MEMORY_H |
ce816fa8 | 663 | select NO_IOPORT_MAP |
b4811bac | 664 | select VIRT_TO_BUS |
1da177e4 LT |
665 | help |
666 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
667 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
668 | ||
669 | config ARCH_SA1100 | |
670 | bool "SA1100-based" | |
b1b3f49c RK |
671 | select ARCH_MTD_XIP |
672 | select ARCH_REQUIRE_GPIOLIB | |
673 | select ARCH_SPARSEMEM_ENABLE | |
674 | select CLKDEV_LOOKUP | |
675 | select CLKSRC_MMIO | |
1937f5b9 | 676 | select CPU_FREQ |
b1b3f49c | 677 | select CPU_SA1100 |
3e238be2 | 678 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 679 | select HAVE_IDE |
1eca42b4 | 680 | select IRQ_DOMAIN |
b1b3f49c | 681 | select ISA |
affcab32 | 682 | select MULTI_IRQ_HANDLER |
0cdc8b92 | 683 | select NEED_MACH_MEMORY_H |
375dec92 | 684 | select SPARSE_IRQ |
f999b8bd MM |
685 | help |
686 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 687 | |
b130d5c2 KK |
688 | config ARCH_S3C24XX |
689 | bool "Samsung S3C24XX SoCs" | |
53650430 | 690 | select ARCH_REQUIRE_GPIOLIB |
335cce74 | 691 | select ATAGS |
b1b3f49c | 692 | select CLKDEV_LOOKUP |
4280506a | 693 | select CLKSRC_SAMSUNG_PWM |
7f78b6eb | 694 | select GENERIC_CLOCKEVENTS |
880cf071 | 695 | select GPIO_SAMSUNG |
20676c15 | 696 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 697 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 698 | select HAVE_S3C_RTC if RTC_CLASS |
17453dd2 | 699 | select MULTI_IRQ_HANDLER |
c334bc15 | 700 | select NEED_MACH_IO_H |
cd8dc7ae | 701 | select SAMSUNG_ATAGS |
1da177e4 | 702 | help |
b130d5c2 KK |
703 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
704 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
705 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
706 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 707 | |
a08ab637 BD |
708 | config ARCH_S3C64XX |
709 | bool "Samsung S3C64XX" | |
b1b3f49c | 710 | select ARCH_REQUIRE_GPIOLIB |
1db0287a | 711 | select ARM_AMBA |
89f0ce72 | 712 | select ARM_VIC |
335cce74 | 713 | select ATAGS |
b1b3f49c | 714 | select CLKDEV_LOOKUP |
4280506a | 715 | select CLKSRC_SAMSUNG_PWM |
ccecba3c | 716 | select COMMON_CLK_SAMSUNG |
70bacadb | 717 | select CPU_V6K |
04a49b71 | 718 | select GENERIC_CLOCKEVENTS |
880cf071 | 719 | select GPIO_SAMSUNG |
b1b3f49c RK |
720 | select HAVE_S3C2410_I2C if I2C |
721 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
6700397a | 722 | select HAVE_TCM |
ce816fa8 | 723 | select NO_IOPORT_MAP |
b1b3f49c | 724 | select PLAT_SAMSUNG |
4ab75a3f | 725 | select PM_GENERIC_DOMAINS if PM |
b1b3f49c RK |
726 | select S3C_DEV_NAND |
727 | select S3C_GPIO_TRACK | |
cd8dc7ae | 728 | select SAMSUNG_ATAGS |
6e2d9e93 | 729 | select SAMSUNG_WAKEMASK |
88f59738 | 730 | select SAMSUNG_WDT_RESET |
a08ab637 BD |
731 | help |
732 | Samsung S3C64XX series based systems | |
733 | ||
7c6337e2 KH |
734 | config ARCH_DAVINCI |
735 | bool "TI DaVinci" | |
b1b3f49c | 736 | select ARCH_HAS_HOLES_MEMORYMODEL |
dce1115b | 737 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 738 | select CLKDEV_LOOKUP |
20e9969b | 739 | select GENERIC_ALLOCATOR |
b1b3f49c | 740 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 741 | select GENERIC_IRQ_CHIP |
b1b3f49c | 742 | select HAVE_IDE |
3ad7a42d | 743 | select TI_PRIV_EDMA |
689e331f | 744 | select USE_OF |
b1b3f49c | 745 | select ZONE_DMA |
7c6337e2 KH |
746 | help |
747 | Support for TI's DaVinci platform. | |
748 | ||
a0694861 TL |
749 | config ARCH_OMAP1 |
750 | bool "TI OMAP1" | |
00a36698 | 751 | depends on MMU |
9af915da | 752 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 753 | select ARCH_OMAP |
21f47fbc | 754 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 755 | select CLKDEV_LOOKUP |
d6e15d78 | 756 | select CLKSRC_MMIO |
b1b3f49c | 757 | select GENERIC_CLOCKEVENTS |
a0694861 | 758 | select GENERIC_IRQ_CHIP |
a0694861 TL |
759 | select HAVE_IDE |
760 | select IRQ_DOMAIN | |
761 | select NEED_MACH_IO_H if PCCARD | |
762 | select NEED_MACH_MEMORY_H | |
21f47fbc | 763 | help |
a0694861 | 764 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 765 | |
1da177e4 LT |
766 | endchoice |
767 | ||
387798b3 RH |
768 | menu "Multiple platform selection" |
769 | depends on ARCH_MULTIPLATFORM | |
770 | ||
771 | comment "CPU Core family selection" | |
772 | ||
f8afae40 AB |
773 | config ARCH_MULTI_V4 |
774 | bool "ARMv4 based platforms (FA526)" | |
775 | depends on !ARCH_MULTI_V6_V7 | |
776 | select ARCH_MULTI_V4_V5 | |
777 | select CPU_FA526 | |
778 | ||
387798b3 RH |
779 | config ARCH_MULTI_V4T |
780 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 781 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 782 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
783 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
784 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
785 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
786 | |
787 | config ARCH_MULTI_V5 | |
788 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 789 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 790 | select ARCH_MULTI_V4_V5 |
12567bbd | 791 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
792 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
793 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
794 | |
795 | config ARCH_MULTI_V4_V5 | |
796 | bool | |
797 | ||
798 | config ARCH_MULTI_V6 | |
8dda05cc | 799 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 800 | select ARCH_MULTI_V6_V7 |
42f4754a | 801 | select CPU_V6K |
387798b3 RH |
802 | |
803 | config ARCH_MULTI_V7 | |
8dda05cc | 804 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
805 | default y |
806 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 807 | select CPU_V7 |
90bc8ac7 | 808 | select HAVE_SMP |
387798b3 RH |
809 | |
810 | config ARCH_MULTI_V6_V7 | |
811 | bool | |
9352b05b | 812 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
813 | |
814 | config ARCH_MULTI_CPU_AUTO | |
815 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
816 | select ARCH_MULTI_V5 | |
817 | ||
818 | endmenu | |
819 | ||
05e2a3de RH |
820 | config ARCH_VIRT |
821 | bool "Dummy Virtual Machine" if ARCH_MULTI_V7 | |
4b8b5f25 | 822 | select ARM_AMBA |
05e2a3de | 823 | select ARM_GIC |
05e2a3de | 824 | select ARM_PSCI |
4b8b5f25 | 825 | select HAVE_ARM_ARCH_TIMER |
05e2a3de | 826 | |
ccf50e23 RK |
827 | # |
828 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
829 | # Kconfigs may be included either alphabetically (according to the | |
830 | # plat- suffix) or along side the corresponding mach-* source. | |
831 | # | |
3e93a22b GC |
832 | source "arch/arm/mach-mvebu/Kconfig" |
833 | ||
d9bfc86d OR |
834 | source "arch/arm/mach-asm9260/Kconfig" |
835 | ||
95b8f20f RK |
836 | source "arch/arm/mach-at91/Kconfig" |
837 | ||
1d22924e AB |
838 | source "arch/arm/mach-axxia/Kconfig" |
839 | ||
8ac49e04 CD |
840 | source "arch/arm/mach-bcm/Kconfig" |
841 | ||
1c37fa10 SH |
842 | source "arch/arm/mach-berlin/Kconfig" |
843 | ||
1da177e4 LT |
844 | source "arch/arm/mach-clps711x/Kconfig" |
845 | ||
d94f944e AV |
846 | source "arch/arm/mach-cns3xxx/Kconfig" |
847 | ||
95b8f20f RK |
848 | source "arch/arm/mach-davinci/Kconfig" |
849 | ||
df8d742e BS |
850 | source "arch/arm/mach-digicolor/Kconfig" |
851 | ||
95b8f20f RK |
852 | source "arch/arm/mach-dove/Kconfig" |
853 | ||
e7736d47 LB |
854 | source "arch/arm/mach-ep93xx/Kconfig" |
855 | ||
1da177e4 LT |
856 | source "arch/arm/mach-footbridge/Kconfig" |
857 | ||
59d3a193 PZ |
858 | source "arch/arm/mach-gemini/Kconfig" |
859 | ||
387798b3 RH |
860 | source "arch/arm/mach-highbank/Kconfig" |
861 | ||
389ee0c2 HZ |
862 | source "arch/arm/mach-hisi/Kconfig" |
863 | ||
1da177e4 LT |
864 | source "arch/arm/mach-integrator/Kconfig" |
865 | ||
3f7e5815 LB |
866 | source "arch/arm/mach-iop32x/Kconfig" |
867 | ||
868 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 869 | |
285f5fa7 DW |
870 | source "arch/arm/mach-iop13xx/Kconfig" |
871 | ||
1da177e4 LT |
872 | source "arch/arm/mach-ixp4xx/Kconfig" |
873 | ||
828989ad SS |
874 | source "arch/arm/mach-keystone/Kconfig" |
875 | ||
95b8f20f RK |
876 | source "arch/arm/mach-ks8695/Kconfig" |
877 | ||
3b8f5030 CC |
878 | source "arch/arm/mach-meson/Kconfig" |
879 | ||
95b8f20f RK |
880 | source "arch/arm/mach-msm/Kconfig" |
881 | ||
17723fd3 JJ |
882 | source "arch/arm/mach-moxart/Kconfig" |
883 | ||
794d15b2 SS |
884 | source "arch/arm/mach-mv78xx0/Kconfig" |
885 | ||
3995eb82 | 886 | source "arch/arm/mach-imx/Kconfig" |
1da177e4 | 887 | |
f682a218 MB |
888 | source "arch/arm/mach-mediatek/Kconfig" |
889 | ||
1d3f33d5 SG |
890 | source "arch/arm/mach-mxs/Kconfig" |
891 | ||
95b8f20f | 892 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 893 | |
95b8f20f | 894 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 895 | |
9851ca57 DT |
896 | source "arch/arm/mach-nspire/Kconfig" |
897 | ||
d48af15e TL |
898 | source "arch/arm/plat-omap/Kconfig" |
899 | ||
900 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 901 | |
1dbae815 TL |
902 | source "arch/arm/mach-omap2/Kconfig" |
903 | ||
9dd0b194 | 904 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 905 | |
387798b3 RH |
906 | source "arch/arm/mach-picoxcell/Kconfig" |
907 | ||
95b8f20f RK |
908 | source "arch/arm/mach-pxa/Kconfig" |
909 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 910 | |
95b8f20f RK |
911 | source "arch/arm/mach-mmp/Kconfig" |
912 | ||
8fc1b0f8 KG |
913 | source "arch/arm/mach-qcom/Kconfig" |
914 | ||
95b8f20f RK |
915 | source "arch/arm/mach-realview/Kconfig" |
916 | ||
d63dc051 HS |
917 | source "arch/arm/mach-rockchip/Kconfig" |
918 | ||
95b8f20f | 919 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 920 | |
387798b3 RH |
921 | source "arch/arm/mach-socfpga/Kconfig" |
922 | ||
a7ed099f | 923 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 924 | |
65ebcc11 SK |
925 | source "arch/arm/mach-sti/Kconfig" |
926 | ||
85fd6d63 | 927 | source "arch/arm/mach-s3c24xx/Kconfig" |
1da177e4 | 928 | |
431107ea | 929 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 | 930 | |
170f4e42 KK |
931 | source "arch/arm/mach-s5pv210/Kconfig" |
932 | ||
83014579 | 933 | source "arch/arm/mach-exynos/Kconfig" |
e509b289 | 934 | source "arch/arm/plat-samsung/Kconfig" |
cc0e72b8 | 935 | |
882d01f9 | 936 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 937 | |
3b52634f MR |
938 | source "arch/arm/mach-sunxi/Kconfig" |
939 | ||
156a0997 BS |
940 | source "arch/arm/mach-prima2/Kconfig" |
941 | ||
c5f80065 EG |
942 | source "arch/arm/mach-tegra/Kconfig" |
943 | ||
95b8f20f | 944 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 945 | |
95b8f20f | 946 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
947 | |
948 | source "arch/arm/mach-versatile/Kconfig" | |
949 | ||
ceade897 | 950 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 951 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 952 | |
6f35f9a9 TP |
953 | source "arch/arm/mach-vt8500/Kconfig" |
954 | ||
7ec80ddf | 955 | source "arch/arm/mach-w90x900/Kconfig" |
956 | ||
9a45eb69 JC |
957 | source "arch/arm/mach-zynq/Kconfig" |
958 | ||
1da177e4 LT |
959 | # Definitions to make life easier |
960 | config ARCH_ACORN | |
961 | bool | |
962 | ||
7ae1f7ec LB |
963 | config PLAT_IOP |
964 | bool | |
469d3044 | 965 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 966 | |
69b02f6a LB |
967 | config PLAT_ORION |
968 | bool | |
bfe45e0b | 969 | select CLKSRC_MMIO |
b1b3f49c | 970 | select COMMON_CLK |
dc7ad3b3 | 971 | select GENERIC_IRQ_CHIP |
278b45b0 | 972 | select IRQ_DOMAIN |
69b02f6a | 973 | |
abcda1dc TP |
974 | config PLAT_ORION_LEGACY |
975 | bool | |
976 | select PLAT_ORION | |
977 | ||
bd5ce433 EM |
978 | config PLAT_PXA |
979 | bool | |
980 | ||
f4b8b319 RK |
981 | config PLAT_VERSATILE |
982 | bool | |
983 | ||
e3887714 RK |
984 | config ARM_TIMER_SP804 |
985 | bool | |
bfe45e0b | 986 | select CLKSRC_MMIO |
7a0eca71 | 987 | select CLKSRC_OF if OF |
e3887714 | 988 | |
d9a1beaa AC |
989 | source "arch/arm/firmware/Kconfig" |
990 | ||
1da177e4 LT |
991 | source arch/arm/mm/Kconfig |
992 | ||
afe4b25e | 993 | config IWMMXT |
d93003e8 SH |
994 | bool "Enable iWMMXt support" |
995 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
996 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
997 | help |
998 | Enable support for iWMMXt context switching at run time if | |
999 | running on a CPU that supports it. | |
1000 | ||
52108641 | 1001 | config MULTI_IRQ_HANDLER |
1002 | bool | |
1003 | help | |
1004 | Allow each machine to specify it's own IRQ handler at run time. | |
1005 | ||
3b93e7b0 HC |
1006 | if !MMU |
1007 | source "arch/arm/Kconfig-nommu" | |
1008 | endif | |
1009 | ||
3e0a07f8 GC |
1010 | config PJ4B_ERRATA_4742 |
1011 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
1012 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
1013 | default y | |
1014 | help | |
1015 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
1016 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
1017 | the retiring WFI/WFE instructions and the newly issued subsequent | |
1018 | instructions. This sensitivity can result in a CPU hang scenario. | |
1019 | Workaround: | |
1020 | The software must insert either a Data Synchronization Barrier (DSB) | |
1021 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
1022 | instruction | |
1023 | ||
f0c4b8d6 WD |
1024 | config ARM_ERRATA_326103 |
1025 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
1026 | depends on CPU_V6 | |
1027 | help | |
1028 | Executing a SWP instruction to read-only memory does not set bit 11 | |
1029 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
1030 | treat the access as a read, preventing a COW from occurring and | |
1031 | causing the faulting task to livelock. | |
1032 | ||
9cba3ccc CM |
1033 | config ARM_ERRATA_411920 |
1034 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 1035 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
1036 | help |
1037 | Invalidation of the Instruction Cache operation can | |
1038 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1039 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1040 | recommended workaround. | |
1041 | ||
7ce236fc CM |
1042 | config ARM_ERRATA_430973 |
1043 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1044 | depends on CPU_V7 | |
1045 | help | |
1046 | This option enables the workaround for the 430973 Cortex-A8 | |
1047 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1048 | interworking branch is replaced with another code sequence at the | |
1049 | same virtual address, whether due to self-modifying code or virtual | |
1050 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1051 | stale interworking branch prediction. This results in Cortex-A8 | |
1052 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1053 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1054 | and also flushes the branch target cache at every context switch. | |
1055 | Note that setting specific bits in the ACTLR register may not be | |
1056 | available in non-secure mode. | |
1057 | ||
855c551f CM |
1058 | config ARM_ERRATA_458693 |
1059 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1060 | depends on CPU_V7 | |
62e4d357 | 1061 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
1062 | help |
1063 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1064 | erratum. For very specific sequences of memory operations, it is | |
1065 | possible for a hazard condition intended for a cache line to instead | |
1066 | be incorrectly associated with a different cache line. This false | |
1067 | hazard might then cause a processor deadlock. The workaround enables | |
1068 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1069 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1070 | register may not be available in non-secure mode. | |
1071 | ||
0516e464 CM |
1072 | config ARM_ERRATA_460075 |
1073 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1074 | depends on CPU_V7 | |
62e4d357 | 1075 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
1076 | help |
1077 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1078 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1079 | situation in which recent store transactions to the L2 cache are lost | |
1080 | and overwritten with stale memory contents from external memory. The | |
1081 | workaround disables the write-allocate mode for the L2 cache via the | |
1082 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1083 | may not be available in non-secure mode. | |
1084 | ||
9f05027c WD |
1085 | config ARM_ERRATA_742230 |
1086 | bool "ARM errata: DMB operation may be faulty" | |
1087 | depends on CPU_V7 && SMP | |
62e4d357 | 1088 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1089 | help |
1090 | This option enables the workaround for the 742230 Cortex-A9 | |
1091 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1092 | between two write operations may not ensure the correct visibility | |
1093 | ordering of the two writes. This workaround sets a specific bit in | |
1094 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1095 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1096 | the two writes. | |
1097 | ||
a672e99b WD |
1098 | config ARM_ERRATA_742231 |
1099 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1100 | depends on CPU_V7 && SMP | |
62e4d357 | 1101 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1102 | help |
1103 | This option enables the workaround for the 742231 Cortex-A9 | |
1104 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1105 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1106 | accessing some data located in the same cache line, may get corrupted | |
1107 | data due to bad handling of the address hazard when the line gets | |
1108 | replaced from one of the CPUs at the same time as another CPU is | |
1109 | accessing it. This workaround sets specific bits in the diagnostic | |
1110 | register of the Cortex-A9 which reduces the linefill issuing | |
1111 | capabilities of the processor. | |
1112 | ||
69155794 JM |
1113 | config ARM_ERRATA_643719 |
1114 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1115 | depends on CPU_V7 && SMP | |
1116 | help | |
1117 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1118 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1119 | register returns zero when it should return one. The workaround | |
1120 | corrects this value, ensuring cache maintenance operations which use | |
1121 | it behave as intended and avoiding data corruption. | |
1122 | ||
cdf357f1 WD |
1123 | config ARM_ERRATA_720789 |
1124 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1125 | depends on CPU_V7 |
cdf357f1 WD |
1126 | help |
1127 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1128 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1129 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1130 | As a consequence of this erratum, some TLB entries which should be | |
1131 | invalidated are not, resulting in an incoherency in the system page | |
1132 | tables. The workaround changes the TLB flushing routines to invalidate | |
1133 | entries regardless of the ASID. | |
475d92fc WD |
1134 | |
1135 | config ARM_ERRATA_743622 | |
1136 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1137 | depends on CPU_V7 | |
62e4d357 | 1138 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1139 | help |
1140 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1141 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1142 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1143 | corruption. This workaround sets a specific bit in the diagnostic | |
1144 | register of the Cortex-A9 which disables the Store Buffer | |
1145 | optimisation, preventing the defect from occurring. This has no | |
1146 | visible impact on the overall performance or power consumption of the | |
1147 | processor. | |
1148 | ||
9a27c27c WD |
1149 | config ARM_ERRATA_751472 |
1150 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1151 | depends on CPU_V7 |
62e4d357 | 1152 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1153 | help |
1154 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1155 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1156 | completion of a following broadcasted operation if the second | |
1157 | operation is received by a CPU before the ICIALLUIS has completed, | |
1158 | potentially leading to corrupted entries in the cache or TLB. | |
1159 | ||
fcbdc5fe WD |
1160 | config ARM_ERRATA_754322 |
1161 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1162 | depends on CPU_V7 | |
1163 | help | |
1164 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1165 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1166 | which starts prior to an ASID switch but completes afterwards. This | |
1167 | can populate the micro-TLB with a stale entry which may be hit with | |
1168 | the new ASID. This workaround places two dsb instructions in the mm | |
1169 | switching code so that no page table walks can cross the ASID switch. | |
1170 | ||
5dab26af WD |
1171 | config ARM_ERRATA_754327 |
1172 | bool "ARM errata: no automatic Store Buffer drain" | |
1173 | depends on CPU_V7 && SMP | |
1174 | help | |
1175 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1176 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1177 | mechanism and therefore a livelock may occur if an external agent | |
1178 | continuously polls a memory location waiting to observe an update. | |
1179 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1180 | written polling loops from denying visibility of updates to memory. | |
1181 | ||
145e10e1 CM |
1182 | config ARM_ERRATA_364296 |
1183 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 1184 | depends on CPU_V6 |
145e10e1 CM |
1185 | help |
1186 | This options enables the workaround for the 364296 ARM1136 | |
1187 | r0p2 erratum (possible cache data corruption with | |
1188 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1189 | the auxiliary control register and the FI bit in the control | |
1190 | register, thus disabling hit-under-miss without putting the | |
1191 | processor into full low interrupt latency mode. ARM11MPCore | |
1192 | is not affected. | |
1193 | ||
f630c1bd WD |
1194 | config ARM_ERRATA_764369 |
1195 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1196 | depends on CPU_V7 && SMP | |
1197 | help | |
1198 | This option enables the workaround for erratum 764369 | |
1199 | affecting Cortex-A9 MPCore with two or more processors (all | |
1200 | current revisions). Under certain timing circumstances, a data | |
1201 | cache line maintenance operation by MVA targeting an Inner | |
1202 | Shareable memory region may fail to proceed up to either the | |
1203 | Point of Coherency or to the Point of Unification of the | |
1204 | system. This workaround adds a DSB instruction before the | |
1205 | relevant cache maintenance functions and sets a specific bit | |
1206 | in the diagnostic control register of the SCU. | |
1207 | ||
7253b85c SH |
1208 | config ARM_ERRATA_775420 |
1209 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1210 | depends on CPU_V7 | |
1211 | help | |
1212 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1213 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1214 | operation aborts with MMU exception, it might cause the processor | |
1215 | to deadlock. This workaround puts DSB before executing ISB if | |
1216 | an abort may occur on cache maintenance. | |
1217 | ||
93dc6887 CM |
1218 | config ARM_ERRATA_798181 |
1219 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1220 | depends on CPU_V7 && SMP | |
1221 | help | |
1222 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1223 | adequately shooting down all use of the old entries. This | |
1224 | option enables the Linux kernel workaround for this erratum | |
1225 | which sends an IPI to the CPUs that are running the same ASID | |
1226 | as the one being invalidated. | |
1227 | ||
84b6504f WD |
1228 | config ARM_ERRATA_773022 |
1229 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1230 | depends on CPU_V7 | |
1231 | help | |
1232 | This option enables the workaround for the 773022 Cortex-A15 | |
1233 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1234 | loop buffer may deliver incorrect instructions. This | |
1235 | workaround disables the loop buffer to avoid the erratum. | |
1236 | ||
1da177e4 LT |
1237 | endmenu |
1238 | ||
1239 | source "arch/arm/common/Kconfig" | |
1240 | ||
1da177e4 LT |
1241 | menu "Bus support" |
1242 | ||
1da177e4 LT |
1243 | config ISA |
1244 | bool | |
1da177e4 LT |
1245 | help |
1246 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1247 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1248 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1249 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1250 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1251 | ||
065909b9 | 1252 | # Select ISA DMA controller support |
1da177e4 LT |
1253 | config ISA_DMA |
1254 | bool | |
065909b9 | 1255 | select ISA_DMA_API |
1da177e4 | 1256 | |
065909b9 | 1257 | # Select ISA DMA interface |
5cae841b AV |
1258 | config ISA_DMA_API |
1259 | bool | |
5cae841b | 1260 | |
1da177e4 | 1261 | config PCI |
0b05da72 | 1262 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1263 | help |
1264 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1265 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1266 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1267 | VESA. If you have PCI, say Y, otherwise N. | |
1268 | ||
52882173 AV |
1269 | config PCI_DOMAINS |
1270 | bool | |
1271 | depends on PCI | |
1272 | ||
8c7d1474 LP |
1273 | config PCI_DOMAINS_GENERIC |
1274 | def_bool PCI_DOMAINS | |
1275 | ||
b080ac8a MRJ |
1276 | config PCI_NANOENGINE |
1277 | bool "BSE nanoEngine PCI support" | |
1278 | depends on SA1100_NANOENGINE | |
1279 | help | |
1280 | Enable PCI on the BSE nanoEngine board. | |
1281 | ||
36e23590 MW |
1282 | config PCI_SYSCALL |
1283 | def_bool PCI | |
1284 | ||
a0113a99 MR |
1285 | config PCI_HOST_ITE8152 |
1286 | bool | |
1287 | depends on PCI && MACH_ARMCORE | |
1288 | default y | |
1289 | select DMABOUNCE | |
1290 | ||
1da177e4 | 1291 | source "drivers/pci/Kconfig" |
3f06d157 | 1292 | source "drivers/pci/pcie/Kconfig" |
1da177e4 LT |
1293 | |
1294 | source "drivers/pcmcia/Kconfig" | |
1295 | ||
1296 | endmenu | |
1297 | ||
1298 | menu "Kernel Features" | |
1299 | ||
3b55658a DM |
1300 | config HAVE_SMP |
1301 | bool | |
1302 | help | |
1303 | This option should be selected by machines which have an SMP- | |
1304 | capable CPU. | |
1305 | ||
1306 | The only effect of this option is to make the SMP-related | |
1307 | options available to the user for configuration. | |
1308 | ||
1da177e4 | 1309 | config SMP |
bb2d8130 | 1310 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1311 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1312 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1313 | depends on HAVE_SMP |
801bb21c | 1314 | depends on MMU || ARM_MPU |
1da177e4 LT |
1315 | help |
1316 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1317 | a system with only one CPU, say N. If you have a system with more |
1318 | than one CPU, say Y. | |
1da177e4 | 1319 | |
4a474157 | 1320 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1321 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1322 | you say Y here, the kernel will run on many, but not all, |
1323 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1324 | will run faster if you say N here. | |
1da177e4 | 1325 | |
395cf969 | 1326 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1327 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1328 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1329 | |
1330 | If you don't know what to do here, say N. | |
1331 | ||
f00ec48f RK |
1332 | config SMP_ON_UP |
1333 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
801bb21c | 1334 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1335 | default y |
1336 | help | |
1337 | SMP kernels contain instructions which fail on non-SMP processors. | |
1338 | Enabling this option allows the kernel to modify itself to make | |
1339 | these instructions safe. Disabling it allows about 1K of space | |
1340 | savings. | |
1341 | ||
1342 | If you don't know what to do here, say Y. | |
1343 | ||
c9018aab VG |
1344 | config ARM_CPU_TOPOLOGY |
1345 | bool "Support cpu topology definition" | |
1346 | depends on SMP && CPU_V7 | |
1347 | default y | |
1348 | help | |
1349 | Support ARM cpu topology definition. The MPIDR register defines | |
1350 | affinity between processors which is then used to describe the cpu | |
1351 | topology of an ARM System. | |
1352 | ||
1353 | config SCHED_MC | |
1354 | bool "Multi-core scheduler support" | |
1355 | depends on ARM_CPU_TOPOLOGY | |
1356 | help | |
1357 | Multi-core scheduler support improves the CPU scheduler's decision | |
1358 | making when dealing with multi-core CPU chips at a cost of slightly | |
1359 | increased overhead in some places. If unsure say N here. | |
1360 | ||
1361 | config SCHED_SMT | |
1362 | bool "SMT scheduler support" | |
1363 | depends on ARM_CPU_TOPOLOGY | |
1364 | help | |
1365 | Improves the CPU scheduler's decision making when dealing with | |
1366 | MultiThreading at a cost of slightly increased overhead in some | |
1367 | places. If unsure say N here. | |
1368 | ||
a8cbcd92 RK |
1369 | config HAVE_ARM_SCU |
1370 | bool | |
a8cbcd92 RK |
1371 | help |
1372 | This option enables support for the ARM system coherency unit | |
1373 | ||
8a4da6e3 | 1374 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1375 | bool "Architected timer support" |
1376 | depends on CPU_V7 | |
8a4da6e3 | 1377 | select ARM_ARCH_TIMER |
0c403462 | 1378 | select GENERIC_CLOCKEVENTS |
022c03a2 MZ |
1379 | help |
1380 | This option enables support for the ARM architected timer | |
1381 | ||
f32f4ce2 RK |
1382 | config HAVE_ARM_TWD |
1383 | bool | |
1384 | depends on SMP | |
da4a686a | 1385 | select CLKSRC_OF if OF |
f32f4ce2 RK |
1386 | help |
1387 | This options enables support for the ARM timer and watchdog unit | |
1388 | ||
e8db288e NP |
1389 | config MCPM |
1390 | bool "Multi-Cluster Power Management" | |
1391 | depends on CPU_V7 && SMP | |
1392 | help | |
1393 | This option provides the common power management infrastructure | |
1394 | for (multi-)cluster based systems, such as big.LITTLE based | |
1395 | systems. | |
1396 | ||
ebf4a5c5 HZ |
1397 | config MCPM_QUAD_CLUSTER |
1398 | bool | |
1399 | depends on MCPM | |
1400 | help | |
1401 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1402 | to 2 clusters by default. | |
1403 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1404 | option to allow the additional clusters to be managed. | |
1405 | ||
1c33be57 NP |
1406 | config BIG_LITTLE |
1407 | bool "big.LITTLE support (Experimental)" | |
1408 | depends on CPU_V7 && SMP | |
1409 | select MCPM | |
1410 | help | |
1411 | This option enables support selections for the big.LITTLE | |
1412 | system architecture. | |
1413 | ||
1414 | config BL_SWITCHER | |
1415 | bool "big.LITTLE switcher support" | |
1416 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU | |
1c33be57 | 1417 | select ARM_CPU_SUSPEND |
51aaf81f | 1418 | select CPU_PM |
1c33be57 NP |
1419 | help |
1420 | The big.LITTLE "switcher" provides the core functionality to | |
1421 | transparently handle transition between a cluster of A15's | |
1422 | and a cluster of A7's in a big.LITTLE system. | |
1423 | ||
b22537c6 NP |
1424 | config BL_SWITCHER_DUMMY_IF |
1425 | tristate "Simple big.LITTLE switcher user interface" | |
1426 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1427 | help | |
1428 | This is a simple and dummy char dev interface to control | |
1429 | the big.LITTLE switcher core code. It is meant for | |
1430 | debugging purposes only. | |
1431 | ||
8d5796d2 LB |
1432 | choice |
1433 | prompt "Memory split" | |
006fa259 | 1434 | depends on MMU |
8d5796d2 LB |
1435 | default VMSPLIT_3G |
1436 | help | |
1437 | Select the desired split between kernel and user memory. | |
1438 | ||
1439 | If you are not absolutely sure what you are doing, leave this | |
1440 | option alone! | |
1441 | ||
1442 | config VMSPLIT_3G | |
1443 | bool "3G/1G user/kernel split" | |
1444 | config VMSPLIT_2G | |
1445 | bool "2G/2G user/kernel split" | |
1446 | config VMSPLIT_1G | |
1447 | bool "1G/3G user/kernel split" | |
1448 | endchoice | |
1449 | ||
1450 | config PAGE_OFFSET | |
1451 | hex | |
006fa259 | 1452 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1453 | default 0x40000000 if VMSPLIT_1G |
1454 | default 0x80000000 if VMSPLIT_2G | |
1455 | default 0xC0000000 | |
1456 | ||
1da177e4 LT |
1457 | config NR_CPUS |
1458 | int "Maximum number of CPUs (2-32)" | |
1459 | range 2 32 | |
1460 | depends on SMP | |
1461 | default "4" | |
1462 | ||
a054a811 | 1463 | config HOTPLUG_CPU |
00b7dede | 1464 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1465 | depends on SMP |
a054a811 RK |
1466 | help |
1467 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1468 | can be controlled through /sys/devices/system/cpu. | |
1469 | ||
2bdd424f WD |
1470 | config ARM_PSCI |
1471 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
1472 | depends on CPU_V7 | |
1473 | help | |
1474 | Say Y here if you want Linux to communicate with system firmware | |
1475 | implementing the PSCI specification for CPU-centric power | |
1476 | management operations described in ARM document number ARM DEN | |
1477 | 0022A ("Power State Coordination Interface System Software on | |
1478 | ARM processors"). | |
1479 | ||
2a6ad871 MR |
1480 | # The GPIO number here must be sorted by descending number. In case of |
1481 | # a multiplatform kernel, we just want the highest value required by the | |
1482 | # selected platforms. | |
44986ab0 PDSN |
1483 | config ARCH_NR_GPIO |
1484 | int | |
6a4d8f36 | 1485 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ |
aa42587a TF |
1486 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1487 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1488 | default 416 if ARCH_SUNXI |
06b851e5 | 1489 | default 392 if ARCH_U8500 |
01bb914c | 1490 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1491 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1492 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1493 | default 0 |
1494 | help | |
1495 | Maximum number of GPIOs in the system. | |
1496 | ||
1497 | If unsure, leave the default value. | |
1498 | ||
d45a398f | 1499 | source kernel/Kconfig.preempt |
1da177e4 | 1500 | |
c9218b16 | 1501 | config HZ_FIXED |
f8065813 | 1502 | int |
070b8b43 | 1503 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ |
a73ddc61 | 1504 | ARCH_S5PV210 || ARCH_EXYNOS4 |
5248c657 | 1505 | default AT91_TIMER_HZ if ARCH_AT91 |
bf98c1ea | 1506 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY |
47d84682 | 1507 | default 0 |
c9218b16 RK |
1508 | |
1509 | choice | |
47d84682 | 1510 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1511 | prompt "Timer frequency" |
1512 | ||
1513 | config HZ_100 | |
1514 | bool "100 Hz" | |
1515 | ||
1516 | config HZ_200 | |
1517 | bool "200 Hz" | |
1518 | ||
1519 | config HZ_250 | |
1520 | bool "250 Hz" | |
1521 | ||
1522 | config HZ_300 | |
1523 | bool "300 Hz" | |
1524 | ||
1525 | config HZ_500 | |
1526 | bool "500 Hz" | |
1527 | ||
1528 | config HZ_1000 | |
1529 | bool "1000 Hz" | |
1530 | ||
1531 | endchoice | |
1532 | ||
1533 | config HZ | |
1534 | int | |
47d84682 | 1535 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1536 | default 100 if HZ_100 |
1537 | default 200 if HZ_200 | |
1538 | default 250 if HZ_250 | |
1539 | default 300 if HZ_300 | |
1540 | default 500 if HZ_500 | |
1541 | default 1000 | |
1542 | ||
1543 | config SCHED_HRTICK | |
1544 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1545 | |
16c79651 | 1546 | config THUMB2_KERNEL |
bc7dea00 | 1547 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1548 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1549 | default y if CPU_THUMBONLY |
16c79651 CM |
1550 | select AEABI |
1551 | select ARM_ASM_UNIFIED | |
89bace65 | 1552 | select ARM_UNWIND |
16c79651 CM |
1553 | help |
1554 | By enabling this option, the kernel will be compiled in | |
1555 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1556 | ARM-Thumb syntax is needed. | |
1557 | ||
1558 | If unsure, say N. | |
1559 | ||
6f685c5c DM |
1560 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1561 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1562 | depends on THUMB2_KERNEL && MODULES | |
1563 | default y | |
1564 | help | |
1565 | Various binutils versions can resolve Thumb-2 branches to | |
1566 | locally-defined, preemptible global symbols as short-range "b.n" | |
1567 | branch instructions. | |
1568 | ||
1569 | This is a problem, because there's no guarantee the final | |
1570 | destination of the symbol, or any candidate locations for a | |
1571 | trampoline, are within range of the branch. For this reason, the | |
1572 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1573 | relocation in modules at all, and it makes little sense to add | |
1574 | support. | |
1575 | ||
1576 | The symptom is that the kernel fails with an "unsupported | |
1577 | relocation" error when loading some modules. | |
1578 | ||
1579 | Until fixed tools are available, passing | |
1580 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1581 | code which hits this problem, at the cost of a bit of extra runtime | |
1582 | stack usage in some cases. | |
1583 | ||
1584 | The problem is described in more detail at: | |
1585 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1586 | ||
1587 | Only Thumb-2 kernels are affected. | |
1588 | ||
1589 | Unless you are sure your tools don't have this problem, say Y. | |
1590 | ||
0becb088 CM |
1591 | config ARM_ASM_UNIFIED |
1592 | bool | |
1593 | ||
704bdda0 NP |
1594 | config AEABI |
1595 | bool "Use the ARM EABI to compile the kernel" | |
1596 | help | |
1597 | This option allows for the kernel to be compiled using the latest | |
1598 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1599 | space environment that is also compiled with EABI. | |
1600 | ||
1601 | Since there are major incompatibilities between the legacy ABI and | |
1602 | EABI, especially with regard to structure member alignment, this | |
1603 | option also changes the kernel syscall calling convention to | |
1604 | disambiguate both ABIs and allow for backward compatibility support | |
1605 | (selected with CONFIG_OABI_COMPAT). | |
1606 | ||
1607 | To use this you need GCC version 4.0.0 or later. | |
1608 | ||
6c90c872 | 1609 | config OABI_COMPAT |
a73a3ff1 | 1610 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1611 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1612 | help |
1613 | This option preserves the old syscall interface along with the | |
1614 | new (ARM EABI) one. It also provides a compatibility layer to | |
1615 | intercept syscalls that have structure arguments which layout | |
1616 | in memory differs between the legacy ABI and the new ARM EABI | |
1617 | (only for non "thumb" binaries). This option adds a tiny | |
1618 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1619 | |
1620 | The seccomp filter system will not be available when this is | |
1621 | selected, since there is no way yet to sensibly distinguish | |
1622 | between calling conventions during filtering. | |
1623 | ||
6c90c872 NP |
1624 | If you know you'll be using only pure EABI user space then you |
1625 | can say N here. If this option is not selected and you attempt | |
1626 | to execute a legacy ABI binary then the result will be | |
1627 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1628 | at all). If in doubt say N. |
6c90c872 | 1629 | |
eb33575c | 1630 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1631 | bool |
e80d6a24 | 1632 | |
05944d74 RK |
1633 | config ARCH_SPARSEMEM_ENABLE |
1634 | bool | |
1635 | ||
07a2f737 RK |
1636 | config ARCH_SPARSEMEM_DEFAULT |
1637 | def_bool ARCH_SPARSEMEM_ENABLE | |
1638 | ||
05944d74 | 1639 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1640 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1641 | |
7b7bf499 WD |
1642 | config HAVE_ARCH_PFN_VALID |
1643 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1644 | ||
b8cd51af SC |
1645 | config HAVE_GENERIC_RCU_GUP |
1646 | def_bool y | |
1647 | depends on ARM_LPAE | |
1648 | ||
053a96ca | 1649 | config HIGHMEM |
e8db89a2 RK |
1650 | bool "High Memory Support" |
1651 | depends on MMU | |
053a96ca NP |
1652 | help |
1653 | The address space of ARM processors is only 4 Gigabytes large | |
1654 | and it has to accommodate user address space, kernel address | |
1655 | space as well as some memory mapped IO. That means that, if you | |
1656 | have a large amount of physical memory and/or IO, not all of the | |
1657 | memory can be "permanently mapped" by the kernel. The physical | |
1658 | memory that is not permanently mapped is called "high memory". | |
1659 | ||
1660 | Depending on the selected kernel/user memory split, minimum | |
1661 | vmalloc space and actual amount of RAM, you may not need this | |
1662 | option which should result in a slightly faster kernel. | |
1663 | ||
1664 | If unsure, say n. | |
1665 | ||
65cec8e3 RK |
1666 | config HIGHPTE |
1667 | bool "Allocate 2nd-level pagetables from highmem" | |
1668 | depends on HIGHMEM | |
65cec8e3 | 1669 | |
1b8873a0 JI |
1670 | config HW_PERF_EVENTS |
1671 | bool "Enable hardware performance counter support for perf events" | |
f0d1bc47 | 1672 | depends on PERF_EVENTS |
1b8873a0 JI |
1673 | default y |
1674 | help | |
1675 | Enable hardware performance counter support for perf events. If | |
1676 | disabled, perf events will use software events only. | |
1677 | ||
1355e2a6 CM |
1678 | config SYS_SUPPORTS_HUGETLBFS |
1679 | def_bool y | |
1680 | depends on ARM_LPAE | |
1681 | ||
8d962507 CM |
1682 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1683 | def_bool y | |
1684 | depends on ARM_LPAE | |
1685 | ||
4bfab203 SC |
1686 | config ARCH_WANT_GENERAL_HUGETLB |
1687 | def_bool y | |
1688 | ||
3f22ab27 DH |
1689 | source "mm/Kconfig" |
1690 | ||
c1b2d970 | 1691 | config FORCE_MAX_ZONEORDER |
bf98c1ea LP |
1692 | int "Maximum zone order" if ARCH_SHMOBILE_LEGACY |
1693 | range 11 64 if ARCH_SHMOBILE_LEGACY | |
898f08e1 | 1694 | default "12" if SOC_AM33XX |
6d85e2b0 | 1695 | default "9" if SA1111 || ARCH_EFM32 |
c1b2d970 MD |
1696 | default "11" |
1697 | help | |
1698 | The kernel memory allocator divides physically contiguous memory | |
1699 | blocks into "zones", where each zone is a power of two number of | |
1700 | pages. This option selects the largest power of two that the kernel | |
1701 | keeps in the memory allocator. If you need to allocate very large | |
1702 | blocks of physically contiguous memory, then you may need to | |
1703 | increase this value. | |
1704 | ||
1705 | This config option is actually maximum order plus one. For example, | |
1706 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1707 | ||
1da177e4 LT |
1708 | config ALIGNMENT_TRAP |
1709 | bool | |
f12d0d7c | 1710 | depends on CPU_CP15_MMU |
1da177e4 | 1711 | default y if !ARCH_EBSA110 |
e119bfff | 1712 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1713 | help |
84eb8d06 | 1714 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1715 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1716 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1717 | fetch/store instructions will be emulated in software if you say | |
1718 | here, which has a severe performance impact. This is necessary for | |
1719 | correct operation of some network protocols. With an IP-only | |
1720 | configuration it is safe to say N, otherwise say Y. | |
1721 | ||
39ec58f3 | 1722 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1723 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1724 | depends on MMU | |
39ec58f3 LB |
1725 | default y if CPU_FEROCEON |
1726 | help | |
1727 | Implement faster copy_to_user and clear_user methods for CPU | |
1728 | cores where a 8-word STM instruction give significantly higher | |
1729 | memory write throughput than a sequence of individual 32bit stores. | |
1730 | ||
1731 | A possible side effect is a slight increase in scheduling latency | |
1732 | between threads sharing the same address space if they invoke | |
1733 | such copy operations with large buffers. | |
1734 | ||
1735 | However, if the CPU data cache is using a write-allocate mode, | |
1736 | this option is unlikely to provide any performance gain. | |
1737 | ||
70c70d97 NP |
1738 | config SECCOMP |
1739 | bool | |
1740 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1741 | ---help--- | |
1742 | This kernel feature is useful for number crunching applications | |
1743 | that may need to compute untrusted bytecode during their | |
1744 | execution. By using pipes or other transports made available to | |
1745 | the process as file descriptors supporting the read/write | |
1746 | syscalls, it's possible to isolate those applications in | |
1747 | their own address space using seccomp. Once seccomp is | |
1748 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1749 | and the task is only allowed to execute a few safe syscalls | |
1750 | defined by each seccomp mode. | |
1751 | ||
06e6295b SS |
1752 | config SWIOTLB |
1753 | def_bool y | |
1754 | ||
1755 | config IOMMU_HELPER | |
1756 | def_bool SWIOTLB | |
1757 | ||
eff8d644 SS |
1758 | config XEN_DOM0 |
1759 | def_bool y | |
1760 | depends on XEN | |
1761 | ||
1762 | config XEN | |
c2ba1f7d | 1763 | bool "Xen guest support on ARM" |
85323a99 | 1764 | depends on ARM && AEABI && OF |
f880b67d | 1765 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1766 | depends on !GENERIC_ATOMIC64 |
7693decc | 1767 | depends on MMU |
51aaf81f | 1768 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1769 | select ARM_PSCI |
83862ccf | 1770 | select SWIOTLB_XEN |
eff8d644 SS |
1771 | help |
1772 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1773 | ||
1da177e4 LT |
1774 | endmenu |
1775 | ||
1776 | menu "Boot options" | |
1777 | ||
9eb8f674 GL |
1778 | config USE_OF |
1779 | bool "Flattened Device Tree support" | |
b1b3f49c | 1780 | select IRQ_DOMAIN |
9eb8f674 GL |
1781 | select OF |
1782 | select OF_EARLY_FLATTREE | |
bcedb5f9 | 1783 | select OF_RESERVED_MEM |
9eb8f674 GL |
1784 | help |
1785 | Include support for flattened device tree machine descriptions. | |
1786 | ||
bd51e2f5 NP |
1787 | config ATAGS |
1788 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1789 | default y | |
1790 | help | |
1791 | This is the traditional way of passing data to the kernel at boot | |
1792 | time. If you are solely relying on the flattened device tree (or | |
1793 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1794 | to remove ATAGS support from your kernel binary. If unsure, | |
1795 | leave this to y. | |
1796 | ||
1797 | config DEPRECATED_PARAM_STRUCT | |
1798 | bool "Provide old way to pass kernel parameters" | |
1799 | depends on ATAGS | |
1800 | help | |
1801 | This was deprecated in 2001 and announced to live on for 5 years. | |
1802 | Some old boot loaders still use this way. | |
1803 | ||
1da177e4 LT |
1804 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1805 | # TEXT and BSS so we preserve their values in the config files. | |
1806 | config ZBOOT_ROM_TEXT | |
1807 | hex "Compressed ROM boot loader base address" | |
1808 | default "0" | |
1809 | help | |
1810 | The physical address at which the ROM-able zImage is to be | |
1811 | placed in the target. Platforms which normally make use of | |
1812 | ROM-able zImage formats normally set this to a suitable | |
1813 | value in their defconfig file. | |
1814 | ||
1815 | If ZBOOT_ROM is not enabled, this has no effect. | |
1816 | ||
1817 | config ZBOOT_ROM_BSS | |
1818 | hex "Compressed ROM boot loader BSS address" | |
1819 | default "0" | |
1820 | help | |
f8c440b2 DF |
1821 | The base address of an area of read/write memory in the target |
1822 | for the ROM-able zImage which must be available while the | |
1823 | decompressor is running. It must be large enough to hold the | |
1824 | entire decompressed kernel plus an additional 128 KiB. | |
1825 | Platforms which normally make use of ROM-able zImage formats | |
1826 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1827 | |
1828 | If ZBOOT_ROM is not enabled, this has no effect. | |
1829 | ||
1830 | config ZBOOT_ROM | |
1831 | bool "Compressed boot loader in ROM/flash" | |
1832 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1833 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1834 | help |
1835 | Say Y here if you intend to execute your compressed kernel image | |
1836 | (zImage) directly from ROM or flash. If unsure, say N. | |
1837 | ||
090ab3ff SH |
1838 | choice |
1839 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1840 | depends on ZBOOT_ROM && ARCH_SH7372 |
090ab3ff SH |
1841 | default ZBOOT_ROM_NONE |
1842 | help | |
1843 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
59bf8964 | 1844 | With this enabled it is possible to write the ROM-able zImage |
090ab3ff SH |
1845 | kernel image to an MMC or SD card and boot the kernel straight |
1846 | from the reset vector. At reset the processor Mask ROM will load | |
59bf8964 | 1847 | the first part of the ROM-able zImage which in turn loads the |
090ab3ff SH |
1848 | rest the kernel image to RAM. |
1849 | ||
1850 | config ZBOOT_ROM_NONE | |
1851 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1852 | help | |
1853 | Do not load image from SD or MMC | |
1854 | ||
f45b1149 SH |
1855 | config ZBOOT_ROM_MMCIF |
1856 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
f45b1149 | 1857 | help |
090ab3ff SH |
1858 | Load image from MMCIF hardware block. |
1859 | ||
1860 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
1861 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
1862 | help | |
1863 | Load image from SDHI hardware block | |
1864 | ||
1865 | endchoice | |
f45b1149 | 1866 | |
e2a6a3aa JB |
1867 | config ARM_APPENDED_DTB |
1868 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1869 | depends on OF |
e2a6a3aa JB |
1870 | help |
1871 | With this option, the boot code will look for a device tree binary | |
1872 | (DTB) appended to zImage | |
1873 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1874 | ||
1875 | This is meant as a backward compatibility convenience for those | |
1876 | systems with a bootloader that can't be upgraded to accommodate | |
1877 | the documented boot protocol using a device tree. | |
1878 | ||
1879 | Beware that there is very little in terms of protection against | |
1880 | this option being confused by leftover garbage in memory that might | |
1881 | look like a DTB header after a reboot if no actual DTB is appended | |
1882 | to zImage. Do not leave this option active in a production kernel | |
1883 | if you don't intend to always append a DTB. Proper passing of the | |
1884 | location into r2 of a bootloader provided DTB is always preferable | |
1885 | to this option. | |
1886 | ||
b90b9a38 NP |
1887 | config ARM_ATAG_DTB_COMPAT |
1888 | bool "Supplement the appended DTB with traditional ATAG information" | |
1889 | depends on ARM_APPENDED_DTB | |
1890 | help | |
1891 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1892 | they provide ATAGs with memory configuration, the ramdisk address, | |
1893 | the kernel cmdline string, etc. Such information is dynamically | |
1894 | provided by the bootloader and can't always be stored in a static | |
1895 | DTB. To allow a device tree enabled kernel to be used with such | |
1896 | bootloaders, this option allows zImage to extract the information | |
1897 | from the ATAG list and store it at run time into the appended DTB. | |
1898 | ||
d0f34a11 GR |
1899 | choice |
1900 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1901 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1902 | ||
1903 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1904 | bool "Use bootloader kernel arguments if available" | |
1905 | help | |
1906 | Uses the command-line options passed by the boot loader instead of | |
1907 | the device tree bootargs property. If the boot loader doesn't provide | |
1908 | any, the device tree bootargs property will be used. | |
1909 | ||
1910 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1911 | bool "Extend with bootloader kernel arguments" | |
1912 | help | |
1913 | The command-line arguments provided by the boot loader will be | |
1914 | appended to the the device tree bootargs property. | |
1915 | ||
1916 | endchoice | |
1917 | ||
1da177e4 LT |
1918 | config CMDLINE |
1919 | string "Default kernel command string" | |
1920 | default "" | |
1921 | help | |
1922 | On some architectures (EBSA110 and CATS), there is currently no way | |
1923 | for the boot loader to pass arguments to the kernel. For these | |
1924 | architectures, you should supply some command-line options at build | |
1925 | time by entering them here. As a minimum, you should specify the | |
1926 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1927 | ||
4394c124 VB |
1928 | choice |
1929 | prompt "Kernel command line type" if CMDLINE != "" | |
1930 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1931 | depends on ATAGS |
4394c124 VB |
1932 | |
1933 | config CMDLINE_FROM_BOOTLOADER | |
1934 | bool "Use bootloader kernel arguments if available" | |
1935 | help | |
1936 | Uses the command-line options passed by the boot loader. If | |
1937 | the boot loader doesn't provide any, the default kernel command | |
1938 | string provided in CMDLINE will be used. | |
1939 | ||
1940 | config CMDLINE_EXTEND | |
1941 | bool "Extend bootloader kernel arguments" | |
1942 | help | |
1943 | The command-line arguments provided by the boot loader will be | |
1944 | appended to the default kernel command string. | |
1945 | ||
92d2040d AH |
1946 | config CMDLINE_FORCE |
1947 | bool "Always use the default kernel command string" | |
92d2040d AH |
1948 | help |
1949 | Always use the default kernel command string, even if the boot | |
1950 | loader passes other arguments to the kernel. | |
1951 | This is useful if you cannot or don't want to change the | |
1952 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1953 | endchoice |
92d2040d | 1954 | |
1da177e4 LT |
1955 | config XIP_KERNEL |
1956 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1957 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1958 | help |
1959 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1960 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1961 | space since the text section of the kernel is not loaded from flash | |
1962 | to RAM. Read-write sections, such as the data section and stack, | |
1963 | are still copied to RAM. The XIP kernel is not compressed since | |
1964 | it has to run directly from flash, so it will take more space to | |
1965 | store it. The flash address used to link the kernel object files, | |
1966 | and for storing it, is configuration dependent. Therefore, if you | |
1967 | say Y here, you must know the proper physical address where to | |
1968 | store the kernel image depending on your own flash memory usage. | |
1969 | ||
1970 | Also note that the make target becomes "make xipImage" rather than | |
1971 | "make zImage" or "make Image". The final kernel binary to put in | |
1972 | ROM memory will be arch/arm/boot/xipImage. | |
1973 | ||
1974 | If unsure, say N. | |
1975 | ||
1976 | config XIP_PHYS_ADDR | |
1977 | hex "XIP Kernel Physical Location" | |
1978 | depends on XIP_KERNEL | |
1979 | default "0x00080000" | |
1980 | help | |
1981 | This is the physical address in your flash memory the kernel will | |
1982 | be linked for and stored to. This address is dependent on your | |
1983 | own flash usage. | |
1984 | ||
c587e4a6 RP |
1985 | config KEXEC |
1986 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 1987 | depends on (!SMP || PM_SLEEP_SMP) |
c587e4a6 RP |
1988 | help |
1989 | kexec is a system call that implements the ability to shutdown your | |
1990 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 1991 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
1992 | you can start any kernel with it, not just Linux. |
1993 | ||
1994 | It is an ongoing process to be certain the hardware in a machine | |
1995 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 1996 | initially work for you. |
c587e4a6 | 1997 | |
4cd9d6f7 RP |
1998 | config ATAGS_PROC |
1999 | bool "Export atags in procfs" | |
bd51e2f5 | 2000 | depends on ATAGS && KEXEC |
b98d7291 | 2001 | default y |
4cd9d6f7 RP |
2002 | help |
2003 | Should the atags used to boot the kernel be exported in an "atags" | |
2004 | file in procfs. Useful with kexec. | |
2005 | ||
cb5d39b3 MW |
2006 | config CRASH_DUMP |
2007 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2008 | help |
2009 | Generate crash dump after being started by kexec. This should | |
2010 | be normally only set in special crash dump kernels which are | |
2011 | loaded in the main kernel with kexec-tools into a specially | |
2012 | reserved region and then later executed after a crash by | |
2013 | kdump/kexec. The crash dump kernel must be compiled to a | |
2014 | memory address not used by the main kernel | |
2015 | ||
2016 | For more details see Documentation/kdump/kdump.txt | |
2017 | ||
e69edc79 EM |
2018 | config AUTO_ZRELADDR |
2019 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
2020 | help |
2021 | ZRELADDR is the physical address where the decompressed kernel | |
2022 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2023 | will be determined at run-time by masking the current IP with | |
2024 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2025 | from start of memory. | |
2026 | ||
1da177e4 LT |
2027 | endmenu |
2028 | ||
ac9d7efc | 2029 | menu "CPU Power Management" |
1da177e4 | 2030 | |
1da177e4 | 2031 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 2032 | |
ac9d7efc RK |
2033 | source "drivers/cpuidle/Kconfig" |
2034 | ||
2035 | endmenu | |
2036 | ||
1da177e4 LT |
2037 | menu "Floating point emulation" |
2038 | ||
2039 | comment "At least one emulation must be selected" | |
2040 | ||
2041 | config FPE_NWFPE | |
2042 | bool "NWFPE math emulation" | |
593c252a | 2043 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2044 | ---help--- |
2045 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2046 | This is necessary to run most binaries. Linux does not currently | |
2047 | support floating point hardware so you need to say Y here even if | |
2048 | your machine has an FPA or floating point co-processor podule. | |
2049 | ||
2050 | You may say N here if you are going to load the Acorn FPEmulator | |
2051 | early in the bootup. | |
2052 | ||
2053 | config FPE_NWFPE_XP | |
2054 | bool "Support extended precision" | |
bedf142b | 2055 | depends on FPE_NWFPE |
1da177e4 LT |
2056 | help |
2057 | Say Y to include 80-bit support in the kernel floating-point | |
2058 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2059 | Note that gcc does not generate 80-bit operations by default, | |
2060 | so in most cases this option only enlarges the size of the | |
2061 | floating point emulator without any good reason. | |
2062 | ||
2063 | You almost surely want to say N here. | |
2064 | ||
2065 | config FPE_FASTFPE | |
2066 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2067 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2068 | ---help--- |
2069 | Say Y here to include the FAST floating point emulator in the kernel. | |
2070 | This is an experimental much faster emulator which now also has full | |
2071 | precision for the mantissa. It does not support any exceptions. | |
2072 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2073 | ||
2074 | It should be sufficient for most programs. It may be not suitable | |
2075 | for scientific calculations, but you have to check this for yourself. | |
2076 | If you do not feel you need a faster FP emulation you should better | |
2077 | choose NWFPE. | |
2078 | ||
2079 | config VFP | |
2080 | bool "VFP-format floating point maths" | |
e399b1a4 | 2081 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2082 | help |
2083 | Say Y to include VFP support code in the kernel. This is needed | |
2084 | if your hardware includes a VFP unit. | |
2085 | ||
2086 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2087 | release notes and additional status information. | |
2088 | ||
2089 | Say N if your target does not have VFP hardware. | |
2090 | ||
25ebee02 CM |
2091 | config VFPv3 |
2092 | bool | |
2093 | depends on VFP | |
2094 | default y if CPU_V7 | |
2095 | ||
b5872db4 CM |
2096 | config NEON |
2097 | bool "Advanced SIMD (NEON) Extension support" | |
2098 | depends on VFPv3 && CPU_V7 | |
2099 | help | |
2100 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2101 | Extension. | |
2102 | ||
73c132c1 AB |
2103 | config KERNEL_MODE_NEON |
2104 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 2105 | depends on NEON && AEABI |
73c132c1 AB |
2106 | help |
2107 | Say Y to include support for NEON in kernel mode. | |
2108 | ||
1da177e4 LT |
2109 | endmenu |
2110 | ||
2111 | menu "Userspace binary formats" | |
2112 | ||
2113 | source "fs/Kconfig.binfmt" | |
2114 | ||
2115 | config ARTHUR | |
2116 | tristate "RISC OS personality" | |
704bdda0 | 2117 | depends on !AEABI |
1da177e4 LT |
2118 | help |
2119 | Say Y here to include the kernel code necessary if you want to run | |
2120 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2121 | experimental; if this sounds frightening, say N and sleep in peace. | |
2122 | You can also say M here to compile this support as a module (which | |
2123 | will be called arthur). | |
2124 | ||
2125 | endmenu | |
2126 | ||
2127 | menu "Power management options" | |
2128 | ||
eceab4ac | 2129 | source "kernel/power/Kconfig" |
1da177e4 | 2130 | |
f4cb5700 | 2131 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 2132 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 2133 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2134 | def_bool y |
2135 | ||
15e0d9e3 AB |
2136 | config ARM_CPU_SUSPEND |
2137 | def_bool PM_SLEEP | |
2138 | ||
603fb42a SC |
2139 | config ARCH_HIBERNATION_POSSIBLE |
2140 | bool | |
2141 | depends on MMU | |
2142 | default y if ARCH_SUSPEND_POSSIBLE | |
2143 | ||
1da177e4 LT |
2144 | endmenu |
2145 | ||
d5950b43 SR |
2146 | source "net/Kconfig" |
2147 | ||
ac25150f | 2148 | source "drivers/Kconfig" |
1da177e4 LT |
2149 | |
2150 | source "fs/Kconfig" | |
2151 | ||
1da177e4 LT |
2152 | source "arch/arm/Kconfig.debug" |
2153 | ||
2154 | source "security/Kconfig" | |
2155 | ||
2156 | source "crypto/Kconfig" | |
2157 | ||
2158 | source "lib/Kconfig" | |
749cf76c CD |
2159 | |
2160 | source "arch/arm/kvm/Kconfig" |