Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
b1b3f49c RK |
4 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE |
5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE | |
3d06770e | 6 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 7 | select ARCH_HAVE_CUSTOM_GPIO_H |
d7018848 | 8 | select ARCH_MIGHT_HAVE_PC_PARPORT |
0cbad9c9 | 9 | select ARCH_USE_CMPXCHG_LOCKREF |
b1b3f49c | 10 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 11 | select BUILDTIME_EXTABLE_SORT if MMU |
171b3f0d | 12 | select CLONE_BACKWARDS |
b1b3f49c | 13 | select CPU_PM if (SUSPEND || CPU_IDLE) |
39b175a0 | 14 | select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU |
4477ca45 | 15 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c | 16 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
171b3f0d | 17 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
18 | select GENERIC_IRQ_PROBE |
19 | select GENERIC_IRQ_SHOW | |
b1b3f49c | 20 | select GENERIC_PCI_IOMAP |
38ff87f7 | 21 | select GENERIC_SCHED_CLOCK |
b1b3f49c RK |
22 | select GENERIC_SMP_IDLE_THREAD |
23 | select GENERIC_STRNCPY_FROM_USER | |
24 | select GENERIC_STRNLEN_USER | |
25 | select HARDIRQS_SW_RESEND | |
09f05d85 | 26 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL |
5cbad0eb | 27 | select HAVE_ARCH_KGDB |
91702175 | 28 | select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) |
0693bf68 | 29 | select HAVE_ARCH_TRACEHOOK |
b1b3f49c | 30 | select HAVE_BPF_JIT |
171b3f0d | 31 | select HAVE_CONTEXT_TRACKING |
b1b3f49c RK |
32 | select HAVE_C_RECORDMCOUNT |
33 | select HAVE_DEBUG_KMEMLEAK | |
34 | select HAVE_DMA_API_DEBUG | |
35 | select HAVE_DMA_ATTRS | |
36 | select HAVE_DMA_CONTIGUOUS if MMU | |
80be7a7f | 37 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) |
b1b3f49c | 38 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 39 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 40 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
1fe53268 | 41 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
42 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
43 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 44 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 45 | select HAVE_KERNEL_GZIP |
f9b493ac | 46 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 47 | select HAVE_KERNEL_LZMA |
b1b3f49c | 48 | select HAVE_KERNEL_LZO |
a7f464f3 | 49 | select HAVE_KERNEL_XZ |
b1b3f49c RK |
50 | select HAVE_KPROBES if !XIP_KERNEL |
51 | select HAVE_KRETPROBES if (HAVE_KPROBES) | |
52 | select HAVE_MEMBLOCK | |
171b3f0d | 53 | select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND |
b1b3f49c | 54 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
7ada189f | 55 | select HAVE_PERF_EVENTS |
49863894 WD |
56 | select HAVE_PERF_REGS |
57 | select HAVE_PERF_USER_STACK_DUMP | |
e513f8bf | 58 | select HAVE_REGS_AND_STACK_ACCESS_API |
b1b3f49c | 59 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 60 | select HAVE_UID16 |
31c1fc81 | 61 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 62 | select IRQ_FORCED_THREADING |
3d92a71a | 63 | select KTIME_SCALAR |
171b3f0d RK |
64 | select MODULES_USE_ELF_REL |
65 | select OLD_SIGACTION | |
66 | select OLD_SIGSUSPEND3 | |
b1b3f49c RK |
67 | select PERF_USE_VMALLOC |
68 | select RTC_LIB | |
69 | select SYS_SUPPORTS_APM_EMULATION | |
171b3f0d RK |
70 | # Above selects are sorted alphabetically; please add new ones |
71 | # according to that. Thanks. | |
1da177e4 LT |
72 | help |
73 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 74 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 75 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 76 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
77 | Europe. There is an ARM Linux project with a web page at |
78 | <http://www.arm.linux.org.uk/>. | |
79 | ||
74facffe RK |
80 | config ARM_HAS_SG_CHAIN |
81 | bool | |
82 | ||
4ce63fcd MS |
83 | config NEED_SG_DMA_LENGTH |
84 | bool | |
85 | ||
86 | config ARM_DMA_USE_IOMMU | |
4ce63fcd | 87 | bool |
b1b3f49c RK |
88 | select ARM_HAS_SG_CHAIN |
89 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 90 | |
60460abf SWK |
91 | if ARM_DMA_USE_IOMMU |
92 | ||
93 | config ARM_DMA_IOMMU_ALIGNMENT | |
94 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
95 | range 4 9 | |
96 | default 8 | |
97 | help | |
98 | DMA mapping framework by default aligns all buffers to the smallest | |
99 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
100 | size. This works well for buffers up to a few hundreds kilobytes, but | |
101 | for larger buffers it just a waste of address space. Drivers which has | |
102 | relatively small addressing window (like 64Mib) might run out of | |
103 | virtual space with just a few allocations. | |
104 | ||
105 | With this parameter you can specify the maximum PAGE_SIZE order for | |
106 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
107 | specified order. The order is expressed as a power of two multiplied | |
108 | by the PAGE_SIZE. | |
109 | ||
110 | endif | |
111 | ||
1a189b97 RK |
112 | config HAVE_PWM |
113 | bool | |
114 | ||
0b05da72 HUK |
115 | config MIGHT_HAVE_PCI |
116 | bool | |
117 | ||
75e7153a RB |
118 | config SYS_SUPPORTS_APM_EMULATION |
119 | bool | |
120 | ||
bc581770 LW |
121 | config HAVE_TCM |
122 | bool | |
123 | select GENERIC_ALLOCATOR | |
124 | ||
e119bfff RK |
125 | config HAVE_PROC_CPU |
126 | bool | |
127 | ||
5ea81769 AV |
128 | config NO_IOPORT |
129 | bool | |
5ea81769 | 130 | |
1da177e4 LT |
131 | config EISA |
132 | bool | |
133 | ---help--- | |
134 | The Extended Industry Standard Architecture (EISA) bus was | |
135 | developed as an open alternative to the IBM MicroChannel bus. | |
136 | ||
137 | The EISA bus provided some of the features of the IBM MicroChannel | |
138 | bus while maintaining backward compatibility with cards made for | |
139 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
140 | 1995 when it was made obsolete by the PCI bus. | |
141 | ||
142 | Say Y here if you are building a kernel for an EISA-based machine. | |
143 | ||
144 | Otherwise, say N. | |
145 | ||
146 | config SBUS | |
147 | bool | |
148 | ||
f16fb1ec RK |
149 | config STACKTRACE_SUPPORT |
150 | bool | |
151 | default y | |
152 | ||
f76e9154 NP |
153 | config HAVE_LATENCYTOP_SUPPORT |
154 | bool | |
155 | depends on !SMP | |
156 | default y | |
157 | ||
f16fb1ec RK |
158 | config LOCKDEP_SUPPORT |
159 | bool | |
160 | default y | |
161 | ||
7ad1bcb2 RK |
162 | config TRACE_IRQFLAGS_SUPPORT |
163 | bool | |
164 | default y | |
165 | ||
1da177e4 LT |
166 | config RWSEM_GENERIC_SPINLOCK |
167 | bool | |
168 | default y | |
169 | ||
170 | config RWSEM_XCHGADD_ALGORITHM | |
171 | bool | |
172 | ||
f0d1b0b3 DH |
173 | config ARCH_HAS_ILOG2_U32 |
174 | bool | |
f0d1b0b3 DH |
175 | |
176 | config ARCH_HAS_ILOG2_U64 | |
177 | bool | |
f0d1b0b3 | 178 | |
89c52ed4 BD |
179 | config ARCH_HAS_CPUFREQ |
180 | bool | |
181 | help | |
182 | Internal node to signify that the ARCH has CPUFREQ support | |
183 | and that the relevant menu configurations are displayed for | |
184 | it. | |
185 | ||
4a1b5733 EV |
186 | config ARCH_HAS_BANDGAP |
187 | bool | |
188 | ||
b89c3b16 AM |
189 | config GENERIC_HWEIGHT |
190 | bool | |
191 | default y | |
192 | ||
1da177e4 LT |
193 | config GENERIC_CALIBRATE_DELAY |
194 | bool | |
195 | default y | |
196 | ||
a08b6b79 Z |
197 | config ARCH_MAY_HAVE_PC_FDC |
198 | bool | |
199 | ||
5ac6da66 CL |
200 | config ZONE_DMA |
201 | bool | |
5ac6da66 | 202 | |
ccd7ab7f FT |
203 | config NEED_DMA_MAP_STATE |
204 | def_bool y | |
205 | ||
58af4a24 RH |
206 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
207 | bool | |
208 | ||
1da177e4 LT |
209 | config GENERIC_ISA_DMA |
210 | bool | |
211 | ||
1da177e4 LT |
212 | config FIQ |
213 | bool | |
214 | ||
13a5045d RH |
215 | config NEED_RET_TO_USER |
216 | bool | |
217 | ||
034d2f5a AV |
218 | config ARCH_MTD_XIP |
219 | bool | |
220 | ||
c760fc19 HC |
221 | config VECTORS_BASE |
222 | hex | |
6afd6fae | 223 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
224 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
225 | default 0x00000000 | |
226 | help | |
19accfd3 RK |
227 | The base address of exception vectors. This must be two pages |
228 | in size. | |
c760fc19 | 229 | |
dc21af99 | 230 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
231 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
232 | default y | |
b511d75d | 233 | depends on !XIP_KERNEL && MMU |
dc21af99 RK |
234 | depends on !ARCH_REALVIEW || !SPARSEMEM |
235 | help | |
111e9a5c RK |
236 | Patch phys-to-virt and virt-to-phys translation functions at |
237 | boot and module load time according to the position of the | |
238 | kernel in system memory. | |
dc21af99 | 239 | |
111e9a5c | 240 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 241 | of physical memory is at a 16MB boundary. |
dc21af99 | 242 | |
c1becedc RK |
243 | Only disable this option if you know that you do not require |
244 | this feature (eg, building a kernel for a single machine) and | |
245 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 246 | |
01464226 RH |
247 | config NEED_MACH_GPIO_H |
248 | bool | |
249 | help | |
250 | Select this when mach/gpio.h is required to provide special | |
251 | definitions for this platform. The need for mach/gpio.h should | |
252 | be avoided when possible. | |
253 | ||
c334bc15 RH |
254 | config NEED_MACH_IO_H |
255 | bool | |
256 | help | |
257 | Select this when mach/io.h is required to provide special | |
258 | definitions for this platform. The need for mach/io.h should | |
259 | be avoided when possible. | |
260 | ||
0cdc8b92 | 261 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
262 | bool |
263 | help | |
0cdc8b92 NP |
264 | Select this when mach/memory.h is required to provide special |
265 | definitions for this platform. The need for mach/memory.h should | |
266 | be avoided when possible. | |
dc21af99 | 267 | |
1b9f95f8 | 268 | config PHYS_OFFSET |
974c0724 | 269 | hex "Physical address of main memory" if MMU |
0cdc8b92 | 270 | depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H |
974c0724 | 271 | default DRAM_BASE if !MMU |
111e9a5c | 272 | help |
1b9f95f8 NP |
273 | Please provide the physical address corresponding to the |
274 | location of main memory in your system. | |
cada3c08 | 275 | |
87e040b6 SG |
276 | config GENERIC_BUG |
277 | def_bool y | |
278 | depends on BUG | |
279 | ||
1da177e4 LT |
280 | source "init/Kconfig" |
281 | ||
dc52ddc0 MH |
282 | source "kernel/Kconfig.freezer" |
283 | ||
1da177e4 LT |
284 | menu "System Type" |
285 | ||
3c427975 HC |
286 | config MMU |
287 | bool "MMU-based Paged Memory Management Support" | |
288 | default y | |
289 | help | |
290 | Select if you want MMU-based virtualised addressing space | |
291 | support by paged memory management. If unsure, say 'Y'. | |
292 | ||
ccf50e23 RK |
293 | # |
294 | # The "ARM system type" choice list is ordered alphabetically by option | |
295 | # text. Please add new entries in the option alphabetic order. | |
296 | # | |
1da177e4 LT |
297 | choice |
298 | prompt "ARM system type" | |
1420b22b AB |
299 | default ARCH_VERSATILE if !MMU |
300 | default ARCH_MULTIPLATFORM if MMU | |
1da177e4 | 301 | |
387798b3 RH |
302 | config ARCH_MULTIPLATFORM |
303 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 304 | depends on MMU |
387798b3 RH |
305 | select ARM_PATCH_PHYS_VIRT |
306 | select AUTO_ZRELADDR | |
66314223 | 307 | select COMMON_CLK |
387798b3 | 308 | select MULTI_IRQ_HANDLER |
66314223 DN |
309 | select SPARSE_IRQ |
310 | select USE_OF | |
66314223 | 311 | |
4af6fee1 DS |
312 | config ARCH_INTEGRATOR |
313 | bool "ARM Ltd. Integrator family" | |
89c52ed4 | 314 | select ARCH_HAS_CPUFREQ |
b1b3f49c | 315 | select ARM_AMBA |
a613163d | 316 | select COMMON_CLK |
f9a6aa43 | 317 | select COMMON_CLK_VERSATILE |
b1b3f49c | 318 | select GENERIC_CLOCKEVENTS |
9904f793 | 319 | select HAVE_TCM |
c5a0adb5 | 320 | select ICST |
b1b3f49c RK |
321 | select MULTI_IRQ_HANDLER |
322 | select NEED_MACH_MEMORY_H | |
f4b8b319 | 323 | select PLAT_VERSATILE |
695436e3 | 324 | select SPARSE_IRQ |
d7057e1d | 325 | select USE_OF |
2389d501 | 326 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
327 | help |
328 | Support for ARM's Integrator platform. | |
329 | ||
330 | config ARCH_REALVIEW | |
331 | bool "ARM Ltd. RealView family" | |
b1b3f49c | 332 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 333 | select ARM_AMBA |
b1b3f49c | 334 | select ARM_TIMER_SP804 |
f9a6aa43 LW |
335 | select COMMON_CLK |
336 | select COMMON_CLK_VERSATILE | |
ae30ceac | 337 | select GENERIC_CLOCKEVENTS |
b56ba8aa | 338 | select GPIO_PL061 if GPIOLIB |
b1b3f49c | 339 | select ICST |
0cdc8b92 | 340 | select NEED_MACH_MEMORY_H |
b1b3f49c RK |
341 | select PLAT_VERSATILE |
342 | select PLAT_VERSATILE_CLCD | |
4af6fee1 DS |
343 | help |
344 | This enables support for ARM Ltd RealView boards. | |
345 | ||
346 | config ARCH_VERSATILE | |
347 | bool "ARM Ltd. Versatile family" | |
b1b3f49c | 348 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 349 | select ARM_AMBA |
b1b3f49c | 350 | select ARM_TIMER_SP804 |
4af6fee1 | 351 | select ARM_VIC |
6d803ba7 | 352 | select CLKDEV_LOOKUP |
b1b3f49c | 353 | select GENERIC_CLOCKEVENTS |
aa3831cf | 354 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 355 | select ICST |
f4b8b319 | 356 | select PLAT_VERSATILE |
3414ba8c | 357 | select PLAT_VERSATILE_CLCD |
b1b3f49c | 358 | select PLAT_VERSATILE_CLOCK |
2389d501 | 359 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
360 | help |
361 | This enables support for ARM Ltd Versatile board. | |
362 | ||
8fc5ffa0 AV |
363 | config ARCH_AT91 |
364 | bool "Atmel AT91" | |
f373e8c0 | 365 | select ARCH_REQUIRE_GPIOLIB |
bd602995 | 366 | select CLKDEV_LOOKUP |
e261501d | 367 | select IRQ_DOMAIN |
01464226 | 368 | select NEED_MACH_GPIO_H |
1ac02d79 | 369 | select NEED_MACH_IO_H if PCCARD |
6732ae5c JCPV |
370 | select PINCTRL |
371 | select PINCTRL_AT91 if USE_OF | |
4af6fee1 | 372 | help |
929e994f NF |
373 | This enables support for systems based on Atmel |
374 | AT91RM9200 and AT91SAM9* processors. | |
4af6fee1 | 375 | |
93e22567 RK |
376 | config ARCH_CLPS711X |
377 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" | |
a3b8d4a5 | 378 | select ARCH_REQUIRE_GPIOLIB |
ea7d1bc9 | 379 | select AUTO_ZRELADDR |
c99f72ad | 380 | select CLKSRC_MMIO |
93e22567 RK |
381 | select COMMON_CLK |
382 | select CPU_ARM720T | |
4a8355c4 | 383 | select GENERIC_CLOCKEVENTS |
6597619f | 384 | select MFD_SYSCON |
99f04c8f | 385 | select MULTI_IRQ_HANDLER |
0d8be81c | 386 | select SPARSE_IRQ |
93e22567 RK |
387 | help |
388 | Support for Cirrus Logic 711x/721x/731x based boards. | |
389 | ||
788c9700 RK |
390 | config ARCH_GEMINI |
391 | bool "Cortina Systems Gemini" | |
788c9700 | 392 | select ARCH_REQUIRE_GPIOLIB |
f3372c01 | 393 | select CLKSRC_MMIO |
b1b3f49c | 394 | select CPU_FA526 |
f3372c01 | 395 | select GENERIC_CLOCKEVENTS |
788c9700 RK |
396 | help |
397 | Support for the Cortina Systems Gemini family SoCs | |
398 | ||
1da177e4 LT |
399 | config ARCH_EBSA110 |
400 | bool "EBSA-110" | |
b1b3f49c | 401 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 402 | select CPU_SA110 |
f7e68bbf | 403 | select ISA |
c334bc15 | 404 | select NEED_MACH_IO_H |
0cdc8b92 | 405 | select NEED_MACH_MEMORY_H |
b1b3f49c | 406 | select NO_IOPORT |
1da177e4 LT |
407 | help |
408 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 409 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
410 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
411 | parallel port. | |
412 | ||
6d85e2b0 UKK |
413 | config ARCH_EFM32 |
414 | bool "Energy Micro efm32" | |
415 | depends on !MMU | |
416 | select ARCH_REQUIRE_GPIOLIB | |
417 | select ARM_NVIC | |
418 | # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged, | |
419 | # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO | |
420 | select CLKSRC_MMIO | |
421 | select CLKSRC_OF | |
422 | select COMMON_CLK | |
423 | select CPU_V7M | |
424 | select GENERIC_CLOCKEVENTS | |
425 | select NO_DMA | |
426 | select NO_IOPORT | |
427 | select SPARSE_IRQ | |
428 | select USE_OF | |
429 | help | |
430 | Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko | |
431 | processors. | |
432 | ||
e7736d47 LB |
433 | config ARCH_EP93XX |
434 | bool "EP93xx-based" | |
b1b3f49c RK |
435 | select ARCH_HAS_HOLES_MEMORYMODEL |
436 | select ARCH_REQUIRE_GPIOLIB | |
437 | select ARCH_USES_GETTIMEOFFSET | |
e7736d47 LB |
438 | select ARM_AMBA |
439 | select ARM_VIC | |
6d803ba7 | 440 | select CLKDEV_LOOKUP |
b1b3f49c | 441 | select CPU_ARM920T |
5725aeae | 442 | select NEED_MACH_MEMORY_H |
e7736d47 LB |
443 | help |
444 | This enables support for the Cirrus EP93xx series of CPUs. | |
445 | ||
1da177e4 LT |
446 | config ARCH_FOOTBRIDGE |
447 | bool "FootBridge" | |
c750815e | 448 | select CPU_SA110 |
1da177e4 | 449 | select FOOTBRIDGE |
4e8d7637 | 450 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 451 | select HAVE_IDE |
8ef6e620 | 452 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 453 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
454 | help |
455 | Support for systems based on the DC21285 companion chip | |
456 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 457 | |
4af6fee1 DS |
458 | config ARCH_NETX |
459 | bool "Hilscher NetX based" | |
b1b3f49c | 460 | select ARM_VIC |
234b6ced | 461 | select CLKSRC_MMIO |
c750815e | 462 | select CPU_ARM926T |
2fcfe6b8 | 463 | select GENERIC_CLOCKEVENTS |
f999b8bd | 464 | help |
4af6fee1 DS |
465 | This enables support for systems based on the Hilscher NetX Soc |
466 | ||
3b938be6 RK |
467 | config ARCH_IOP13XX |
468 | bool "IOP13xx-based" | |
469 | depends on MMU | |
b1b3f49c | 470 | select CPU_XSC3 |
0cdc8b92 | 471 | select NEED_MACH_MEMORY_H |
13a5045d | 472 | select NEED_RET_TO_USER |
b1b3f49c RK |
473 | select PCI |
474 | select PLAT_IOP | |
475 | select VMSPLIT_1G | |
3b938be6 RK |
476 | help |
477 | Support for Intel's IOP13XX (XScale) family of processors. | |
478 | ||
3f7e5815 LB |
479 | config ARCH_IOP32X |
480 | bool "IOP32x-based" | |
a4f7e763 | 481 | depends on MMU |
b1b3f49c | 482 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 483 | select CPU_XSCALE |
e9004f50 | 484 | select GPIO_IOP |
13a5045d | 485 | select NEED_RET_TO_USER |
f7e68bbf | 486 | select PCI |
b1b3f49c | 487 | select PLAT_IOP |
f999b8bd | 488 | help |
3f7e5815 LB |
489 | Support for Intel's 80219 and IOP32X (XScale) family of |
490 | processors. | |
491 | ||
492 | config ARCH_IOP33X | |
493 | bool "IOP33x-based" | |
494 | depends on MMU | |
b1b3f49c | 495 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 496 | select CPU_XSCALE |
e9004f50 | 497 | select GPIO_IOP |
13a5045d | 498 | select NEED_RET_TO_USER |
3f7e5815 | 499 | select PCI |
b1b3f49c | 500 | select PLAT_IOP |
3f7e5815 LB |
501 | help |
502 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 503 | |
3b938be6 RK |
504 | config ARCH_IXP4XX |
505 | bool "IXP4xx-based" | |
a4f7e763 | 506 | depends on MMU |
58af4a24 | 507 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
d10d2d48 | 508 | select ARCH_SUPPORTS_BIG_ENDIAN |
b1b3f49c | 509 | select ARCH_REQUIRE_GPIOLIB |
234b6ced | 510 | select CLKSRC_MMIO |
c750815e | 511 | select CPU_XSCALE |
b1b3f49c | 512 | select DMABOUNCE if PCI |
3b938be6 | 513 | select GENERIC_CLOCKEVENTS |
0b05da72 | 514 | select MIGHT_HAVE_PCI |
c334bc15 | 515 | select NEED_MACH_IO_H |
9296d94d | 516 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 517 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 518 | help |
3b938be6 | 519 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 520 | |
edabd38e SB |
521 | config ARCH_DOVE |
522 | bool "Marvell Dove" | |
edabd38e | 523 | select ARCH_REQUIRE_GPIOLIB |
756b2531 | 524 | select CPU_PJ4 |
edabd38e | 525 | select GENERIC_CLOCKEVENTS |
0f81bd43 | 526 | select MIGHT_HAVE_PCI |
171b3f0d | 527 | select MVEBU_MBUS |
9139acd1 SH |
528 | select PINCTRL |
529 | select PINCTRL_DOVE | |
abcda1dc | 530 | select PLAT_ORION_LEGACY |
0f81bd43 | 531 | select USB_ARCH_HAS_EHCI |
edabd38e SB |
532 | help |
533 | Support for the Marvell Dove SoC 88AP510 | |
534 | ||
651c74c7 SB |
535 | config ARCH_KIRKWOOD |
536 | bool "Marvell Kirkwood" | |
0e2ee0c0 | 537 | select ARCH_HAS_CPUFREQ |
a8865655 | 538 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 539 | select CPU_FEROCEON |
651c74c7 | 540 | select GENERIC_CLOCKEVENTS |
171b3f0d | 541 | select MVEBU_MBUS |
b1b3f49c | 542 | select PCI |
1dc831bf | 543 | select PCI_QUIRKS |
f9e75922 AL |
544 | select PINCTRL |
545 | select PINCTRL_KIRKWOOD | |
abcda1dc | 546 | select PLAT_ORION_LEGACY |
651c74c7 SB |
547 | help |
548 | Support for the following Marvell Kirkwood series SoCs: | |
549 | 88F6180, 88F6192 and 88F6281. | |
550 | ||
794d15b2 SS |
551 | config ARCH_MV78XX0 |
552 | bool "Marvell MV78xx0" | |
a8865655 | 553 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 554 | select CPU_FEROCEON |
794d15b2 | 555 | select GENERIC_CLOCKEVENTS |
171b3f0d | 556 | select MVEBU_MBUS |
b1b3f49c | 557 | select PCI |
abcda1dc | 558 | select PLAT_ORION_LEGACY |
794d15b2 SS |
559 | help |
560 | Support for the following Marvell MV78xx0 series SoCs: | |
561 | MV781x0, MV782x0. | |
562 | ||
9dd0b194 | 563 | config ARCH_ORION5X |
585cf175 TP |
564 | bool "Marvell Orion" |
565 | depends on MMU | |
a8865655 | 566 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 567 | select CPU_FEROCEON |
51cbff1d | 568 | select GENERIC_CLOCKEVENTS |
171b3f0d | 569 | select MVEBU_MBUS |
b1b3f49c | 570 | select PCI |
abcda1dc | 571 | select PLAT_ORION_LEGACY |
585cf175 | 572 | help |
9dd0b194 | 573 | Support for the following Marvell Orion 5x series SoCs: |
d2b2a6bb | 574 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
d323ade1 | 575 | Orion-2 (5281), Orion-1-90 (6183). |
585cf175 | 576 | |
788c9700 | 577 | config ARCH_MMP |
2f7e8fae | 578 | bool "Marvell PXA168/910/MMP2" |
788c9700 | 579 | depends on MMU |
788c9700 | 580 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 581 | select CLKDEV_LOOKUP |
b1b3f49c | 582 | select GENERIC_ALLOCATOR |
788c9700 | 583 | select GENERIC_CLOCKEVENTS |
157d2644 | 584 | select GPIO_PXA |
c24b3114 | 585 | select IRQ_DOMAIN |
0f374561 | 586 | select MULTI_IRQ_HANDLER |
7c8f86a4 | 587 | select PINCTRL |
788c9700 | 588 | select PLAT_PXA |
0bd86961 | 589 | select SPARSE_IRQ |
788c9700 | 590 | help |
2f7e8fae | 591 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. |
788c9700 RK |
592 | |
593 | config ARCH_KS8695 | |
594 | bool "Micrel/Kendin KS8695" | |
98830bc9 | 595 | select ARCH_REQUIRE_GPIOLIB |
c7e783d6 | 596 | select CLKSRC_MMIO |
b1b3f49c | 597 | select CPU_ARM922T |
c7e783d6 | 598 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 599 | select NEED_MACH_MEMORY_H |
788c9700 RK |
600 | help |
601 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
602 | System-on-Chip devices. | |
603 | ||
788c9700 RK |
604 | config ARCH_W90X900 |
605 | bool "Nuvoton W90X900 CPU" | |
c52d3d68 | 606 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 607 | select CLKDEV_LOOKUP |
6fa5d5f7 | 608 | select CLKSRC_MMIO |
b1b3f49c | 609 | select CPU_ARM926T |
58b5369e | 610 | select GENERIC_CLOCKEVENTS |
788c9700 | 611 | help |
a8bc4ead | 612 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
613 | At present, the w90x900 has been renamed nuc900, regarding | |
614 | the ARM series product line, you can login the following | |
615 | link address to know more. | |
616 | ||
617 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
618 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 619 | |
93e22567 RK |
620 | config ARCH_LPC32XX |
621 | bool "NXP LPC32XX" | |
622 | select ARCH_REQUIRE_GPIOLIB | |
623 | select ARM_AMBA | |
624 | select CLKDEV_LOOKUP | |
625 | select CLKSRC_MMIO | |
626 | select CPU_ARM926T | |
627 | select GENERIC_CLOCKEVENTS | |
628 | select HAVE_IDE | |
629 | select HAVE_PWM | |
630 | select USB_ARCH_HAS_OHCI | |
631 | select USE_OF | |
632 | help | |
633 | Support for the NXP LPC32XX family of processors | |
634 | ||
1da177e4 | 635 | config ARCH_PXA |
2c8086a5 | 636 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 637 | depends on MMU |
89c52ed4 | 638 | select ARCH_HAS_CPUFREQ |
b1b3f49c RK |
639 | select ARCH_MTD_XIP |
640 | select ARCH_REQUIRE_GPIOLIB | |
641 | select ARM_CPU_SUSPEND if PM | |
642 | select AUTO_ZRELADDR | |
6d803ba7 | 643 | select CLKDEV_LOOKUP |
234b6ced | 644 | select CLKSRC_MMIO |
981d0f39 | 645 | select GENERIC_CLOCKEVENTS |
157d2644 | 646 | select GPIO_PXA |
d0ee9f40 | 647 | select HAVE_IDE |
b1b3f49c | 648 | select MULTI_IRQ_HANDLER |
b1b3f49c RK |
649 | select PLAT_PXA |
650 | select SPARSE_IRQ | |
f999b8bd | 651 | help |
2c8086a5 | 652 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 | 653 | |
788c9700 RK |
654 | config ARCH_MSM |
655 | bool "Qualcomm MSM" | |
923a081c | 656 | select ARCH_REQUIRE_GPIOLIB |
c602520f | 657 | select CLKSRC_OF if OF |
8cc7f533 | 658 | select COMMON_CLK |
b1b3f49c | 659 | select GENERIC_CLOCKEVENTS |
49cbe786 | 660 | help |
4b53eb4f DW |
661 | Support for Qualcomm MSM/QSD based systems. This runs on the |
662 | apps processor of the MSM/QSD and depends on a shared memory | |
663 | interface to the modem processor which runs the baseband | |
664 | stack and controls some vital subsystems | |
665 | (clock and power control, etc). | |
49cbe786 | 666 | |
bf98c1ea LP |
667 | config ARCH_SHMOBILE_LEGACY |
668 | bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)" | |
669 | select ARCH_SHMOBILE | |
69469995 | 670 | select ARM_PATCH_PHYS_VIRT |
5e93c6b4 | 671 | select CLKDEV_LOOKUP |
b1b3f49c | 672 | select GENERIC_CLOCKEVENTS |
4c3ffffd | 673 | select HAVE_ARM_SCU if SMP |
a894fcc2 | 674 | select HAVE_ARM_TWD if SMP |
aa3831cf | 675 | select HAVE_MACH_CLKDEV |
3b55658a | 676 | select HAVE_SMP |
ce5ea9f3 | 677 | select MIGHT_HAVE_CACHE_L2X0 |
60f1435c | 678 | select MULTI_IRQ_HANDLER |
b1b3f49c | 679 | select NO_IOPORT |
2cd3c927 | 680 | select PINCTRL |
b1b3f49c RK |
681 | select PM_GENERIC_DOMAINS if PM |
682 | select SPARSE_IRQ | |
c793c1b0 | 683 | help |
bf98c1ea LP |
684 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms using |
685 | a non-multiplatform kernel. | |
c793c1b0 | 686 | |
1da177e4 LT |
687 | config ARCH_RPC |
688 | bool "RiscPC" | |
689 | select ARCH_ACORN | |
a08b6b79 | 690 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 691 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 692 | select ARCH_USES_GETTIMEOFFSET |
b1b3f49c | 693 | select FIQ |
d0ee9f40 | 694 | select HAVE_IDE |
b1b3f49c RK |
695 | select HAVE_PATA_PLATFORM |
696 | select ISA_DMA_API | |
c334bc15 | 697 | select NEED_MACH_IO_H |
0cdc8b92 | 698 | select NEED_MACH_MEMORY_H |
b1b3f49c | 699 | select NO_IOPORT |
b4811bac | 700 | select VIRT_TO_BUS |
1da177e4 LT |
701 | help |
702 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
703 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
704 | ||
705 | config ARCH_SA1100 | |
706 | bool "SA1100-based" | |
89c52ed4 | 707 | select ARCH_HAS_CPUFREQ |
b1b3f49c RK |
708 | select ARCH_MTD_XIP |
709 | select ARCH_REQUIRE_GPIOLIB | |
710 | select ARCH_SPARSEMEM_ENABLE | |
711 | select CLKDEV_LOOKUP | |
712 | select CLKSRC_MMIO | |
1937f5b9 | 713 | select CPU_FREQ |
b1b3f49c | 714 | select CPU_SA1100 |
3e238be2 | 715 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 716 | select HAVE_IDE |
b1b3f49c | 717 | select ISA |
0cdc8b92 | 718 | select NEED_MACH_MEMORY_H |
375dec92 | 719 | select SPARSE_IRQ |
f999b8bd MM |
720 | help |
721 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 722 | |
b130d5c2 KK |
723 | config ARCH_S3C24XX |
724 | bool "Samsung S3C24XX SoCs" | |
9d56c02a | 725 | select ARCH_HAS_CPUFREQ |
53650430 | 726 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 727 | select CLKDEV_LOOKUP |
4280506a | 728 | select CLKSRC_SAMSUNG_PWM |
7f78b6eb | 729 | select GENERIC_CLOCKEVENTS |
880cf071 | 730 | select GPIO_SAMSUNG |
20676c15 | 731 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 732 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 733 | select HAVE_S3C_RTC if RTC_CLASS |
17453dd2 | 734 | select MULTI_IRQ_HANDLER |
01464226 | 735 | select NEED_MACH_GPIO_H |
c334bc15 | 736 | select NEED_MACH_IO_H |
cd8dc7ae | 737 | select SAMSUNG_ATAGS |
1da177e4 | 738 | help |
b130d5c2 KK |
739 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
740 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
741 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
742 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 743 | |
a08ab637 BD |
744 | config ARCH_S3C64XX |
745 | bool "Samsung S3C64XX" | |
b1b3f49c RK |
746 | select ARCH_HAS_CPUFREQ |
747 | select ARCH_REQUIRE_GPIOLIB | |
89f0ce72 | 748 | select ARM_VIC |
b1b3f49c | 749 | select CLKDEV_LOOKUP |
4280506a | 750 | select CLKSRC_SAMSUNG_PWM |
b69f460d | 751 | select COMMON_CLK |
b1b3f49c | 752 | select CPU_V6 |
04a49b71 | 753 | select GENERIC_CLOCKEVENTS |
880cf071 | 754 | select GPIO_SAMSUNG |
b1b3f49c RK |
755 | select HAVE_S3C2410_I2C if I2C |
756 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
6700397a | 757 | select HAVE_TCM |
b1b3f49c | 758 | select NEED_MACH_GPIO_H |
89f0ce72 | 759 | select NO_IOPORT |
b1b3f49c | 760 | select PLAT_SAMSUNG |
6e2d9e93 | 761 | select PM_GENERIC_DOMAINS |
b1b3f49c RK |
762 | select S3C_DEV_NAND |
763 | select S3C_GPIO_TRACK | |
cd8dc7ae | 764 | select SAMSUNG_ATAGS |
b1b3f49c | 765 | select SAMSUNG_GPIOLIB_4BIT |
6e2d9e93 | 766 | select SAMSUNG_WAKEMASK |
88f59738 | 767 | select SAMSUNG_WDT_RESET |
89f0ce72 | 768 | select USB_ARCH_HAS_OHCI |
a08ab637 BD |
769 | help |
770 | Samsung S3C64XX series based systems | |
771 | ||
49b7a491 KK |
772 | config ARCH_S5P64X0 |
773 | bool "Samsung S5P6440 S5P6450" | |
d8b22d25 | 774 | select CLKDEV_LOOKUP |
4280506a | 775 | select CLKSRC_SAMSUNG_PWM |
b1b3f49c | 776 | select CPU_V6 |
9e65bbf2 | 777 | select GENERIC_CLOCKEVENTS |
880cf071 | 778 | select GPIO_SAMSUNG |
20676c15 | 779 | select HAVE_S3C2410_I2C if I2C |
b1b3f49c | 780 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
754961a8 | 781 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 782 | select NEED_MACH_GPIO_H |
cd8dc7ae | 783 | select SAMSUNG_ATAGS |
171b3f0d | 784 | select SAMSUNG_WDT_RESET |
c4ffccdd | 785 | help |
49b7a491 KK |
786 | Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, |
787 | SMDK6450. | |
c4ffccdd | 788 | |
acc84707 MS |
789 | config ARCH_S5PC100 |
790 | bool "Samsung S5PC100" | |
53650430 | 791 | select ARCH_REQUIRE_GPIOLIB |
29e8eb0f | 792 | select CLKDEV_LOOKUP |
4280506a | 793 | select CLKSRC_SAMSUNG_PWM |
5a7652f2 | 794 | select CPU_V7 |
6a5a2e3b | 795 | select GENERIC_CLOCKEVENTS |
880cf071 | 796 | select GPIO_SAMSUNG |
20676c15 | 797 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 798 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 799 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 800 | select NEED_MACH_GPIO_H |
cd8dc7ae | 801 | select SAMSUNG_ATAGS |
171b3f0d | 802 | select SAMSUNG_WDT_RESET |
5a7652f2 | 803 | help |
acc84707 | 804 | Samsung S5PC100 series based systems |
5a7652f2 | 805 | |
170f4e42 KK |
806 | config ARCH_S5PV210 |
807 | bool "Samsung S5PV210/S5PC110" | |
b1b3f49c | 808 | select ARCH_HAS_CPUFREQ |
0f75a96b | 809 | select ARCH_HAS_HOLES_MEMORYMODEL |
b1b3f49c | 810 | select ARCH_SPARSEMEM_ENABLE |
b2a9dd46 | 811 | select CLKDEV_LOOKUP |
4280506a | 812 | select CLKSRC_SAMSUNG_PWM |
b1b3f49c | 813 | select CPU_V7 |
9e65bbf2 | 814 | select GENERIC_CLOCKEVENTS |
880cf071 | 815 | select GPIO_SAMSUNG |
20676c15 | 816 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 817 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 818 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 819 | select NEED_MACH_GPIO_H |
0cdc8b92 | 820 | select NEED_MACH_MEMORY_H |
cd8dc7ae | 821 | select SAMSUNG_ATAGS |
170f4e42 KK |
822 | help |
823 | Samsung S5PV210/S5PC110 series based systems | |
824 | ||
83014579 | 825 | config ARCH_EXYNOS |
93e22567 | 826 | bool "Samsung EXYNOS" |
b1b3f49c | 827 | select ARCH_HAS_CPUFREQ |
0f75a96b | 828 | select ARCH_HAS_HOLES_MEMORYMODEL |
e245f969 | 829 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 830 | select ARCH_SPARSEMEM_ENABLE |
e245f969 | 831 | select ARM_GIC |
340fcb5c | 832 | select COMMON_CLK |
b1b3f49c | 833 | select CPU_V7 |
cc0e72b8 | 834 | select GENERIC_CLOCKEVENTS |
20676c15 | 835 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 836 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 837 | select HAVE_S3C_RTC if RTC_CLASS |
0cdc8b92 | 838 | select NEED_MACH_MEMORY_H |
6e726ea4 | 839 | select SPARSE_IRQ |
f8b1ac01 | 840 | select USE_OF |
cc0e72b8 | 841 | help |
83014579 | 842 | Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) |
cc0e72b8 | 843 | |
7c6337e2 KH |
844 | config ARCH_DAVINCI |
845 | bool "TI DaVinci" | |
b1b3f49c | 846 | select ARCH_HAS_HOLES_MEMORYMODEL |
dce1115b | 847 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 848 | select CLKDEV_LOOKUP |
20e9969b | 849 | select GENERIC_ALLOCATOR |
b1b3f49c | 850 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 851 | select GENERIC_IRQ_CHIP |
b1b3f49c | 852 | select HAVE_IDE |
3ad7a42d | 853 | select TI_PRIV_EDMA |
689e331f | 854 | select USE_OF |
b1b3f49c | 855 | select ZONE_DMA |
7c6337e2 KH |
856 | help |
857 | Support for TI's DaVinci platform. | |
858 | ||
a0694861 TL |
859 | config ARCH_OMAP1 |
860 | bool "TI OMAP1" | |
00a36698 | 861 | depends on MMU |
89c52ed4 | 862 | select ARCH_HAS_CPUFREQ |
9af915da | 863 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 864 | select ARCH_OMAP |
21f47fbc | 865 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 866 | select CLKDEV_LOOKUP |
d6e15d78 | 867 | select CLKSRC_MMIO |
b1b3f49c | 868 | select GENERIC_CLOCKEVENTS |
a0694861 | 869 | select GENERIC_IRQ_CHIP |
a0694861 TL |
870 | select HAVE_IDE |
871 | select IRQ_DOMAIN | |
872 | select NEED_MACH_IO_H if PCCARD | |
873 | select NEED_MACH_MEMORY_H | |
21f47fbc | 874 | help |
a0694861 | 875 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 876 | |
1da177e4 LT |
877 | endchoice |
878 | ||
387798b3 RH |
879 | menu "Multiple platform selection" |
880 | depends on ARCH_MULTIPLATFORM | |
881 | ||
882 | comment "CPU Core family selection" | |
883 | ||
387798b3 RH |
884 | config ARCH_MULTI_V4T |
885 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 886 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 887 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
888 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
889 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
890 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
891 | |
892 | config ARCH_MULTI_V5 | |
893 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 894 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 895 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
896 | select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ |
897 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ | |
898 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
899 | |
900 | config ARCH_MULTI_V4_V5 | |
901 | bool | |
902 | ||
903 | config ARCH_MULTI_V6 | |
8dda05cc | 904 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 905 | select ARCH_MULTI_V6_V7 |
b1b3f49c | 906 | select CPU_V6 |
387798b3 RH |
907 | |
908 | config ARCH_MULTI_V7 | |
8dda05cc | 909 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
910 | default y |
911 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 912 | select CPU_V7 |
387798b3 RH |
913 | |
914 | config ARCH_MULTI_V6_V7 | |
915 | bool | |
916 | ||
917 | config ARCH_MULTI_CPU_AUTO | |
918 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
919 | select ARCH_MULTI_V5 | |
920 | ||
921 | endmenu | |
922 | ||
ccf50e23 RK |
923 | # |
924 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
925 | # Kconfigs may be included either alphabetically (according to the | |
926 | # plat- suffix) or along side the corresponding mach-* source. | |
927 | # | |
3e93a22b GC |
928 | source "arch/arm/mach-mvebu/Kconfig" |
929 | ||
95b8f20f RK |
930 | source "arch/arm/mach-at91/Kconfig" |
931 | ||
8ac49e04 CD |
932 | source "arch/arm/mach-bcm/Kconfig" |
933 | ||
f1ac922d SW |
934 | source "arch/arm/mach-bcm2835/Kconfig" |
935 | ||
1c37fa10 SH |
936 | source "arch/arm/mach-berlin/Kconfig" |
937 | ||
1da177e4 LT |
938 | source "arch/arm/mach-clps711x/Kconfig" |
939 | ||
d94f944e AV |
940 | source "arch/arm/mach-cns3xxx/Kconfig" |
941 | ||
95b8f20f RK |
942 | source "arch/arm/mach-davinci/Kconfig" |
943 | ||
944 | source "arch/arm/mach-dove/Kconfig" | |
945 | ||
e7736d47 LB |
946 | source "arch/arm/mach-ep93xx/Kconfig" |
947 | ||
1da177e4 LT |
948 | source "arch/arm/mach-footbridge/Kconfig" |
949 | ||
59d3a193 PZ |
950 | source "arch/arm/mach-gemini/Kconfig" |
951 | ||
387798b3 RH |
952 | source "arch/arm/mach-highbank/Kconfig" |
953 | ||
1da177e4 LT |
954 | source "arch/arm/mach-integrator/Kconfig" |
955 | ||
3f7e5815 LB |
956 | source "arch/arm/mach-iop32x/Kconfig" |
957 | ||
958 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 959 | |
285f5fa7 DW |
960 | source "arch/arm/mach-iop13xx/Kconfig" |
961 | ||
1da177e4 LT |
962 | source "arch/arm/mach-ixp4xx/Kconfig" |
963 | ||
828989ad SS |
964 | source "arch/arm/mach-keystone/Kconfig" |
965 | ||
95b8f20f RK |
966 | source "arch/arm/mach-kirkwood/Kconfig" |
967 | ||
968 | source "arch/arm/mach-ks8695/Kconfig" | |
969 | ||
95b8f20f RK |
970 | source "arch/arm/mach-msm/Kconfig" |
971 | ||
794d15b2 SS |
972 | source "arch/arm/mach-mv78xx0/Kconfig" |
973 | ||
3995eb82 | 974 | source "arch/arm/mach-imx/Kconfig" |
1da177e4 | 975 | |
1d3f33d5 SG |
976 | source "arch/arm/mach-mxs/Kconfig" |
977 | ||
95b8f20f | 978 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 979 | |
95b8f20f | 980 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 981 | |
9851ca57 DT |
982 | source "arch/arm/mach-nspire/Kconfig" |
983 | ||
d48af15e TL |
984 | source "arch/arm/plat-omap/Kconfig" |
985 | ||
986 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 987 | |
1dbae815 TL |
988 | source "arch/arm/mach-omap2/Kconfig" |
989 | ||
9dd0b194 | 990 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 991 | |
387798b3 RH |
992 | source "arch/arm/mach-picoxcell/Kconfig" |
993 | ||
95b8f20f RK |
994 | source "arch/arm/mach-pxa/Kconfig" |
995 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 996 | |
95b8f20f RK |
997 | source "arch/arm/mach-mmp/Kconfig" |
998 | ||
999 | source "arch/arm/mach-realview/Kconfig" | |
1000 | ||
d63dc051 HS |
1001 | source "arch/arm/mach-rockchip/Kconfig" |
1002 | ||
95b8f20f | 1003 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 1004 | |
cf383678 | 1005 | source "arch/arm/plat-samsung/Kconfig" |
a21765a7 | 1006 | |
387798b3 RH |
1007 | source "arch/arm/mach-socfpga/Kconfig" |
1008 | ||
a7ed099f | 1009 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 1010 | |
65ebcc11 SK |
1011 | source "arch/arm/mach-sti/Kconfig" |
1012 | ||
85fd6d63 | 1013 | source "arch/arm/mach-s3c24xx/Kconfig" |
1da177e4 | 1014 | |
431107ea | 1015 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 | 1016 | |
49b7a491 | 1017 | source "arch/arm/mach-s5p64x0/Kconfig" |
c4ffccdd | 1018 | |
5a7652f2 | 1019 | source "arch/arm/mach-s5pc100/Kconfig" |
5a7652f2 | 1020 | |
170f4e42 KK |
1021 | source "arch/arm/mach-s5pv210/Kconfig" |
1022 | ||
83014579 | 1023 | source "arch/arm/mach-exynos/Kconfig" |
cc0e72b8 | 1024 | |
882d01f9 | 1025 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 1026 | |
3b52634f MR |
1027 | source "arch/arm/mach-sunxi/Kconfig" |
1028 | ||
156a0997 BS |
1029 | source "arch/arm/mach-prima2/Kconfig" |
1030 | ||
c5f80065 EG |
1031 | source "arch/arm/mach-tegra/Kconfig" |
1032 | ||
95b8f20f | 1033 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 1034 | |
95b8f20f | 1035 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
1036 | |
1037 | source "arch/arm/mach-versatile/Kconfig" | |
1038 | ||
ceade897 | 1039 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 1040 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 1041 | |
2a0ba738 MZ |
1042 | source "arch/arm/mach-virt/Kconfig" |
1043 | ||
6f35f9a9 TP |
1044 | source "arch/arm/mach-vt8500/Kconfig" |
1045 | ||
7ec80ddf | 1046 | source "arch/arm/mach-w90x900/Kconfig" |
1047 | ||
9a45eb69 JC |
1048 | source "arch/arm/mach-zynq/Kconfig" |
1049 | ||
1da177e4 LT |
1050 | # Definitions to make life easier |
1051 | config ARCH_ACORN | |
1052 | bool | |
1053 | ||
7ae1f7ec LB |
1054 | config PLAT_IOP |
1055 | bool | |
469d3044 | 1056 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 1057 | |
69b02f6a LB |
1058 | config PLAT_ORION |
1059 | bool | |
bfe45e0b | 1060 | select CLKSRC_MMIO |
b1b3f49c | 1061 | select COMMON_CLK |
dc7ad3b3 | 1062 | select GENERIC_IRQ_CHIP |
278b45b0 | 1063 | select IRQ_DOMAIN |
69b02f6a | 1064 | |
abcda1dc TP |
1065 | config PLAT_ORION_LEGACY |
1066 | bool | |
1067 | select PLAT_ORION | |
1068 | ||
bd5ce433 EM |
1069 | config PLAT_PXA |
1070 | bool | |
1071 | ||
f4b8b319 RK |
1072 | config PLAT_VERSATILE |
1073 | bool | |
1074 | ||
e3887714 RK |
1075 | config ARM_TIMER_SP804 |
1076 | bool | |
bfe45e0b | 1077 | select CLKSRC_MMIO |
7a0eca71 | 1078 | select CLKSRC_OF if OF |
e3887714 | 1079 | |
1da177e4 LT |
1080 | source arch/arm/mm/Kconfig |
1081 | ||
958cab0f RK |
1082 | config ARM_NR_BANKS |
1083 | int | |
1084 | default 16 if ARCH_EP93XX | |
1085 | default 8 | |
1086 | ||
afe4b25e | 1087 | config IWMMXT |
698613b6 | 1088 | bool "Enable iWMMXt support" if !CPU_PJ4 |
ef6c8445 | 1089 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 |
698613b6 | 1090 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 |
afe4b25e LB |
1091 | help |
1092 | Enable support for iWMMXt context switching at run time if | |
1093 | running on a CPU that supports it. | |
1094 | ||
52108641 | 1095 | config MULTI_IRQ_HANDLER |
1096 | bool | |
1097 | help | |
1098 | Allow each machine to specify it's own IRQ handler at run time. | |
1099 | ||
3b93e7b0 HC |
1100 | if !MMU |
1101 | source "arch/arm/Kconfig-nommu" | |
1102 | endif | |
1103 | ||
3e0a07f8 GC |
1104 | config PJ4B_ERRATA_4742 |
1105 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
1106 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
1107 | default y | |
1108 | help | |
1109 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
1110 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
1111 | the retiring WFI/WFE instructions and the newly issued subsequent | |
1112 | instructions. This sensitivity can result in a CPU hang scenario. | |
1113 | Workaround: | |
1114 | The software must insert either a Data Synchronization Barrier (DSB) | |
1115 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
1116 | instruction | |
1117 | ||
f0c4b8d6 WD |
1118 | config ARM_ERRATA_326103 |
1119 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
1120 | depends on CPU_V6 | |
1121 | help | |
1122 | Executing a SWP instruction to read-only memory does not set bit 11 | |
1123 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
1124 | treat the access as a read, preventing a COW from occurring and | |
1125 | causing the faulting task to livelock. | |
1126 | ||
9cba3ccc CM |
1127 | config ARM_ERRATA_411920 |
1128 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 1129 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
1130 | help |
1131 | Invalidation of the Instruction Cache operation can | |
1132 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1133 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1134 | recommended workaround. | |
1135 | ||
7ce236fc CM |
1136 | config ARM_ERRATA_430973 |
1137 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1138 | depends on CPU_V7 | |
1139 | help | |
1140 | This option enables the workaround for the 430973 Cortex-A8 | |
1141 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1142 | interworking branch is replaced with another code sequence at the | |
1143 | same virtual address, whether due to self-modifying code or virtual | |
1144 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1145 | stale interworking branch prediction. This results in Cortex-A8 | |
1146 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1147 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1148 | and also flushes the branch target cache at every context switch. | |
1149 | Note that setting specific bits in the ACTLR register may not be | |
1150 | available in non-secure mode. | |
1151 | ||
855c551f CM |
1152 | config ARM_ERRATA_458693 |
1153 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1154 | depends on CPU_V7 | |
62e4d357 | 1155 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
1156 | help |
1157 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1158 | erratum. For very specific sequences of memory operations, it is | |
1159 | possible for a hazard condition intended for a cache line to instead | |
1160 | be incorrectly associated with a different cache line. This false | |
1161 | hazard might then cause a processor deadlock. The workaround enables | |
1162 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1163 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1164 | register may not be available in non-secure mode. | |
1165 | ||
0516e464 CM |
1166 | config ARM_ERRATA_460075 |
1167 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1168 | depends on CPU_V7 | |
62e4d357 | 1169 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
1170 | help |
1171 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1172 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1173 | situation in which recent store transactions to the L2 cache are lost | |
1174 | and overwritten with stale memory contents from external memory. The | |
1175 | workaround disables the write-allocate mode for the L2 cache via the | |
1176 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1177 | may not be available in non-secure mode. | |
1178 | ||
9f05027c WD |
1179 | config ARM_ERRATA_742230 |
1180 | bool "ARM errata: DMB operation may be faulty" | |
1181 | depends on CPU_V7 && SMP | |
62e4d357 | 1182 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1183 | help |
1184 | This option enables the workaround for the 742230 Cortex-A9 | |
1185 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1186 | between two write operations may not ensure the correct visibility | |
1187 | ordering of the two writes. This workaround sets a specific bit in | |
1188 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1189 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1190 | the two writes. | |
1191 | ||
a672e99b WD |
1192 | config ARM_ERRATA_742231 |
1193 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1194 | depends on CPU_V7 && SMP | |
62e4d357 | 1195 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1196 | help |
1197 | This option enables the workaround for the 742231 Cortex-A9 | |
1198 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1199 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1200 | accessing some data located in the same cache line, may get corrupted | |
1201 | data due to bad handling of the address hazard when the line gets | |
1202 | replaced from one of the CPUs at the same time as another CPU is | |
1203 | accessing it. This workaround sets specific bits in the diagnostic | |
1204 | register of the Cortex-A9 which reduces the linefill issuing | |
1205 | capabilities of the processor. | |
1206 | ||
9e65582a | 1207 | config PL310_ERRATA_588369 |
fa0ce403 | 1208 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" |
2839e06c | 1209 | depends on CACHE_L2X0 |
9e65582a SS |
1210 | help |
1211 | The PL310 L2 cache controller implements three types of Clean & | |
1212 | Invalidate maintenance operations: by Physical Address | |
1213 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
1214 | They are architecturally defined to behave as the execution of a | |
1215 | clean operation followed immediately by an invalidate operation, | |
1216 | both performing to the same memory location. This functionality | |
1217 | is not correctly implemented in PL310 as clean lines are not | |
2839e06c | 1218 | invalidated as a result of these operations. |
cdf357f1 | 1219 | |
69155794 JM |
1220 | config ARM_ERRATA_643719 |
1221 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1222 | depends on CPU_V7 && SMP | |
1223 | help | |
1224 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1225 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1226 | register returns zero when it should return one. The workaround | |
1227 | corrects this value, ensuring cache maintenance operations which use | |
1228 | it behave as intended and avoiding data corruption. | |
1229 | ||
cdf357f1 WD |
1230 | config ARM_ERRATA_720789 |
1231 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1232 | depends on CPU_V7 |
cdf357f1 WD |
1233 | help |
1234 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1235 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1236 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1237 | As a consequence of this erratum, some TLB entries which should be | |
1238 | invalidated are not, resulting in an incoherency in the system page | |
1239 | tables. The workaround changes the TLB flushing routines to invalidate | |
1240 | entries regardless of the ASID. | |
475d92fc | 1241 | |
1f0090a1 | 1242 | config PL310_ERRATA_727915 |
fa0ce403 | 1243 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" |
1f0090a1 RK |
1244 | depends on CACHE_L2X0 |
1245 | help | |
1246 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
1247 | operation (offset 0x7FC). This operation runs in background so that | |
1248 | PL310 can handle normal accesses while it is in progress. Under very | |
1249 | rare circumstances, due to this erratum, write data can be lost when | |
1250 | PL310 treats a cacheable write transaction during a Clean & | |
1251 | Invalidate by Way operation. | |
1252 | ||
475d92fc WD |
1253 | config ARM_ERRATA_743622 |
1254 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1255 | depends on CPU_V7 | |
62e4d357 | 1256 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1257 | help |
1258 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1259 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1260 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1261 | corruption. This workaround sets a specific bit in the diagnostic | |
1262 | register of the Cortex-A9 which disables the Store Buffer | |
1263 | optimisation, preventing the defect from occurring. This has no | |
1264 | visible impact on the overall performance or power consumption of the | |
1265 | processor. | |
1266 | ||
9a27c27c WD |
1267 | config ARM_ERRATA_751472 |
1268 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1269 | depends on CPU_V7 |
62e4d357 | 1270 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1271 | help |
1272 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1273 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1274 | completion of a following broadcasted operation if the second | |
1275 | operation is received by a CPU before the ICIALLUIS has completed, | |
1276 | potentially leading to corrupted entries in the cache or TLB. | |
1277 | ||
fa0ce403 WD |
1278 | config PL310_ERRATA_753970 |
1279 | bool "PL310 errata: cache sync operation may be faulty" | |
885028e4 SK |
1280 | depends on CACHE_PL310 |
1281 | help | |
1282 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
1283 | ||
1284 | Under some condition the effect of cache sync operation on | |
1285 | the store buffer still remains when the operation completes. | |
1286 | This means that the store buffer is always asked to drain and | |
1287 | this prevents it from merging any further writes. The workaround | |
1288 | is to replace the normal offset of cache sync operation (0x730) | |
1289 | by another offset targeting an unmapped PL310 register 0x740. | |
1290 | This has the same effect as the cache sync operation: store buffer | |
1291 | drain and waiting for all buffers empty. | |
1292 | ||
fcbdc5fe WD |
1293 | config ARM_ERRATA_754322 |
1294 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1295 | depends on CPU_V7 | |
1296 | help | |
1297 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1298 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1299 | which starts prior to an ASID switch but completes afterwards. This | |
1300 | can populate the micro-TLB with a stale entry which may be hit with | |
1301 | the new ASID. This workaround places two dsb instructions in the mm | |
1302 | switching code so that no page table walks can cross the ASID switch. | |
1303 | ||
5dab26af WD |
1304 | config ARM_ERRATA_754327 |
1305 | bool "ARM errata: no automatic Store Buffer drain" | |
1306 | depends on CPU_V7 && SMP | |
1307 | help | |
1308 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1309 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1310 | mechanism and therefore a livelock may occur if an external agent | |
1311 | continuously polls a memory location waiting to observe an update. | |
1312 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1313 | written polling loops from denying visibility of updates to memory. | |
1314 | ||
145e10e1 CM |
1315 | config ARM_ERRATA_364296 |
1316 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 1317 | depends on CPU_V6 |
145e10e1 CM |
1318 | help |
1319 | This options enables the workaround for the 364296 ARM1136 | |
1320 | r0p2 erratum (possible cache data corruption with | |
1321 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1322 | the auxiliary control register and the FI bit in the control | |
1323 | register, thus disabling hit-under-miss without putting the | |
1324 | processor into full low interrupt latency mode. ARM11MPCore | |
1325 | is not affected. | |
1326 | ||
f630c1bd WD |
1327 | config ARM_ERRATA_764369 |
1328 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1329 | depends on CPU_V7 && SMP | |
1330 | help | |
1331 | This option enables the workaround for erratum 764369 | |
1332 | affecting Cortex-A9 MPCore with two or more processors (all | |
1333 | current revisions). Under certain timing circumstances, a data | |
1334 | cache line maintenance operation by MVA targeting an Inner | |
1335 | Shareable memory region may fail to proceed up to either the | |
1336 | Point of Coherency or to the Point of Unification of the | |
1337 | system. This workaround adds a DSB instruction before the | |
1338 | relevant cache maintenance functions and sets a specific bit | |
1339 | in the diagnostic control register of the SCU. | |
1340 | ||
11ed0ba1 WD |
1341 | config PL310_ERRATA_769419 |
1342 | bool "PL310 errata: no automatic Store Buffer drain" | |
1343 | depends on CACHE_L2X0 | |
1344 | help | |
1345 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
1346 | not automatically drain. This can cause normal, non-cacheable | |
1347 | writes to be retained when the memory system is idle, leading | |
1348 | to suboptimal I/O performance for drivers using coherent DMA. | |
1349 | This option adds a write barrier to the cpu_idle loop so that, | |
1350 | on systems with an outer cache, the store buffer is drained | |
1351 | explicitly. | |
1352 | ||
7253b85c SH |
1353 | config ARM_ERRATA_775420 |
1354 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1355 | depends on CPU_V7 | |
1356 | help | |
1357 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1358 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1359 | operation aborts with MMU exception, it might cause the processor | |
1360 | to deadlock. This workaround puts DSB before executing ISB if | |
1361 | an abort may occur on cache maintenance. | |
1362 | ||
93dc6887 CM |
1363 | config ARM_ERRATA_798181 |
1364 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1365 | depends on CPU_V7 && SMP | |
1366 | help | |
1367 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1368 | adequately shooting down all use of the old entries. This | |
1369 | option enables the Linux kernel workaround for this erratum | |
1370 | which sends an IPI to the CPUs that are running the same ASID | |
1371 | as the one being invalidated. | |
1372 | ||
84b6504f WD |
1373 | config ARM_ERRATA_773022 |
1374 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1375 | depends on CPU_V7 | |
1376 | help | |
1377 | This option enables the workaround for the 773022 Cortex-A15 | |
1378 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1379 | loop buffer may deliver incorrect instructions. This | |
1380 | workaround disables the loop buffer to avoid the erratum. | |
1381 | ||
1da177e4 LT |
1382 | endmenu |
1383 | ||
1384 | source "arch/arm/common/Kconfig" | |
1385 | ||
1da177e4 LT |
1386 | menu "Bus support" |
1387 | ||
1388 | config ARM_AMBA | |
1389 | bool | |
1390 | ||
1391 | config ISA | |
1392 | bool | |
1da177e4 LT |
1393 | help |
1394 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1395 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1396 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1397 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1398 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1399 | ||
065909b9 | 1400 | # Select ISA DMA controller support |
1da177e4 LT |
1401 | config ISA_DMA |
1402 | bool | |
065909b9 | 1403 | select ISA_DMA_API |
1da177e4 | 1404 | |
065909b9 | 1405 | # Select ISA DMA interface |
5cae841b AV |
1406 | config ISA_DMA_API |
1407 | bool | |
5cae841b | 1408 | |
1da177e4 | 1409 | config PCI |
0b05da72 | 1410 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1411 | help |
1412 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1413 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1414 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1415 | VESA. If you have PCI, say Y, otherwise N. | |
1416 | ||
52882173 AV |
1417 | config PCI_DOMAINS |
1418 | bool | |
1419 | depends on PCI | |
1420 | ||
b080ac8a MRJ |
1421 | config PCI_NANOENGINE |
1422 | bool "BSE nanoEngine PCI support" | |
1423 | depends on SA1100_NANOENGINE | |
1424 | help | |
1425 | Enable PCI on the BSE nanoEngine board. | |
1426 | ||
36e23590 MW |
1427 | config PCI_SYSCALL |
1428 | def_bool PCI | |
1429 | ||
a0113a99 MR |
1430 | config PCI_HOST_ITE8152 |
1431 | bool | |
1432 | depends on PCI && MACH_ARMCORE | |
1433 | default y | |
1434 | select DMABOUNCE | |
1435 | ||
1da177e4 | 1436 | source "drivers/pci/Kconfig" |
3f06d157 | 1437 | source "drivers/pci/pcie/Kconfig" |
1da177e4 LT |
1438 | |
1439 | source "drivers/pcmcia/Kconfig" | |
1440 | ||
1441 | endmenu | |
1442 | ||
1443 | menu "Kernel Features" | |
1444 | ||
3b55658a DM |
1445 | config HAVE_SMP |
1446 | bool | |
1447 | help | |
1448 | This option should be selected by machines which have an SMP- | |
1449 | capable CPU. | |
1450 | ||
1451 | The only effect of this option is to make the SMP-related | |
1452 | options available to the user for configuration. | |
1453 | ||
1da177e4 | 1454 | config SMP |
bb2d8130 | 1455 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1456 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1457 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1458 | depends on HAVE_SMP |
801bb21c | 1459 | depends on MMU || ARM_MPU |
1da177e4 LT |
1460 | help |
1461 | This enables support for systems with more than one CPU. If you have | |
1462 | a system with only one CPU, like most personal computers, say N. If | |
1463 | you have a system with more than one CPU, say Y. | |
1464 | ||
1465 | If you say N here, the kernel will run on single and multiprocessor | |
1466 | machines, but will use only one CPU of a multiprocessor machine. If | |
1467 | you say Y here, the kernel will run on many, but not all, single | |
1468 | processor machines. On a single processor machine, the kernel will | |
1469 | run faster if you say N here. | |
1470 | ||
395cf969 | 1471 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1472 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1473 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1474 | |
1475 | If you don't know what to do here, say N. | |
1476 | ||
f00ec48f RK |
1477 | config SMP_ON_UP |
1478 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
801bb21c | 1479 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1480 | default y |
1481 | help | |
1482 | SMP kernels contain instructions which fail on non-SMP processors. | |
1483 | Enabling this option allows the kernel to modify itself to make | |
1484 | these instructions safe. Disabling it allows about 1K of space | |
1485 | savings. | |
1486 | ||
1487 | If you don't know what to do here, say Y. | |
1488 | ||
c9018aab VG |
1489 | config ARM_CPU_TOPOLOGY |
1490 | bool "Support cpu topology definition" | |
1491 | depends on SMP && CPU_V7 | |
1492 | default y | |
1493 | help | |
1494 | Support ARM cpu topology definition. The MPIDR register defines | |
1495 | affinity between processors which is then used to describe the cpu | |
1496 | topology of an ARM System. | |
1497 | ||
1498 | config SCHED_MC | |
1499 | bool "Multi-core scheduler support" | |
1500 | depends on ARM_CPU_TOPOLOGY | |
1501 | help | |
1502 | Multi-core scheduler support improves the CPU scheduler's decision | |
1503 | making when dealing with multi-core CPU chips at a cost of slightly | |
1504 | increased overhead in some places. If unsure say N here. | |
1505 | ||
1506 | config SCHED_SMT | |
1507 | bool "SMT scheduler support" | |
1508 | depends on ARM_CPU_TOPOLOGY | |
1509 | help | |
1510 | Improves the CPU scheduler's decision making when dealing with | |
1511 | MultiThreading at a cost of slightly increased overhead in some | |
1512 | places. If unsure say N here. | |
1513 | ||
a8cbcd92 RK |
1514 | config HAVE_ARM_SCU |
1515 | bool | |
a8cbcd92 RK |
1516 | help |
1517 | This option enables support for the ARM system coherency unit | |
1518 | ||
8a4da6e3 | 1519 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1520 | bool "Architected timer support" |
1521 | depends on CPU_V7 | |
8a4da6e3 | 1522 | select ARM_ARCH_TIMER |
0c403462 | 1523 | select GENERIC_CLOCKEVENTS |
022c03a2 MZ |
1524 | help |
1525 | This option enables support for the ARM architected timer | |
1526 | ||
f32f4ce2 RK |
1527 | config HAVE_ARM_TWD |
1528 | bool | |
1529 | depends on SMP | |
da4a686a | 1530 | select CLKSRC_OF if OF |
f32f4ce2 RK |
1531 | help |
1532 | This options enables support for the ARM timer and watchdog unit | |
1533 | ||
e8db288e NP |
1534 | config MCPM |
1535 | bool "Multi-Cluster Power Management" | |
1536 | depends on CPU_V7 && SMP | |
1537 | help | |
1538 | This option provides the common power management infrastructure | |
1539 | for (multi-)cluster based systems, such as big.LITTLE based | |
1540 | systems. | |
1541 | ||
1c33be57 NP |
1542 | config BIG_LITTLE |
1543 | bool "big.LITTLE support (Experimental)" | |
1544 | depends on CPU_V7 && SMP | |
1545 | select MCPM | |
1546 | help | |
1547 | This option enables support selections for the big.LITTLE | |
1548 | system architecture. | |
1549 | ||
1550 | config BL_SWITCHER | |
1551 | bool "big.LITTLE switcher support" | |
1552 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU | |
1553 | select CPU_PM | |
1554 | select ARM_CPU_SUSPEND | |
1555 | help | |
1556 | The big.LITTLE "switcher" provides the core functionality to | |
1557 | transparently handle transition between a cluster of A15's | |
1558 | and a cluster of A7's in a big.LITTLE system. | |
1559 | ||
b22537c6 NP |
1560 | config BL_SWITCHER_DUMMY_IF |
1561 | tristate "Simple big.LITTLE switcher user interface" | |
1562 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1563 | help | |
1564 | This is a simple and dummy char dev interface to control | |
1565 | the big.LITTLE switcher core code. It is meant for | |
1566 | debugging purposes only. | |
1567 | ||
8d5796d2 LB |
1568 | choice |
1569 | prompt "Memory split" | |
1570 | default VMSPLIT_3G | |
1571 | help | |
1572 | Select the desired split between kernel and user memory. | |
1573 | ||
1574 | If you are not absolutely sure what you are doing, leave this | |
1575 | option alone! | |
1576 | ||
1577 | config VMSPLIT_3G | |
1578 | bool "3G/1G user/kernel split" | |
1579 | config VMSPLIT_2G | |
1580 | bool "2G/2G user/kernel split" | |
1581 | config VMSPLIT_1G | |
1582 | bool "1G/3G user/kernel split" | |
1583 | endchoice | |
1584 | ||
1585 | config PAGE_OFFSET | |
1586 | hex | |
1587 | default 0x40000000 if VMSPLIT_1G | |
1588 | default 0x80000000 if VMSPLIT_2G | |
1589 | default 0xC0000000 | |
1590 | ||
1da177e4 LT |
1591 | config NR_CPUS |
1592 | int "Maximum number of CPUs (2-32)" | |
1593 | range 2 32 | |
1594 | depends on SMP | |
1595 | default "4" | |
1596 | ||
a054a811 | 1597 | config HOTPLUG_CPU |
00b7dede | 1598 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1599 | depends on SMP |
a054a811 RK |
1600 | help |
1601 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1602 | can be controlled through /sys/devices/system/cpu. | |
1603 | ||
2bdd424f WD |
1604 | config ARM_PSCI |
1605 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
1606 | depends on CPU_V7 | |
1607 | help | |
1608 | Say Y here if you want Linux to communicate with system firmware | |
1609 | implementing the PSCI specification for CPU-centric power | |
1610 | management operations described in ARM document number ARM DEN | |
1611 | 0022A ("Power State Coordination Interface System Software on | |
1612 | ARM processors"). | |
1613 | ||
2a6ad871 MR |
1614 | # The GPIO number here must be sorted by descending number. In case of |
1615 | # a multiplatform kernel, we just want the highest value required by the | |
1616 | # selected platforms. | |
44986ab0 PDSN |
1617 | config ARCH_NR_GPIO |
1618 | int | |
3dea19e8 | 1619 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
6d0fc190 | 1620 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX |
06b851e5 | 1621 | default 392 if ARCH_U8500 |
01bb914c TP |
1622 | default 352 if ARCH_VT8500 |
1623 | default 288 if ARCH_SUNXI | |
2a6ad871 | 1624 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1625 | default 0 |
1626 | help | |
1627 | Maximum number of GPIOs in the system. | |
1628 | ||
1629 | If unsure, leave the default value. | |
1630 | ||
d45a398f | 1631 | source kernel/Kconfig.preempt |
1da177e4 | 1632 | |
c9218b16 | 1633 | config HZ_FIXED |
f8065813 | 1634 | int |
b130d5c2 | 1635 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ |
a73ddc61 | 1636 | ARCH_S5PV210 || ARCH_EXYNOS4 |
5248c657 | 1637 | default AT91_TIMER_HZ if ARCH_AT91 |
bf98c1ea | 1638 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY |
47d84682 | 1639 | default 0 |
c9218b16 RK |
1640 | |
1641 | choice | |
47d84682 | 1642 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1643 | prompt "Timer frequency" |
1644 | ||
1645 | config HZ_100 | |
1646 | bool "100 Hz" | |
1647 | ||
1648 | config HZ_200 | |
1649 | bool "200 Hz" | |
1650 | ||
1651 | config HZ_250 | |
1652 | bool "250 Hz" | |
1653 | ||
1654 | config HZ_300 | |
1655 | bool "300 Hz" | |
1656 | ||
1657 | config HZ_500 | |
1658 | bool "500 Hz" | |
1659 | ||
1660 | config HZ_1000 | |
1661 | bool "1000 Hz" | |
1662 | ||
1663 | endchoice | |
1664 | ||
1665 | config HZ | |
1666 | int | |
47d84682 | 1667 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1668 | default 100 if HZ_100 |
1669 | default 200 if HZ_200 | |
1670 | default 250 if HZ_250 | |
1671 | default 300 if HZ_300 | |
1672 | default 500 if HZ_500 | |
1673 | default 1000 | |
1674 | ||
1675 | config SCHED_HRTICK | |
1676 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1677 | |
b28748fb RK |
1678 | config SCHED_HRTICK |
1679 | def_bool HIGH_RES_TIMERS | |
1680 | ||
16c79651 | 1681 | config THUMB2_KERNEL |
bc7dea00 | 1682 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1683 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1684 | default y if CPU_THUMBONLY |
16c79651 CM |
1685 | select AEABI |
1686 | select ARM_ASM_UNIFIED | |
89bace65 | 1687 | select ARM_UNWIND |
16c79651 CM |
1688 | help |
1689 | By enabling this option, the kernel will be compiled in | |
1690 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1691 | ARM-Thumb syntax is needed. | |
1692 | ||
1693 | If unsure, say N. | |
1694 | ||
6f685c5c DM |
1695 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1696 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1697 | depends on THUMB2_KERNEL && MODULES | |
1698 | default y | |
1699 | help | |
1700 | Various binutils versions can resolve Thumb-2 branches to | |
1701 | locally-defined, preemptible global symbols as short-range "b.n" | |
1702 | branch instructions. | |
1703 | ||
1704 | This is a problem, because there's no guarantee the final | |
1705 | destination of the symbol, or any candidate locations for a | |
1706 | trampoline, are within range of the branch. For this reason, the | |
1707 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1708 | relocation in modules at all, and it makes little sense to add | |
1709 | support. | |
1710 | ||
1711 | The symptom is that the kernel fails with an "unsupported | |
1712 | relocation" error when loading some modules. | |
1713 | ||
1714 | Until fixed tools are available, passing | |
1715 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1716 | code which hits this problem, at the cost of a bit of extra runtime | |
1717 | stack usage in some cases. | |
1718 | ||
1719 | The problem is described in more detail at: | |
1720 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1721 | ||
1722 | Only Thumb-2 kernels are affected. | |
1723 | ||
1724 | Unless you are sure your tools don't have this problem, say Y. | |
1725 | ||
0becb088 CM |
1726 | config ARM_ASM_UNIFIED |
1727 | bool | |
1728 | ||
704bdda0 NP |
1729 | config AEABI |
1730 | bool "Use the ARM EABI to compile the kernel" | |
1731 | help | |
1732 | This option allows for the kernel to be compiled using the latest | |
1733 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1734 | space environment that is also compiled with EABI. | |
1735 | ||
1736 | Since there are major incompatibilities between the legacy ABI and | |
1737 | EABI, especially with regard to structure member alignment, this | |
1738 | option also changes the kernel syscall calling convention to | |
1739 | disambiguate both ABIs and allow for backward compatibility support | |
1740 | (selected with CONFIG_OABI_COMPAT). | |
1741 | ||
1742 | To use this you need GCC version 4.0.0 or later. | |
1743 | ||
6c90c872 | 1744 | config OABI_COMPAT |
a73a3ff1 | 1745 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1746 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1747 | help |
1748 | This option preserves the old syscall interface along with the | |
1749 | new (ARM EABI) one. It also provides a compatibility layer to | |
1750 | intercept syscalls that have structure arguments which layout | |
1751 | in memory differs between the legacy ABI and the new ARM EABI | |
1752 | (only for non "thumb" binaries). This option adds a tiny | |
1753 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1754 | |
1755 | The seccomp filter system will not be available when this is | |
1756 | selected, since there is no way yet to sensibly distinguish | |
1757 | between calling conventions during filtering. | |
1758 | ||
6c90c872 NP |
1759 | If you know you'll be using only pure EABI user space then you |
1760 | can say N here. If this option is not selected and you attempt | |
1761 | to execute a legacy ABI binary then the result will be | |
1762 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1763 | at all). If in doubt say N. |
6c90c872 | 1764 | |
eb33575c | 1765 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1766 | bool |
e80d6a24 | 1767 | |
05944d74 RK |
1768 | config ARCH_SPARSEMEM_ENABLE |
1769 | bool | |
1770 | ||
07a2f737 RK |
1771 | config ARCH_SPARSEMEM_DEFAULT |
1772 | def_bool ARCH_SPARSEMEM_ENABLE | |
1773 | ||
05944d74 | 1774 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1775 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1776 | |
7b7bf499 WD |
1777 | config HAVE_ARCH_PFN_VALID |
1778 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1779 | ||
053a96ca | 1780 | config HIGHMEM |
e8db89a2 RK |
1781 | bool "High Memory Support" |
1782 | depends on MMU | |
053a96ca NP |
1783 | help |
1784 | The address space of ARM processors is only 4 Gigabytes large | |
1785 | and it has to accommodate user address space, kernel address | |
1786 | space as well as some memory mapped IO. That means that, if you | |
1787 | have a large amount of physical memory and/or IO, not all of the | |
1788 | memory can be "permanently mapped" by the kernel. The physical | |
1789 | memory that is not permanently mapped is called "high memory". | |
1790 | ||
1791 | Depending on the selected kernel/user memory split, minimum | |
1792 | vmalloc space and actual amount of RAM, you may not need this | |
1793 | option which should result in a slightly faster kernel. | |
1794 | ||
1795 | If unsure, say n. | |
1796 | ||
65cec8e3 RK |
1797 | config HIGHPTE |
1798 | bool "Allocate 2nd-level pagetables from highmem" | |
1799 | depends on HIGHMEM | |
65cec8e3 | 1800 | |
1b8873a0 JI |
1801 | config HW_PERF_EVENTS |
1802 | bool "Enable hardware performance counter support for perf events" | |
f0d1bc47 | 1803 | depends on PERF_EVENTS |
1b8873a0 JI |
1804 | default y |
1805 | help | |
1806 | Enable hardware performance counter support for perf events. If | |
1807 | disabled, perf events will use software events only. | |
1808 | ||
1355e2a6 CM |
1809 | config SYS_SUPPORTS_HUGETLBFS |
1810 | def_bool y | |
1811 | depends on ARM_LPAE | |
1812 | ||
8d962507 CM |
1813 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1814 | def_bool y | |
1815 | depends on ARM_LPAE | |
1816 | ||
4bfab203 SC |
1817 | config ARCH_WANT_GENERAL_HUGETLB |
1818 | def_bool y | |
1819 | ||
3f22ab27 DH |
1820 | source "mm/Kconfig" |
1821 | ||
c1b2d970 | 1822 | config FORCE_MAX_ZONEORDER |
bf98c1ea LP |
1823 | int "Maximum zone order" if ARCH_SHMOBILE_LEGACY |
1824 | range 11 64 if ARCH_SHMOBILE_LEGACY | |
898f08e1 | 1825 | default "12" if SOC_AM33XX |
6d85e2b0 | 1826 | default "9" if SA1111 || ARCH_EFM32 |
c1b2d970 MD |
1827 | default "11" |
1828 | help | |
1829 | The kernel memory allocator divides physically contiguous memory | |
1830 | blocks into "zones", where each zone is a power of two number of | |
1831 | pages. This option selects the largest power of two that the kernel | |
1832 | keeps in the memory allocator. If you need to allocate very large | |
1833 | blocks of physically contiguous memory, then you may need to | |
1834 | increase this value. | |
1835 | ||
1836 | This config option is actually maximum order plus one. For example, | |
1837 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1838 | ||
1da177e4 LT |
1839 | config ALIGNMENT_TRAP |
1840 | bool | |
f12d0d7c | 1841 | depends on CPU_CP15_MMU |
1da177e4 | 1842 | default y if !ARCH_EBSA110 |
e119bfff | 1843 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1844 | help |
84eb8d06 | 1845 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1846 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1847 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1848 | fetch/store instructions will be emulated in software if you say | |
1849 | here, which has a severe performance impact. This is necessary for | |
1850 | correct operation of some network protocols. With an IP-only | |
1851 | configuration it is safe to say N, otherwise say Y. | |
1852 | ||
39ec58f3 | 1853 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1854 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1855 | depends on MMU | |
39ec58f3 LB |
1856 | default y if CPU_FEROCEON |
1857 | help | |
1858 | Implement faster copy_to_user and clear_user methods for CPU | |
1859 | cores where a 8-word STM instruction give significantly higher | |
1860 | memory write throughput than a sequence of individual 32bit stores. | |
1861 | ||
1862 | A possible side effect is a slight increase in scheduling latency | |
1863 | between threads sharing the same address space if they invoke | |
1864 | such copy operations with large buffers. | |
1865 | ||
1866 | However, if the CPU data cache is using a write-allocate mode, | |
1867 | this option is unlikely to provide any performance gain. | |
1868 | ||
70c70d97 NP |
1869 | config SECCOMP |
1870 | bool | |
1871 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1872 | ---help--- | |
1873 | This kernel feature is useful for number crunching applications | |
1874 | that may need to compute untrusted bytecode during their | |
1875 | execution. By using pipes or other transports made available to | |
1876 | the process as file descriptors supporting the read/write | |
1877 | syscalls, it's possible to isolate those applications in | |
1878 | their own address space using seccomp. Once seccomp is | |
1879 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1880 | and the task is only allowed to execute a few safe syscalls | |
1881 | defined by each seccomp mode. | |
1882 | ||
c743f380 NP |
1883 | config CC_STACKPROTECTOR |
1884 | bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" | |
1885 | help | |
1886 | This option turns on the -fstack-protector GCC feature. This | |
1887 | feature puts, at the beginning of functions, a canary value on | |
1888 | the stack just before the return address, and validates | |
1889 | the value just before actually returning. Stack based buffer | |
1890 | overflows (that need to overwrite this return address) now also | |
1891 | overwrite the canary, which gets detected and the attack is then | |
1892 | neutralized via a kernel panic. | |
1893 | This feature requires gcc version 4.2 or above. | |
1894 | ||
06e6295b SS |
1895 | config SWIOTLB |
1896 | def_bool y | |
1897 | ||
1898 | config IOMMU_HELPER | |
1899 | def_bool SWIOTLB | |
1900 | ||
eff8d644 SS |
1901 | config XEN_DOM0 |
1902 | def_bool y | |
1903 | depends on XEN | |
1904 | ||
1905 | config XEN | |
1906 | bool "Xen guest support on ARM (EXPERIMENTAL)" | |
85323a99 | 1907 | depends on ARM && AEABI && OF |
f880b67d | 1908 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1909 | depends on !GENERIC_ATOMIC64 |
17b7ab80 | 1910 | select ARM_PSCI |
83862ccf | 1911 | select SWIOTLB_XEN |
eff8d644 SS |
1912 | help |
1913 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1914 | ||
1da177e4 LT |
1915 | endmenu |
1916 | ||
1917 | menu "Boot options" | |
1918 | ||
9eb8f674 GL |
1919 | config USE_OF |
1920 | bool "Flattened Device Tree support" | |
b1b3f49c | 1921 | select IRQ_DOMAIN |
9eb8f674 GL |
1922 | select OF |
1923 | select OF_EARLY_FLATTREE | |
1924 | help | |
1925 | Include support for flattened device tree machine descriptions. | |
1926 | ||
bd51e2f5 NP |
1927 | config ATAGS |
1928 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1929 | default y | |
1930 | help | |
1931 | This is the traditional way of passing data to the kernel at boot | |
1932 | time. If you are solely relying on the flattened device tree (or | |
1933 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1934 | to remove ATAGS support from your kernel binary. If unsure, | |
1935 | leave this to y. | |
1936 | ||
1937 | config DEPRECATED_PARAM_STRUCT | |
1938 | bool "Provide old way to pass kernel parameters" | |
1939 | depends on ATAGS | |
1940 | help | |
1941 | This was deprecated in 2001 and announced to live on for 5 years. | |
1942 | Some old boot loaders still use this way. | |
1943 | ||
1da177e4 LT |
1944 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1945 | # TEXT and BSS so we preserve their values in the config files. | |
1946 | config ZBOOT_ROM_TEXT | |
1947 | hex "Compressed ROM boot loader base address" | |
1948 | default "0" | |
1949 | help | |
1950 | The physical address at which the ROM-able zImage is to be | |
1951 | placed in the target. Platforms which normally make use of | |
1952 | ROM-able zImage formats normally set this to a suitable | |
1953 | value in their defconfig file. | |
1954 | ||
1955 | If ZBOOT_ROM is not enabled, this has no effect. | |
1956 | ||
1957 | config ZBOOT_ROM_BSS | |
1958 | hex "Compressed ROM boot loader BSS address" | |
1959 | default "0" | |
1960 | help | |
f8c440b2 DF |
1961 | The base address of an area of read/write memory in the target |
1962 | for the ROM-able zImage which must be available while the | |
1963 | decompressor is running. It must be large enough to hold the | |
1964 | entire decompressed kernel plus an additional 128 KiB. | |
1965 | Platforms which normally make use of ROM-able zImage formats | |
1966 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1967 | |
1968 | If ZBOOT_ROM is not enabled, this has no effect. | |
1969 | ||
1970 | config ZBOOT_ROM | |
1971 | bool "Compressed boot loader in ROM/flash" | |
1972 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
1973 | help | |
1974 | Say Y here if you intend to execute your compressed kernel image | |
1975 | (zImage) directly from ROM or flash. If unsure, say N. | |
1976 | ||
090ab3ff SH |
1977 | choice |
1978 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1979 | depends on ZBOOT_ROM && ARCH_SH7372 |
090ab3ff SH |
1980 | default ZBOOT_ROM_NONE |
1981 | help | |
1982 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
59bf8964 | 1983 | With this enabled it is possible to write the ROM-able zImage |
090ab3ff SH |
1984 | kernel image to an MMC or SD card and boot the kernel straight |
1985 | from the reset vector. At reset the processor Mask ROM will load | |
59bf8964 | 1986 | the first part of the ROM-able zImage which in turn loads the |
090ab3ff SH |
1987 | rest the kernel image to RAM. |
1988 | ||
1989 | config ZBOOT_ROM_NONE | |
1990 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1991 | help | |
1992 | Do not load image from SD or MMC | |
1993 | ||
f45b1149 SH |
1994 | config ZBOOT_ROM_MMCIF |
1995 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
f45b1149 | 1996 | help |
090ab3ff SH |
1997 | Load image from MMCIF hardware block. |
1998 | ||
1999 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
2000 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
2001 | help | |
2002 | Load image from SDHI hardware block | |
2003 | ||
2004 | endchoice | |
f45b1149 | 2005 | |
e2a6a3aa JB |
2006 | config ARM_APPENDED_DTB |
2007 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
d6f94fa0 | 2008 | depends on OF && !ZBOOT_ROM |
e2a6a3aa JB |
2009 | help |
2010 | With this option, the boot code will look for a device tree binary | |
2011 | (DTB) appended to zImage | |
2012 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
2013 | ||
2014 | This is meant as a backward compatibility convenience for those | |
2015 | systems with a bootloader that can't be upgraded to accommodate | |
2016 | the documented boot protocol using a device tree. | |
2017 | ||
2018 | Beware that there is very little in terms of protection against | |
2019 | this option being confused by leftover garbage in memory that might | |
2020 | look like a DTB header after a reboot if no actual DTB is appended | |
2021 | to zImage. Do not leave this option active in a production kernel | |
2022 | if you don't intend to always append a DTB. Proper passing of the | |
2023 | location into r2 of a bootloader provided DTB is always preferable | |
2024 | to this option. | |
2025 | ||
b90b9a38 NP |
2026 | config ARM_ATAG_DTB_COMPAT |
2027 | bool "Supplement the appended DTB with traditional ATAG information" | |
2028 | depends on ARM_APPENDED_DTB | |
2029 | help | |
2030 | Some old bootloaders can't be updated to a DTB capable one, yet | |
2031 | they provide ATAGs with memory configuration, the ramdisk address, | |
2032 | the kernel cmdline string, etc. Such information is dynamically | |
2033 | provided by the bootloader and can't always be stored in a static | |
2034 | DTB. To allow a device tree enabled kernel to be used with such | |
2035 | bootloaders, this option allows zImage to extract the information | |
2036 | from the ATAG list and store it at run time into the appended DTB. | |
2037 | ||
d0f34a11 GR |
2038 | choice |
2039 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
2040 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
2041 | ||
2042 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
2043 | bool "Use bootloader kernel arguments if available" | |
2044 | help | |
2045 | Uses the command-line options passed by the boot loader instead of | |
2046 | the device tree bootargs property. If the boot loader doesn't provide | |
2047 | any, the device tree bootargs property will be used. | |
2048 | ||
2049 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
2050 | bool "Extend with bootloader kernel arguments" | |
2051 | help | |
2052 | The command-line arguments provided by the boot loader will be | |
2053 | appended to the the device tree bootargs property. | |
2054 | ||
2055 | endchoice | |
2056 | ||
1da177e4 LT |
2057 | config CMDLINE |
2058 | string "Default kernel command string" | |
2059 | default "" | |
2060 | help | |
2061 | On some architectures (EBSA110 and CATS), there is currently no way | |
2062 | for the boot loader to pass arguments to the kernel. For these | |
2063 | architectures, you should supply some command-line options at build | |
2064 | time by entering them here. As a minimum, you should specify the | |
2065 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
2066 | ||
4394c124 VB |
2067 | choice |
2068 | prompt "Kernel command line type" if CMDLINE != "" | |
2069 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 2070 | depends on ATAGS |
4394c124 VB |
2071 | |
2072 | config CMDLINE_FROM_BOOTLOADER | |
2073 | bool "Use bootloader kernel arguments if available" | |
2074 | help | |
2075 | Uses the command-line options passed by the boot loader. If | |
2076 | the boot loader doesn't provide any, the default kernel command | |
2077 | string provided in CMDLINE will be used. | |
2078 | ||
2079 | config CMDLINE_EXTEND | |
2080 | bool "Extend bootloader kernel arguments" | |
2081 | help | |
2082 | The command-line arguments provided by the boot loader will be | |
2083 | appended to the default kernel command string. | |
2084 | ||
92d2040d AH |
2085 | config CMDLINE_FORCE |
2086 | bool "Always use the default kernel command string" | |
92d2040d AH |
2087 | help |
2088 | Always use the default kernel command string, even if the boot | |
2089 | loader passes other arguments to the kernel. | |
2090 | This is useful if you cannot or don't want to change the | |
2091 | command-line options your boot loader passes to the kernel. | |
4394c124 | 2092 | endchoice |
92d2040d | 2093 | |
1da177e4 LT |
2094 | config XIP_KERNEL |
2095 | bool "Kernel Execute-In-Place from ROM" | |
387798b3 | 2096 | depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
2097 | help |
2098 | Execute-In-Place allows the kernel to run from non-volatile storage | |
2099 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
2100 | space since the text section of the kernel is not loaded from flash | |
2101 | to RAM. Read-write sections, such as the data section and stack, | |
2102 | are still copied to RAM. The XIP kernel is not compressed since | |
2103 | it has to run directly from flash, so it will take more space to | |
2104 | store it. The flash address used to link the kernel object files, | |
2105 | and for storing it, is configuration dependent. Therefore, if you | |
2106 | say Y here, you must know the proper physical address where to | |
2107 | store the kernel image depending on your own flash memory usage. | |
2108 | ||
2109 | Also note that the make target becomes "make xipImage" rather than | |
2110 | "make zImage" or "make Image". The final kernel binary to put in | |
2111 | ROM memory will be arch/arm/boot/xipImage. | |
2112 | ||
2113 | If unsure, say N. | |
2114 | ||
2115 | config XIP_PHYS_ADDR | |
2116 | hex "XIP Kernel Physical Location" | |
2117 | depends on XIP_KERNEL | |
2118 | default "0x00080000" | |
2119 | help | |
2120 | This is the physical address in your flash memory the kernel will | |
2121 | be linked for and stored to. This address is dependent on your | |
2122 | own flash usage. | |
2123 | ||
c587e4a6 RP |
2124 | config KEXEC |
2125 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 2126 | depends on (!SMP || PM_SLEEP_SMP) |
c587e4a6 RP |
2127 | help |
2128 | kexec is a system call that implements the ability to shutdown your | |
2129 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 2130 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
2131 | you can start any kernel with it, not just Linux. |
2132 | ||
2133 | It is an ongoing process to be certain the hardware in a machine | |
2134 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 2135 | initially work for you. |
c587e4a6 | 2136 | |
4cd9d6f7 RP |
2137 | config ATAGS_PROC |
2138 | bool "Export atags in procfs" | |
bd51e2f5 | 2139 | depends on ATAGS && KEXEC |
b98d7291 | 2140 | default y |
4cd9d6f7 RP |
2141 | help |
2142 | Should the atags used to boot the kernel be exported in an "atags" | |
2143 | file in procfs. Useful with kexec. | |
2144 | ||
cb5d39b3 MW |
2145 | config CRASH_DUMP |
2146 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2147 | help |
2148 | Generate crash dump after being started by kexec. This should | |
2149 | be normally only set in special crash dump kernels which are | |
2150 | loaded in the main kernel with kexec-tools into a specially | |
2151 | reserved region and then later executed after a crash by | |
2152 | kdump/kexec. The crash dump kernel must be compiled to a | |
2153 | memory address not used by the main kernel | |
2154 | ||
2155 | For more details see Documentation/kdump/kdump.txt | |
2156 | ||
e69edc79 EM |
2157 | config AUTO_ZRELADDR |
2158 | bool "Auto calculation of the decompressed kernel image address" | |
e1b31445 | 2159 | depends on !ZBOOT_ROM |
e69edc79 EM |
2160 | help |
2161 | ZRELADDR is the physical address where the decompressed kernel | |
2162 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2163 | will be determined at run-time by masking the current IP with | |
2164 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2165 | from start of memory. | |
2166 | ||
1da177e4 LT |
2167 | endmenu |
2168 | ||
ac9d7efc | 2169 | menu "CPU Power Management" |
1da177e4 | 2170 | |
89c52ed4 | 2171 | if ARCH_HAS_CPUFREQ |
1da177e4 | 2172 | source "drivers/cpufreq/Kconfig" |
1da177e4 LT |
2173 | endif |
2174 | ||
ac9d7efc RK |
2175 | source "drivers/cpuidle/Kconfig" |
2176 | ||
2177 | endmenu | |
2178 | ||
1da177e4 LT |
2179 | menu "Floating point emulation" |
2180 | ||
2181 | comment "At least one emulation must be selected" | |
2182 | ||
2183 | config FPE_NWFPE | |
2184 | bool "NWFPE math emulation" | |
593c252a | 2185 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2186 | ---help--- |
2187 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2188 | This is necessary to run most binaries. Linux does not currently | |
2189 | support floating point hardware so you need to say Y here even if | |
2190 | your machine has an FPA or floating point co-processor podule. | |
2191 | ||
2192 | You may say N here if you are going to load the Acorn FPEmulator | |
2193 | early in the bootup. | |
2194 | ||
2195 | config FPE_NWFPE_XP | |
2196 | bool "Support extended precision" | |
bedf142b | 2197 | depends on FPE_NWFPE |
1da177e4 LT |
2198 | help |
2199 | Say Y to include 80-bit support in the kernel floating-point | |
2200 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2201 | Note that gcc does not generate 80-bit operations by default, | |
2202 | so in most cases this option only enlarges the size of the | |
2203 | floating point emulator without any good reason. | |
2204 | ||
2205 | You almost surely want to say N here. | |
2206 | ||
2207 | config FPE_FASTFPE | |
2208 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2209 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2210 | ---help--- |
2211 | Say Y here to include the FAST floating point emulator in the kernel. | |
2212 | This is an experimental much faster emulator which now also has full | |
2213 | precision for the mantissa. It does not support any exceptions. | |
2214 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2215 | ||
2216 | It should be sufficient for most programs. It may be not suitable | |
2217 | for scientific calculations, but you have to check this for yourself. | |
2218 | If you do not feel you need a faster FP emulation you should better | |
2219 | choose NWFPE. | |
2220 | ||
2221 | config VFP | |
2222 | bool "VFP-format floating point maths" | |
e399b1a4 | 2223 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2224 | help |
2225 | Say Y to include VFP support code in the kernel. This is needed | |
2226 | if your hardware includes a VFP unit. | |
2227 | ||
2228 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2229 | release notes and additional status information. | |
2230 | ||
2231 | Say N if your target does not have VFP hardware. | |
2232 | ||
25ebee02 CM |
2233 | config VFPv3 |
2234 | bool | |
2235 | depends on VFP | |
2236 | default y if CPU_V7 | |
2237 | ||
b5872db4 CM |
2238 | config NEON |
2239 | bool "Advanced SIMD (NEON) Extension support" | |
2240 | depends on VFPv3 && CPU_V7 | |
2241 | help | |
2242 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2243 | Extension. | |
2244 | ||
73c132c1 AB |
2245 | config KERNEL_MODE_NEON |
2246 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 2247 | depends on NEON && AEABI |
73c132c1 AB |
2248 | help |
2249 | Say Y to include support for NEON in kernel mode. | |
2250 | ||
1da177e4 LT |
2251 | endmenu |
2252 | ||
2253 | menu "Userspace binary formats" | |
2254 | ||
2255 | source "fs/Kconfig.binfmt" | |
2256 | ||
2257 | config ARTHUR | |
2258 | tristate "RISC OS personality" | |
704bdda0 | 2259 | depends on !AEABI |
1da177e4 LT |
2260 | help |
2261 | Say Y here to include the kernel code necessary if you want to run | |
2262 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2263 | experimental; if this sounds frightening, say N and sleep in peace. | |
2264 | You can also say M here to compile this support as a module (which | |
2265 | will be called arthur). | |
2266 | ||
2267 | endmenu | |
2268 | ||
2269 | menu "Power management options" | |
2270 | ||
eceab4ac | 2271 | source "kernel/power/Kconfig" |
1da177e4 | 2272 | |
f4cb5700 | 2273 | config ARCH_SUSPEND_POSSIBLE |
4b1082ca | 2274 | depends on !ARCH_S5PC100 |
19a0519d | 2275 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
3f5d0819 | 2276 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2277 | def_bool y |
2278 | ||
15e0d9e3 AB |
2279 | config ARM_CPU_SUSPEND |
2280 | def_bool PM_SLEEP | |
2281 | ||
1da177e4 LT |
2282 | endmenu |
2283 | ||
d5950b43 SR |
2284 | source "net/Kconfig" |
2285 | ||
ac25150f | 2286 | source "drivers/Kconfig" |
1da177e4 LT |
2287 | |
2288 | source "fs/Kconfig" | |
2289 | ||
1da177e4 LT |
2290 | source "arch/arm/Kconfig.debug" |
2291 | ||
2292 | source "security/Kconfig" | |
2293 | ||
2294 | source "crypto/Kconfig" | |
2295 | ||
2296 | source "lib/Kconfig" | |
749cf76c CD |
2297 | |
2298 | source "arch/arm/kvm/Kconfig" |