Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
e17c6d56 | 4 | select HAVE_AOUT |
24056f52 | 5 | select HAVE_DMA_API_DEBUG |
2064c946 | 6 | select HAVE_IDE |
2778f620 | 7 | select HAVE_MEMBLOCK |
12b824fb | 8 | select RTC_LIB |
75e7153a | 9 | select SYS_SUPPORTS_APM_EMULATION |
a41297a0 | 10 | select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) |
fe166148 | 11 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
5cbad0eb | 12 | select HAVE_ARCH_KGDB |
856bc356 | 13 | select HAVE_KPROBES if !XIP_KERNEL |
9edddaa2 | 14 | select HAVE_KRETPROBES if (HAVE_KPROBES) |
606576ce | 15 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
80be7a7f RV |
16 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
17 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) | |
0e341af8 | 18 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
1fe53268 | 19 | select HAVE_GENERIC_DMA_COHERENT |
e7db7b42 AT |
20 | select HAVE_KERNEL_GZIP |
21 | select HAVE_KERNEL_LZO | |
6e8699f7 | 22 | select HAVE_KERNEL_LZMA |
e360adbe | 23 | select HAVE_IRQ_WORK |
7ada189f JI |
24 | select HAVE_PERF_EVENTS |
25 | select PERF_USE_VMALLOC | |
e513f8bf | 26 | select HAVE_REGS_AND_STACK_ACCESS_API |
e399b1a4 | 27 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
ed60453f | 28 | select HAVE_C_RECORDMCOUNT |
e2a93ecc LB |
29 | select HAVE_GENERIC_HARDIRQS |
30 | select HAVE_SPARSE_IRQ | |
25a5662a | 31 | select GENERIC_IRQ_SHOW |
1da177e4 LT |
32 | help |
33 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 34 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 35 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 36 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
37 | Europe. There is an ARM Linux project with a web page at |
38 | <http://www.arm.linux.org.uk/>. | |
39 | ||
74facffe RK |
40 | config ARM_HAS_SG_CHAIN |
41 | bool | |
42 | ||
1a189b97 RK |
43 | config HAVE_PWM |
44 | bool | |
45 | ||
0b05da72 HUK |
46 | config MIGHT_HAVE_PCI |
47 | bool | |
48 | ||
75e7153a RB |
49 | config SYS_SUPPORTS_APM_EMULATION |
50 | bool | |
51 | ||
112f38a4 RK |
52 | config HAVE_SCHED_CLOCK |
53 | bool | |
54 | ||
0a938b97 DB |
55 | config GENERIC_GPIO |
56 | bool | |
0a938b97 | 57 | |
5cfc8ee0 JS |
58 | config ARCH_USES_GETTIMEOFFSET |
59 | bool | |
60 | default n | |
746140c7 | 61 | |
0567a0c0 KH |
62 | config GENERIC_CLOCKEVENTS |
63 | bool | |
0567a0c0 | 64 | |
a8655e83 CM |
65 | config GENERIC_CLOCKEVENTS_BROADCAST |
66 | bool | |
67 | depends on GENERIC_CLOCKEVENTS | |
5388a6b2 | 68 | default y if SMP |
a8655e83 | 69 | |
bf9dd360 RH |
70 | config KTIME_SCALAR |
71 | bool | |
72 | default y | |
73 | ||
bc581770 LW |
74 | config HAVE_TCM |
75 | bool | |
76 | select GENERIC_ALLOCATOR | |
77 | ||
e119bfff RK |
78 | config HAVE_PROC_CPU |
79 | bool | |
80 | ||
5ea81769 AV |
81 | config NO_IOPORT |
82 | bool | |
5ea81769 | 83 | |
1da177e4 LT |
84 | config EISA |
85 | bool | |
86 | ---help--- | |
87 | The Extended Industry Standard Architecture (EISA) bus was | |
88 | developed as an open alternative to the IBM MicroChannel bus. | |
89 | ||
90 | The EISA bus provided some of the features of the IBM MicroChannel | |
91 | bus while maintaining backward compatibility with cards made for | |
92 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
93 | 1995 when it was made obsolete by the PCI bus. | |
94 | ||
95 | Say Y here if you are building a kernel for an EISA-based machine. | |
96 | ||
97 | Otherwise, say N. | |
98 | ||
99 | config SBUS | |
100 | bool | |
101 | ||
102 | config MCA | |
103 | bool | |
104 | help | |
105 | MicroChannel Architecture is found in some IBM PS/2 machines and | |
106 | laptops. It is a bus system similar to PCI or ISA. See | |
107 | <file:Documentation/mca.txt> (and especially the web page given | |
108 | there) before attempting to build an MCA bus kernel. | |
109 | ||
f16fb1ec RK |
110 | config STACKTRACE_SUPPORT |
111 | bool | |
112 | default y | |
113 | ||
f76e9154 NP |
114 | config HAVE_LATENCYTOP_SUPPORT |
115 | bool | |
116 | depends on !SMP | |
117 | default y | |
118 | ||
f16fb1ec RK |
119 | config LOCKDEP_SUPPORT |
120 | bool | |
121 | default y | |
122 | ||
7ad1bcb2 RK |
123 | config TRACE_IRQFLAGS_SUPPORT |
124 | bool | |
125 | default y | |
126 | ||
4a2581a0 TG |
127 | config HARDIRQS_SW_RESEND |
128 | bool | |
129 | default y | |
130 | ||
131 | config GENERIC_IRQ_PROBE | |
132 | bool | |
133 | default y | |
134 | ||
95c354fe NP |
135 | config GENERIC_LOCKBREAK |
136 | bool | |
137 | default y | |
138 | depends on SMP && PREEMPT | |
139 | ||
1da177e4 LT |
140 | config RWSEM_GENERIC_SPINLOCK |
141 | bool | |
142 | default y | |
143 | ||
144 | config RWSEM_XCHGADD_ALGORITHM | |
145 | bool | |
146 | ||
f0d1b0b3 DH |
147 | config ARCH_HAS_ILOG2_U32 |
148 | bool | |
f0d1b0b3 DH |
149 | |
150 | config ARCH_HAS_ILOG2_U64 | |
151 | bool | |
f0d1b0b3 | 152 | |
89c52ed4 BD |
153 | config ARCH_HAS_CPUFREQ |
154 | bool | |
155 | help | |
156 | Internal node to signify that the ARCH has CPUFREQ support | |
157 | and that the relevant menu configurations are displayed for | |
158 | it. | |
159 | ||
c7b0aff4 KH |
160 | config ARCH_HAS_CPU_IDLE_WAIT |
161 | def_bool y | |
162 | ||
b89c3b16 AM |
163 | config GENERIC_HWEIGHT |
164 | bool | |
165 | default y | |
166 | ||
1da177e4 LT |
167 | config GENERIC_CALIBRATE_DELAY |
168 | bool | |
169 | default y | |
170 | ||
a08b6b79 Z |
171 | config ARCH_MAY_HAVE_PC_FDC |
172 | bool | |
173 | ||
5ac6da66 CL |
174 | config ZONE_DMA |
175 | bool | |
5ac6da66 | 176 | |
ccd7ab7f FT |
177 | config NEED_DMA_MAP_STATE |
178 | def_bool y | |
179 | ||
1da177e4 LT |
180 | config GENERIC_ISA_DMA |
181 | bool | |
182 | ||
1da177e4 LT |
183 | config FIQ |
184 | bool | |
185 | ||
034d2f5a AV |
186 | config ARCH_MTD_XIP |
187 | bool | |
188 | ||
c760fc19 HC |
189 | config VECTORS_BASE |
190 | hex | |
6afd6fae | 191 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
192 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
193 | default 0x00000000 | |
194 | help | |
195 | The base address of exception vectors. | |
196 | ||
dc21af99 | 197 | config ARM_PATCH_PHYS_VIRT |
4eb979d4 | 198 | bool "Patch physical to virtual translations at runtime" |
b511d75d | 199 | depends on !XIP_KERNEL && MMU |
dc21af99 RK |
200 | depends on !ARCH_REALVIEW || !SPARSEMEM |
201 | help | |
111e9a5c RK |
202 | Patch phys-to-virt and virt-to-phys translation functions at |
203 | boot and module load time according to the position of the | |
204 | kernel in system memory. | |
dc21af99 | 205 | |
111e9a5c RK |
206 | This can only be used with non-XIP MMU kernels where the base |
207 | of physical memory is at a 16MB boundary, or theoretically 64K | |
208 | for the MSM machine class. | |
dc21af99 | 209 | |
cada3c08 RK |
210 | config ARM_PATCH_PHYS_VIRT_16BIT |
211 | def_bool y | |
212 | depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM | |
111e9a5c RK |
213 | help |
214 | This option extends the physical to virtual translation patching | |
215 | to allow physical memory down to a theoretical minimum of 64K | |
216 | boundaries. | |
cada3c08 | 217 | |
1da177e4 LT |
218 | source "init/Kconfig" |
219 | ||
dc52ddc0 MH |
220 | source "kernel/Kconfig.freezer" |
221 | ||
1da177e4 LT |
222 | menu "System Type" |
223 | ||
3c427975 HC |
224 | config MMU |
225 | bool "MMU-based Paged Memory Management Support" | |
226 | default y | |
227 | help | |
228 | Select if you want MMU-based virtualised addressing space | |
229 | support by paged memory management. If unsure, say 'Y'. | |
230 | ||
ccf50e23 RK |
231 | # |
232 | # The "ARM system type" choice list is ordered alphabetically by option | |
233 | # text. Please add new entries in the option alphabetic order. | |
234 | # | |
1da177e4 LT |
235 | choice |
236 | prompt "ARM system type" | |
6a0e2430 | 237 | default ARCH_VERSATILE |
1da177e4 | 238 | |
4af6fee1 DS |
239 | config ARCH_INTEGRATOR |
240 | bool "ARM Ltd. Integrator family" | |
241 | select ARM_AMBA | |
89c52ed4 | 242 | select ARCH_HAS_CPUFREQ |
6d803ba7 | 243 | select CLKDEV_LOOKUP |
aa3831cf | 244 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 245 | select ICST |
13edd86d | 246 | select GENERIC_CLOCKEVENTS |
f4b8b319 | 247 | select PLAT_VERSATILE |
c41b16f8 | 248 | select PLAT_VERSATILE_FPGA_IRQ |
4af6fee1 DS |
249 | help |
250 | Support for ARM's Integrator platform. | |
251 | ||
252 | config ARCH_REALVIEW | |
253 | bool "ARM Ltd. RealView family" | |
254 | select ARM_AMBA | |
6d803ba7 | 255 | select CLKDEV_LOOKUP |
aa3831cf | 256 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 257 | select ICST |
ae30ceac | 258 | select GENERIC_CLOCKEVENTS |
eb7fffa3 | 259 | select ARCH_WANT_OPTIONAL_GPIOLIB |
f4b8b319 | 260 | select PLAT_VERSATILE |
3cb5ee49 | 261 | select PLAT_VERSATILE_CLCD |
e3887714 | 262 | select ARM_TIMER_SP804 |
b56ba8aa | 263 | select GPIO_PL061 if GPIOLIB |
4af6fee1 DS |
264 | help |
265 | This enables support for ARM Ltd RealView boards. | |
266 | ||
267 | config ARCH_VERSATILE | |
268 | bool "ARM Ltd. Versatile family" | |
269 | select ARM_AMBA | |
270 | select ARM_VIC | |
6d803ba7 | 271 | select CLKDEV_LOOKUP |
aa3831cf | 272 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 273 | select ICST |
89df1272 | 274 | select GENERIC_CLOCKEVENTS |
bbeddc43 | 275 | select ARCH_WANT_OPTIONAL_GPIOLIB |
f4b8b319 | 276 | select PLAT_VERSATILE |
3414ba8c | 277 | select PLAT_VERSATILE_CLCD |
c41b16f8 | 278 | select PLAT_VERSATILE_FPGA_IRQ |
e3887714 | 279 | select ARM_TIMER_SP804 |
4af6fee1 DS |
280 | help |
281 | This enables support for ARM Ltd Versatile board. | |
282 | ||
ceade897 RK |
283 | config ARCH_VEXPRESS |
284 | bool "ARM Ltd. Versatile Express family" | |
285 | select ARCH_WANT_OPTIONAL_GPIOLIB | |
286 | select ARM_AMBA | |
287 | select ARM_TIMER_SP804 | |
6d803ba7 | 288 | select CLKDEV_LOOKUP |
aa3831cf | 289 | select HAVE_MACH_CLKDEV |
ceade897 | 290 | select GENERIC_CLOCKEVENTS |
ceade897 | 291 | select HAVE_CLK |
95c34f83 | 292 | select HAVE_PATA_PLATFORM |
ceade897 RK |
293 | select ICST |
294 | select PLAT_VERSATILE | |
0fb44b91 | 295 | select PLAT_VERSATILE_CLCD |
ceade897 RK |
296 | help |
297 | This enables support for the ARM Ltd Versatile Express boards. | |
298 | ||
8fc5ffa0 AV |
299 | config ARCH_AT91 |
300 | bool "Atmel AT91" | |
f373e8c0 | 301 | select ARCH_REQUIRE_GPIOLIB |
93686ae8 | 302 | select HAVE_CLK |
bd602995 | 303 | select CLKDEV_LOOKUP |
3d51f259 | 304 | select ARM_PATCH_PHYS_VIRT if MMU |
4af6fee1 | 305 | help |
2b3b3516 AV |
306 | This enables support for systems based on the Atmel AT91RM9200, |
307 | AT91SAM9 and AT91CAP9 processors. | |
4af6fee1 | 308 | |
ccf50e23 RK |
309 | config ARCH_BCMRING |
310 | bool "Broadcom BCMRING" | |
311 | depends on MMU | |
312 | select CPU_V6 | |
313 | select ARM_AMBA | |
82d63734 | 314 | select ARM_TIMER_SP804 |
6d803ba7 | 315 | select CLKDEV_LOOKUP |
ccf50e23 RK |
316 | select GENERIC_CLOCKEVENTS |
317 | select ARCH_WANT_OPTIONAL_GPIOLIB | |
318 | help | |
319 | Support for Broadcom's BCMRing platform. | |
320 | ||
1da177e4 | 321 | config ARCH_CLPS711X |
4af6fee1 | 322 | bool "Cirrus Logic CLPS711x/EP721x-based" |
c750815e | 323 | select CPU_ARM720T |
5cfc8ee0 | 324 | select ARCH_USES_GETTIMEOFFSET |
f999b8bd MM |
325 | help |
326 | Support for Cirrus Logic 711x/721x based boards. | |
1da177e4 | 327 | |
d94f944e AV |
328 | config ARCH_CNS3XXX |
329 | bool "Cavium Networks CNS3XXX family" | |
00d2711d | 330 | select CPU_V6K |
d94f944e AV |
331 | select GENERIC_CLOCKEVENTS |
332 | select ARM_GIC | |
0b05da72 | 333 | select MIGHT_HAVE_PCI |
5f32f7a0 | 334 | select PCI_DOMAINS if PCI |
d94f944e AV |
335 | help |
336 | Support for Cavium Networks CNS3XXX platform. | |
337 | ||
788c9700 RK |
338 | config ARCH_GEMINI |
339 | bool "Cortina Systems Gemini" | |
340 | select CPU_FA526 | |
788c9700 | 341 | select ARCH_REQUIRE_GPIOLIB |
5cfc8ee0 | 342 | select ARCH_USES_GETTIMEOFFSET |
788c9700 RK |
343 | help |
344 | Support for the Cortina Systems Gemini family SoCs | |
345 | ||
3a6cb8ce AB |
346 | config ARCH_PRIMA2 |
347 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" | |
348 | select CPU_V7 | |
349 | select GENERIC_TIME | |
350 | select NO_IOPORT | |
351 | select GENERIC_CLOCKEVENTS | |
352 | select CLKDEV_LOOKUP | |
353 | select GENERIC_IRQ_CHIP | |
354 | select USE_OF | |
355 | select ZONE_DMA | |
356 | help | |
357 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
358 | ||
1da177e4 LT |
359 | config ARCH_EBSA110 |
360 | bool "EBSA-110" | |
c750815e | 361 | select CPU_SA110 |
f7e68bbf | 362 | select ISA |
c5eb2a2b | 363 | select NO_IOPORT |
5cfc8ee0 | 364 | select ARCH_USES_GETTIMEOFFSET |
1da177e4 LT |
365 | help |
366 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 367 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
368 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
369 | parallel port. | |
370 | ||
e7736d47 LB |
371 | config ARCH_EP93XX |
372 | bool "EP93xx-based" | |
c750815e | 373 | select CPU_ARM920T |
e7736d47 LB |
374 | select ARM_AMBA |
375 | select ARM_VIC | |
6d803ba7 | 376 | select CLKDEV_LOOKUP |
7444a72e | 377 | select ARCH_REQUIRE_GPIOLIB |
eb33575c | 378 | select ARCH_HAS_HOLES_MEMORYMODEL |
5cfc8ee0 | 379 | select ARCH_USES_GETTIMEOFFSET |
e7736d47 LB |
380 | help |
381 | This enables support for the Cirrus EP93xx series of CPUs. | |
382 | ||
1da177e4 LT |
383 | config ARCH_FOOTBRIDGE |
384 | bool "FootBridge" | |
c750815e | 385 | select CPU_SA110 |
1da177e4 | 386 | select FOOTBRIDGE |
4e8d7637 | 387 | select GENERIC_CLOCKEVENTS |
f999b8bd MM |
388 | help |
389 | Support for systems based on the DC21285 companion chip | |
390 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 391 | |
788c9700 RK |
392 | config ARCH_MXC |
393 | bool "Freescale MXC/iMX-based" | |
788c9700 | 394 | select GENERIC_CLOCKEVENTS |
788c9700 | 395 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 396 | select CLKDEV_LOOKUP |
234b6ced | 397 | select CLKSRC_MMIO |
8b6c44f1 | 398 | select GENERIC_IRQ_CHIP |
c124befc | 399 | select HAVE_SCHED_CLOCK |
788c9700 RK |
400 | help |
401 | Support for Freescale MXC/iMX-based family of processors | |
402 | ||
1d3f33d5 SG |
403 | config ARCH_MXS |
404 | bool "Freescale MXS-based" | |
405 | select GENERIC_CLOCKEVENTS | |
406 | select ARCH_REQUIRE_GPIOLIB | |
b9214b97 | 407 | select CLKDEV_LOOKUP |
5c61ddcf | 408 | select CLKSRC_MMIO |
1d3f33d5 SG |
409 | help |
410 | Support for Freescale MXS-based family of processors | |
411 | ||
4af6fee1 DS |
412 | config ARCH_NETX |
413 | bool "Hilscher NetX based" | |
234b6ced | 414 | select CLKSRC_MMIO |
c750815e | 415 | select CPU_ARM926T |
4af6fee1 | 416 | select ARM_VIC |
2fcfe6b8 | 417 | select GENERIC_CLOCKEVENTS |
f999b8bd | 418 | help |
4af6fee1 DS |
419 | This enables support for systems based on the Hilscher NetX Soc |
420 | ||
421 | config ARCH_H720X | |
422 | bool "Hynix HMS720x-based" | |
c750815e | 423 | select CPU_ARM720T |
4af6fee1 | 424 | select ISA_DMA_API |
5cfc8ee0 | 425 | select ARCH_USES_GETTIMEOFFSET |
4af6fee1 DS |
426 | help |
427 | This enables support for systems based on the Hynix HMS720x | |
428 | ||
3b938be6 RK |
429 | config ARCH_IOP13XX |
430 | bool "IOP13xx-based" | |
431 | depends on MMU | |
c750815e | 432 | select CPU_XSC3 |
3b938be6 RK |
433 | select PLAT_IOP |
434 | select PCI | |
435 | select ARCH_SUPPORTS_MSI | |
8d5796d2 | 436 | select VMSPLIT_1G |
3b938be6 RK |
437 | help |
438 | Support for Intel's IOP13XX (XScale) family of processors. | |
439 | ||
3f7e5815 LB |
440 | config ARCH_IOP32X |
441 | bool "IOP32x-based" | |
a4f7e763 | 442 | depends on MMU |
c750815e | 443 | select CPU_XSCALE |
7ae1f7ec | 444 | select PLAT_IOP |
f7e68bbf | 445 | select PCI |
bb2b180c | 446 | select ARCH_REQUIRE_GPIOLIB |
f999b8bd | 447 | help |
3f7e5815 LB |
448 | Support for Intel's 80219 and IOP32X (XScale) family of |
449 | processors. | |
450 | ||
451 | config ARCH_IOP33X | |
452 | bool "IOP33x-based" | |
453 | depends on MMU | |
c750815e | 454 | select CPU_XSCALE |
7ae1f7ec | 455 | select PLAT_IOP |
3f7e5815 | 456 | select PCI |
bb2b180c | 457 | select ARCH_REQUIRE_GPIOLIB |
3f7e5815 LB |
458 | help |
459 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 460 | |
3b938be6 RK |
461 | config ARCH_IXP23XX |
462 | bool "IXP23XX-based" | |
a4f7e763 | 463 | depends on MMU |
c750815e | 464 | select CPU_XSC3 |
3b938be6 | 465 | select PCI |
5cfc8ee0 | 466 | select ARCH_USES_GETTIMEOFFSET |
f999b8bd | 467 | help |
3b938be6 | 468 | Support for Intel's IXP23xx (XScale) family of processors. |
1da177e4 LT |
469 | |
470 | config ARCH_IXP2000 | |
471 | bool "IXP2400/2800-based" | |
a4f7e763 | 472 | depends on MMU |
c750815e | 473 | select CPU_XSCALE |
f7e68bbf | 474 | select PCI |
5cfc8ee0 | 475 | select ARCH_USES_GETTIMEOFFSET |
f999b8bd MM |
476 | help |
477 | Support for Intel's IXP2400/2800 (XScale) family of processors. | |
1da177e4 | 478 | |
3b938be6 RK |
479 | config ARCH_IXP4XX |
480 | bool "IXP4xx-based" | |
a4f7e763 | 481 | depends on MMU |
234b6ced | 482 | select CLKSRC_MMIO |
c750815e | 483 | select CPU_XSCALE |
8858e9af | 484 | select GENERIC_GPIO |
3b938be6 | 485 | select GENERIC_CLOCKEVENTS |
5b0d495c | 486 | select HAVE_SCHED_CLOCK |
0b05da72 | 487 | select MIGHT_HAVE_PCI |
485bdde7 | 488 | select DMABOUNCE if PCI |
c4713074 | 489 | help |
3b938be6 | 490 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 491 | |
edabd38e SB |
492 | config ARCH_DOVE |
493 | bool "Marvell Dove" | |
7b769bb3 | 494 | select CPU_V7 |
edabd38e | 495 | select PCI |
edabd38e | 496 | select ARCH_REQUIRE_GPIOLIB |
edabd38e SB |
497 | select GENERIC_CLOCKEVENTS |
498 | select PLAT_ORION | |
499 | help | |
500 | Support for the Marvell Dove SoC 88AP510 | |
501 | ||
651c74c7 SB |
502 | config ARCH_KIRKWOOD |
503 | bool "Marvell Kirkwood" | |
c750815e | 504 | select CPU_FEROCEON |
651c74c7 | 505 | select PCI |
a8865655 | 506 | select ARCH_REQUIRE_GPIOLIB |
651c74c7 SB |
507 | select GENERIC_CLOCKEVENTS |
508 | select PLAT_ORION | |
509 | help | |
510 | Support for the following Marvell Kirkwood series SoCs: | |
511 | 88F6180, 88F6192 and 88F6281. | |
512 | ||
40805949 KW |
513 | config ARCH_LPC32XX |
514 | bool "NXP LPC32XX" | |
234b6ced | 515 | select CLKSRC_MMIO |
40805949 KW |
516 | select CPU_ARM926T |
517 | select ARCH_REQUIRE_GPIOLIB | |
518 | select HAVE_IDE | |
519 | select ARM_AMBA | |
520 | select USB_ARCH_HAS_OHCI | |
6d803ba7 | 521 | select CLKDEV_LOOKUP |
40805949 KW |
522 | select GENERIC_TIME |
523 | select GENERIC_CLOCKEVENTS | |
524 | help | |
525 | Support for the NXP LPC32XX family of processors | |
526 | ||
794d15b2 SS |
527 | config ARCH_MV78XX0 |
528 | bool "Marvell MV78xx0" | |
c750815e | 529 | select CPU_FEROCEON |
794d15b2 | 530 | select PCI |
a8865655 | 531 | select ARCH_REQUIRE_GPIOLIB |
794d15b2 SS |
532 | select GENERIC_CLOCKEVENTS |
533 | select PLAT_ORION | |
534 | help | |
535 | Support for the following Marvell MV78xx0 series SoCs: | |
536 | MV781x0, MV782x0. | |
537 | ||
9dd0b194 | 538 | config ARCH_ORION5X |
585cf175 TP |
539 | bool "Marvell Orion" |
540 | depends on MMU | |
c750815e | 541 | select CPU_FEROCEON |
038ee083 | 542 | select PCI |
a8865655 | 543 | select ARCH_REQUIRE_GPIOLIB |
51cbff1d | 544 | select GENERIC_CLOCKEVENTS |
69b02f6a | 545 | select PLAT_ORION |
585cf175 | 546 | help |
9dd0b194 | 547 | Support for the following Marvell Orion 5x series SoCs: |
d2b2a6bb | 548 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
d323ade1 | 549 | Orion-2 (5281), Orion-1-90 (6183). |
585cf175 | 550 | |
788c9700 | 551 | config ARCH_MMP |
2f7e8fae | 552 | bool "Marvell PXA168/910/MMP2" |
788c9700 | 553 | depends on MMU |
788c9700 | 554 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 555 | select CLKDEV_LOOKUP |
788c9700 | 556 | select GENERIC_CLOCKEVENTS |
28bb7bc6 | 557 | select HAVE_SCHED_CLOCK |
788c9700 RK |
558 | select TICK_ONESHOT |
559 | select PLAT_PXA | |
0bd86961 | 560 | select SPARSE_IRQ |
788c9700 | 561 | help |
2f7e8fae | 562 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. |
788c9700 RK |
563 | |
564 | config ARCH_KS8695 | |
565 | bool "Micrel/Kendin KS8695" | |
566 | select CPU_ARM922T | |
98830bc9 | 567 | select ARCH_REQUIRE_GPIOLIB |
5cfc8ee0 | 568 | select ARCH_USES_GETTIMEOFFSET |
788c9700 RK |
569 | help |
570 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
571 | System-on-Chip devices. | |
572 | ||
788c9700 RK |
573 | config ARCH_W90X900 |
574 | bool "Nuvoton W90X900 CPU" | |
575 | select CPU_ARM926T | |
c52d3d68 | 576 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 577 | select CLKDEV_LOOKUP |
6fa5d5f7 | 578 | select CLKSRC_MMIO |
58b5369e | 579 | select GENERIC_CLOCKEVENTS |
788c9700 | 580 | help |
a8bc4ead | 581 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
582 | At present, the w90x900 has been renamed nuc900, regarding | |
583 | the ARM series product line, you can login the following | |
584 | link address to know more. | |
585 | ||
586 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
587 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 588 | |
a62e9030 | 589 | config ARCH_NUC93X |
590 | bool "Nuvoton NUC93X CPU" | |
591 | select CPU_ARM926T | |
6d803ba7 | 592 | select CLKDEV_LOOKUP |
a62e9030 | 593 | help |
594 | Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a | |
595 | low-power and high performance MPEG-4/JPEG multimedia controller chip. | |
596 | ||
c5f80065 EG |
597 | config ARCH_TEGRA |
598 | bool "NVIDIA Tegra" | |
4073723a | 599 | select CLKDEV_LOOKUP |
234b6ced | 600 | select CLKSRC_MMIO |
c5f80065 EG |
601 | select GENERIC_TIME |
602 | select GENERIC_CLOCKEVENTS | |
603 | select GENERIC_GPIO | |
604 | select HAVE_CLK | |
e3f4c0ab | 605 | select HAVE_SCHED_CLOCK |
7056d423 | 606 | select ARCH_HAS_CPUFREQ |
c5f80065 EG |
607 | help |
608 | This enables support for NVIDIA Tegra based systems (Tegra APX, | |
609 | Tegra 6xx and Tegra 2 series). | |
610 | ||
4af6fee1 DS |
611 | config ARCH_PNX4008 |
612 | bool "Philips Nexperia PNX4008 Mobile" | |
c750815e | 613 | select CPU_ARM926T |
6d803ba7 | 614 | select CLKDEV_LOOKUP |
5cfc8ee0 | 615 | select ARCH_USES_GETTIMEOFFSET |
4af6fee1 DS |
616 | help |
617 | This enables support for Philips PNX4008 mobile platform. | |
618 | ||
1da177e4 | 619 | config ARCH_PXA |
2c8086a5 | 620 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 621 | depends on MMU |
034d2f5a | 622 | select ARCH_MTD_XIP |
89c52ed4 | 623 | select ARCH_HAS_CPUFREQ |
6d803ba7 | 624 | select CLKDEV_LOOKUP |
234b6ced | 625 | select CLKSRC_MMIO |
7444a72e | 626 | select ARCH_REQUIRE_GPIOLIB |
981d0f39 | 627 | select GENERIC_CLOCKEVENTS |
7ce83018 | 628 | select HAVE_SCHED_CLOCK |
a88264c2 | 629 | select TICK_ONESHOT |
bd5ce433 | 630 | select PLAT_PXA |
6ac6b817 | 631 | select SPARSE_IRQ |
4e234cc0 | 632 | select AUTO_ZRELADDR |
8a97ae2f | 633 | select MULTI_IRQ_HANDLER |
f999b8bd | 634 | help |
2c8086a5 | 635 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 | 636 | |
788c9700 RK |
637 | config ARCH_MSM |
638 | bool "Qualcomm MSM" | |
4b536b8d | 639 | select HAVE_CLK |
49cbe786 | 640 | select GENERIC_CLOCKEVENTS |
923a081c | 641 | select ARCH_REQUIRE_GPIOLIB |
bd32344a | 642 | select CLKDEV_LOOKUP |
49cbe786 | 643 | help |
4b53eb4f DW |
644 | Support for Qualcomm MSM/QSD based systems. This runs on the |
645 | apps processor of the MSM/QSD and depends on a shared memory | |
646 | interface to the modem processor which runs the baseband | |
647 | stack and controls some vital subsystems | |
648 | (clock and power control, etc). | |
49cbe786 | 649 | |
c793c1b0 | 650 | config ARCH_SHMOBILE |
6d72ad35 PM |
651 | bool "Renesas SH-Mobile / R-Mobile" |
652 | select HAVE_CLK | |
5e93c6b4 | 653 | select CLKDEV_LOOKUP |
aa3831cf | 654 | select HAVE_MACH_CLKDEV |
6d72ad35 PM |
655 | select GENERIC_CLOCKEVENTS |
656 | select NO_IOPORT | |
657 | select SPARSE_IRQ | |
60f1435c | 658 | select MULTI_IRQ_HANDLER |
e3e01091 | 659 | select PM_GENERIC_DOMAINS if PM |
c793c1b0 | 660 | help |
6d72ad35 | 661 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms. |
c793c1b0 | 662 | |
1da177e4 LT |
663 | config ARCH_RPC |
664 | bool "RiscPC" | |
665 | select ARCH_ACORN | |
666 | select FIQ | |
667 | select TIMER_ACORN | |
a08b6b79 | 668 | select ARCH_MAY_HAVE_PC_FDC |
341eb781 | 669 | select HAVE_PATA_PLATFORM |
065909b9 | 670 | select ISA_DMA_API |
5ea81769 | 671 | select NO_IOPORT |
07f841b7 | 672 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 673 | select ARCH_USES_GETTIMEOFFSET |
1da177e4 LT |
674 | help |
675 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
676 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
677 | ||
678 | config ARCH_SA1100 | |
679 | bool "SA1100-based" | |
234b6ced | 680 | select CLKSRC_MMIO |
c750815e | 681 | select CPU_SA1100 |
f7e68bbf | 682 | select ISA |
05944d74 | 683 | select ARCH_SPARSEMEM_ENABLE |
034d2f5a | 684 | select ARCH_MTD_XIP |
89c52ed4 | 685 | select ARCH_HAS_CPUFREQ |
1937f5b9 | 686 | select CPU_FREQ |
3e238be2 | 687 | select GENERIC_CLOCKEVENTS |
9483a578 | 688 | select HAVE_CLK |
5094b92f | 689 | select HAVE_SCHED_CLOCK |
3e238be2 | 690 | select TICK_ONESHOT |
7444a72e | 691 | select ARCH_REQUIRE_GPIOLIB |
f999b8bd MM |
692 | help |
693 | Support for StrongARM 11x0 based boards. | |
1da177e4 LT |
694 | |
695 | config ARCH_S3C2410 | |
63b1f51b | 696 | bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" |
0a938b97 | 697 | select GENERIC_GPIO |
9d56c02a | 698 | select ARCH_HAS_CPUFREQ |
9483a578 | 699 | select HAVE_CLK |
e83626f2 | 700 | select CLKDEV_LOOKUP |
5cfc8ee0 | 701 | select ARCH_USES_GETTIMEOFFSET |
20676c15 | 702 | select HAVE_S3C2410_I2C if I2C |
1da177e4 LT |
703 | help |
704 | Samsung S3C2410X CPU based systems, such as the Simtec Electronics | |
705 | BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or | |
f6c8965a | 706 | the Samsung SMDK2410 development board (and derivatives). |
1da177e4 | 707 | |
63b1f51b | 708 | Note, the S3C2416 and the S3C2450 are so close that they even share |
25985edc | 709 | the same SoC ID code. This means that there is no separate machine |
63b1f51b BD |
710 | directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. |
711 | ||
a08ab637 BD |
712 | config ARCH_S3C64XX |
713 | bool "Samsung S3C64XX" | |
89f1fa08 | 714 | select PLAT_SAMSUNG |
89f0ce72 | 715 | select CPU_V6 |
89f0ce72 | 716 | select ARM_VIC |
a08ab637 | 717 | select HAVE_CLK |
226e85f4 | 718 | select CLKDEV_LOOKUP |
89f0ce72 | 719 | select NO_IOPORT |
5cfc8ee0 | 720 | select ARCH_USES_GETTIMEOFFSET |
89c52ed4 | 721 | select ARCH_HAS_CPUFREQ |
89f0ce72 BD |
722 | select ARCH_REQUIRE_GPIOLIB |
723 | select SAMSUNG_CLKSRC | |
724 | select SAMSUNG_IRQ_VIC_TIMER | |
725 | select SAMSUNG_IRQ_UART | |
726 | select S3C_GPIO_TRACK | |
727 | select S3C_GPIO_PULL_UPDOWN | |
728 | select S3C_GPIO_CFG_S3C24XX | |
729 | select S3C_GPIO_CFG_S3C64XX | |
730 | select S3C_DEV_NAND | |
731 | select USB_ARCH_HAS_OHCI | |
732 | select SAMSUNG_GPIOLIB_4BIT | |
20676c15 | 733 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 734 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
a08ab637 BD |
735 | help |
736 | Samsung S3C64XX series based systems | |
737 | ||
49b7a491 KK |
738 | config ARCH_S5P64X0 |
739 | bool "Samsung S5P6440 S5P6450" | |
c4ffccdd KK |
740 | select CPU_V6 |
741 | select GENERIC_GPIO | |
742 | select HAVE_CLK | |
d8b22d25 | 743 | select CLKDEV_LOOKUP |
0665ccc4 | 744 | select CLKSRC_MMIO |
c39d8d55 | 745 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
9e65bbf2 SK |
746 | select GENERIC_CLOCKEVENTS |
747 | select HAVE_SCHED_CLOCK | |
20676c15 | 748 | select HAVE_S3C2410_I2C if I2C |
754961a8 | 749 | select HAVE_S3C_RTC if RTC_CLASS |
c4ffccdd | 750 | help |
49b7a491 KK |
751 | Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, |
752 | SMDK6450. | |
c4ffccdd | 753 | |
acc84707 MS |
754 | config ARCH_S5PC100 |
755 | bool "Samsung S5PC100" | |
5a7652f2 BM |
756 | select GENERIC_GPIO |
757 | select HAVE_CLK | |
29e8eb0f | 758 | select CLKDEV_LOOKUP |
5a7652f2 | 759 | select CPU_V7 |
d6d502fa | 760 | select ARM_L1_CACHE_SHIFT_6 |
925c68cd | 761 | select ARCH_USES_GETTIMEOFFSET |
20676c15 | 762 | select HAVE_S3C2410_I2C if I2C |
754961a8 | 763 | select HAVE_S3C_RTC if RTC_CLASS |
c39d8d55 | 764 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
5a7652f2 | 765 | help |
acc84707 | 766 | Samsung S5PC100 series based systems |
5a7652f2 | 767 | |
170f4e42 KK |
768 | config ARCH_S5PV210 |
769 | bool "Samsung S5PV210/S5PC110" | |
770 | select CPU_V7 | |
eecb6a84 | 771 | select ARCH_SPARSEMEM_ENABLE |
0f75a96b | 772 | select ARCH_HAS_HOLES_MEMORYMODEL |
170f4e42 KK |
773 | select GENERIC_GPIO |
774 | select HAVE_CLK | |
b2a9dd46 | 775 | select CLKDEV_LOOKUP |
0665ccc4 | 776 | select CLKSRC_MMIO |
170f4e42 | 777 | select ARM_L1_CACHE_SHIFT_6 |
d8144aea | 778 | select ARCH_HAS_CPUFREQ |
9e65bbf2 SK |
779 | select GENERIC_CLOCKEVENTS |
780 | select HAVE_SCHED_CLOCK | |
20676c15 | 781 | select HAVE_S3C2410_I2C if I2C |
754961a8 | 782 | select HAVE_S3C_RTC if RTC_CLASS |
c39d8d55 | 783 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
170f4e42 KK |
784 | help |
785 | Samsung S5PV210/S5PC110 series based systems | |
786 | ||
10606aad KK |
787 | config ARCH_EXYNOS4 |
788 | bool "Samsung EXYNOS4" | |
cc0e72b8 | 789 | select CPU_V7 |
f567fa6f | 790 | select ARCH_SPARSEMEM_ENABLE |
0f75a96b | 791 | select ARCH_HAS_HOLES_MEMORYMODEL |
cc0e72b8 CY |
792 | select GENERIC_GPIO |
793 | select HAVE_CLK | |
badc4f2d | 794 | select CLKDEV_LOOKUP |
b333fb16 | 795 | select ARCH_HAS_CPUFREQ |
cc0e72b8 | 796 | select GENERIC_CLOCKEVENTS |
754961a8 | 797 | select HAVE_S3C_RTC if RTC_CLASS |
20676c15 | 798 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 799 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
cc0e72b8 | 800 | help |
10606aad | 801 | Samsung EXYNOS4 series based systems |
cc0e72b8 | 802 | |
1da177e4 LT |
803 | config ARCH_SHARK |
804 | bool "Shark" | |
c750815e | 805 | select CPU_SA110 |
f7e68bbf RK |
806 | select ISA |
807 | select ISA_DMA | |
3bca103a | 808 | select ZONE_DMA |
f7e68bbf | 809 | select PCI |
5cfc8ee0 | 810 | select ARCH_USES_GETTIMEOFFSET |
f999b8bd MM |
811 | help |
812 | Support for the StrongARM based Digital DNARD machine, also known | |
813 | as "Shark" (<http://www.shark-linux.de/shark.html>). | |
1da177e4 | 814 | |
83ef3338 HK |
815 | config ARCH_TCC_926 |
816 | bool "Telechips TCC ARM926-based systems" | |
234b6ced | 817 | select CLKSRC_MMIO |
83ef3338 HK |
818 | select CPU_ARM926T |
819 | select HAVE_CLK | |
6d803ba7 | 820 | select CLKDEV_LOOKUP |
83ef3338 HK |
821 | select GENERIC_CLOCKEVENTS |
822 | help | |
823 | Support for Telechips TCC ARM926-based systems. | |
824 | ||
d98aac75 LW |
825 | config ARCH_U300 |
826 | bool "ST-Ericsson U300 Series" | |
827 | depends on MMU | |
234b6ced | 828 | select CLKSRC_MMIO |
d98aac75 | 829 | select CPU_ARM926T |
5c21b7ca | 830 | select HAVE_SCHED_CLOCK |
bc581770 | 831 | select HAVE_TCM |
d98aac75 LW |
832 | select ARM_AMBA |
833 | select ARM_VIC | |
d98aac75 | 834 | select GENERIC_CLOCKEVENTS |
6d803ba7 | 835 | select CLKDEV_LOOKUP |
aa3831cf | 836 | select HAVE_MACH_CLKDEV |
d98aac75 LW |
837 | select GENERIC_GPIO |
838 | help | |
839 | Support for ST-Ericsson U300 series mobile platforms. | |
840 | ||
ccf50e23 RK |
841 | config ARCH_U8500 |
842 | bool "ST-Ericsson U8500 Series" | |
843 | select CPU_V7 | |
844 | select ARM_AMBA | |
ccf50e23 | 845 | select GENERIC_CLOCKEVENTS |
6d803ba7 | 846 | select CLKDEV_LOOKUP |
94bdc0e2 | 847 | select ARCH_REQUIRE_GPIOLIB |
7c1a70e9 | 848 | select ARCH_HAS_CPUFREQ |
ccf50e23 RK |
849 | help |
850 | Support for ST-Ericsson's Ux500 architecture | |
851 | ||
852 | config ARCH_NOMADIK | |
853 | bool "STMicroelectronics Nomadik" | |
854 | select ARM_AMBA | |
855 | select ARM_VIC | |
856 | select CPU_ARM926T | |
6d803ba7 | 857 | select CLKDEV_LOOKUP |
ccf50e23 | 858 | select GENERIC_CLOCKEVENTS |
ccf50e23 RK |
859 | select ARCH_REQUIRE_GPIOLIB |
860 | help | |
861 | Support for the Nomadik platform by ST-Ericsson | |
862 | ||
7c6337e2 KH |
863 | config ARCH_DAVINCI |
864 | bool "TI DaVinci" | |
7c6337e2 | 865 | select GENERIC_CLOCKEVENTS |
dce1115b | 866 | select ARCH_REQUIRE_GPIOLIB |
3bca103a | 867 | select ZONE_DMA |
9232fcc9 | 868 | select HAVE_IDE |
6d803ba7 | 869 | select CLKDEV_LOOKUP |
20e9969b | 870 | select GENERIC_ALLOCATOR |
dc7ad3b3 | 871 | select GENERIC_IRQ_CHIP |
ae88e05a | 872 | select ARCH_HAS_HOLES_MEMORYMODEL |
7c6337e2 KH |
873 | help |
874 | Support for TI's DaVinci platform. | |
875 | ||
3b938be6 RK |
876 | config ARCH_OMAP |
877 | bool "TI OMAP" | |
9483a578 | 878 | select HAVE_CLK |
7444a72e | 879 | select ARCH_REQUIRE_GPIOLIB |
89c52ed4 | 880 | select ARCH_HAS_CPUFREQ |
354a183f | 881 | select CLKSRC_MMIO |
06cad098 | 882 | select GENERIC_CLOCKEVENTS |
dc548fbb | 883 | select HAVE_SCHED_CLOCK |
9af915da | 884 | select ARCH_HAS_HOLES_MEMORYMODEL |
3b938be6 | 885 | help |
6e457bb0 | 886 | Support for TI's OMAP platform (OMAP1/2/3/4). |
3b938be6 | 887 | |
cee37e50 | 888 | config PLAT_SPEAR |
889 | bool "ST SPEAr" | |
890 | select ARM_AMBA | |
891 | select ARCH_REQUIRE_GPIOLIB | |
6d803ba7 | 892 | select CLKDEV_LOOKUP |
d6e15d78 | 893 | select CLKSRC_MMIO |
cee37e50 | 894 | select GENERIC_CLOCKEVENTS |
cee37e50 | 895 | select HAVE_CLK |
896 | help | |
897 | Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). | |
898 | ||
21f47fbc AC |
899 | config ARCH_VT8500 |
900 | bool "VIA/WonderMedia 85xx" | |
901 | select CPU_ARM926T | |
902 | select GENERIC_GPIO | |
903 | select ARCH_HAS_CPUFREQ | |
904 | select GENERIC_CLOCKEVENTS | |
905 | select ARCH_REQUIRE_GPIOLIB | |
906 | select HAVE_PWM | |
907 | help | |
908 | Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. | |
02c981c0 | 909 | |
b85a3ef4 JL |
910 | config ARCH_ZYNQ |
911 | bool "Xilinx Zynq ARM Cortex A9 Platform" | |
02c981c0 BD |
912 | select CPU_V7 |
913 | select GENERIC_TIME | |
02c981c0 BD |
914 | select GENERIC_CLOCKEVENTS |
915 | select CLKDEV_LOOKUP | |
b85a3ef4 JL |
916 | select ARM_GIC |
917 | select ARM_AMBA | |
918 | select ICST | |
02c981c0 | 919 | select USE_OF |
02c981c0 | 920 | help |
b85a3ef4 | 921 | Support for Xilinx Zynq ARM Cortex A9 Platform |
1da177e4 LT |
922 | endchoice |
923 | ||
ccf50e23 RK |
924 | # |
925 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
926 | # Kconfigs may be included either alphabetically (according to the | |
927 | # plat- suffix) or along side the corresponding mach-* source. | |
928 | # | |
95b8f20f RK |
929 | source "arch/arm/mach-at91/Kconfig" |
930 | ||
931 | source "arch/arm/mach-bcmring/Kconfig" | |
932 | ||
1da177e4 LT |
933 | source "arch/arm/mach-clps711x/Kconfig" |
934 | ||
d94f944e AV |
935 | source "arch/arm/mach-cns3xxx/Kconfig" |
936 | ||
95b8f20f RK |
937 | source "arch/arm/mach-davinci/Kconfig" |
938 | ||
939 | source "arch/arm/mach-dove/Kconfig" | |
940 | ||
e7736d47 LB |
941 | source "arch/arm/mach-ep93xx/Kconfig" |
942 | ||
1da177e4 LT |
943 | source "arch/arm/mach-footbridge/Kconfig" |
944 | ||
59d3a193 PZ |
945 | source "arch/arm/mach-gemini/Kconfig" |
946 | ||
95b8f20f RK |
947 | source "arch/arm/mach-h720x/Kconfig" |
948 | ||
1da177e4 LT |
949 | source "arch/arm/mach-integrator/Kconfig" |
950 | ||
3f7e5815 LB |
951 | source "arch/arm/mach-iop32x/Kconfig" |
952 | ||
953 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 954 | |
285f5fa7 DW |
955 | source "arch/arm/mach-iop13xx/Kconfig" |
956 | ||
1da177e4 LT |
957 | source "arch/arm/mach-ixp4xx/Kconfig" |
958 | ||
959 | source "arch/arm/mach-ixp2000/Kconfig" | |
960 | ||
c4713074 LB |
961 | source "arch/arm/mach-ixp23xx/Kconfig" |
962 | ||
95b8f20f RK |
963 | source "arch/arm/mach-kirkwood/Kconfig" |
964 | ||
965 | source "arch/arm/mach-ks8695/Kconfig" | |
966 | ||
40805949 KW |
967 | source "arch/arm/mach-lpc32xx/Kconfig" |
968 | ||
95b8f20f RK |
969 | source "arch/arm/mach-msm/Kconfig" |
970 | ||
794d15b2 SS |
971 | source "arch/arm/mach-mv78xx0/Kconfig" |
972 | ||
95b8f20f | 973 | source "arch/arm/plat-mxc/Kconfig" |
1da177e4 | 974 | |
1d3f33d5 SG |
975 | source "arch/arm/mach-mxs/Kconfig" |
976 | ||
95b8f20f | 977 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 978 | |
95b8f20f RK |
979 | source "arch/arm/mach-nomadik/Kconfig" |
980 | source "arch/arm/plat-nomadik/Kconfig" | |
981 | ||
186f93ea | 982 | source "arch/arm/mach-nuc93x/Kconfig" |
1da177e4 | 983 | |
d48af15e TL |
984 | source "arch/arm/plat-omap/Kconfig" |
985 | ||
986 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 987 | |
1dbae815 TL |
988 | source "arch/arm/mach-omap2/Kconfig" |
989 | ||
9dd0b194 | 990 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 991 | |
95b8f20f RK |
992 | source "arch/arm/mach-pxa/Kconfig" |
993 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 994 | |
95b8f20f RK |
995 | source "arch/arm/mach-mmp/Kconfig" |
996 | ||
997 | source "arch/arm/mach-realview/Kconfig" | |
998 | ||
999 | source "arch/arm/mach-sa1100/Kconfig" | |
edabd38e | 1000 | |
cf383678 | 1001 | source "arch/arm/plat-samsung/Kconfig" |
a21765a7 | 1002 | source "arch/arm/plat-s3c24xx/Kconfig" |
c4ffccdd | 1003 | source "arch/arm/plat-s5p/Kconfig" |
a21765a7 | 1004 | |
cee37e50 | 1005 | source "arch/arm/plat-spear/Kconfig" |
a21765a7 | 1006 | |
83ef3338 HK |
1007 | source "arch/arm/plat-tcc/Kconfig" |
1008 | ||
a21765a7 | 1009 | if ARCH_S3C2410 |
1da177e4 | 1010 | source "arch/arm/mach-s3c2410/Kconfig" |
a21765a7 | 1011 | source "arch/arm/mach-s3c2412/Kconfig" |
f1290a49 | 1012 | source "arch/arm/mach-s3c2416/Kconfig" |
a21765a7 | 1013 | source "arch/arm/mach-s3c2440/Kconfig" |
e4d06e39 | 1014 | source "arch/arm/mach-s3c2443/Kconfig" |
a21765a7 | 1015 | endif |
1da177e4 | 1016 | |
a08ab637 | 1017 | if ARCH_S3C64XX |
431107ea | 1018 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 BD |
1019 | endif |
1020 | ||
49b7a491 | 1021 | source "arch/arm/mach-s5p64x0/Kconfig" |
c4ffccdd | 1022 | |
5a7652f2 | 1023 | source "arch/arm/mach-s5pc100/Kconfig" |
5a7652f2 | 1024 | |
170f4e42 KK |
1025 | source "arch/arm/mach-s5pv210/Kconfig" |
1026 | ||
10606aad | 1027 | source "arch/arm/mach-exynos4/Kconfig" |
cc0e72b8 | 1028 | |
882d01f9 | 1029 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 1030 | |
c5f80065 EG |
1031 | source "arch/arm/mach-tegra/Kconfig" |
1032 | ||
95b8f20f | 1033 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 1034 | |
95b8f20f | 1035 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
1036 | |
1037 | source "arch/arm/mach-versatile/Kconfig" | |
1038 | ||
ceade897 | 1039 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 1040 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 1041 | |
21f47fbc AC |
1042 | source "arch/arm/mach-vt8500/Kconfig" |
1043 | ||
7ec80ddf | 1044 | source "arch/arm/mach-w90x900/Kconfig" |
1045 | ||
1da177e4 LT |
1046 | # Definitions to make life easier |
1047 | config ARCH_ACORN | |
1048 | bool | |
1049 | ||
7ae1f7ec LB |
1050 | config PLAT_IOP |
1051 | bool | |
469d3044 | 1052 | select GENERIC_CLOCKEVENTS |
08f26b1e | 1053 | select HAVE_SCHED_CLOCK |
7ae1f7ec | 1054 | |
69b02f6a LB |
1055 | config PLAT_ORION |
1056 | bool | |
bfe45e0b | 1057 | select CLKSRC_MMIO |
dc7ad3b3 | 1058 | select GENERIC_IRQ_CHIP |
f06a1624 | 1059 | select HAVE_SCHED_CLOCK |
69b02f6a | 1060 | |
bd5ce433 EM |
1061 | config PLAT_PXA |
1062 | bool | |
1063 | ||
f4b8b319 RK |
1064 | config PLAT_VERSATILE |
1065 | bool | |
1066 | ||
e3887714 RK |
1067 | config ARM_TIMER_SP804 |
1068 | bool | |
bfe45e0b | 1069 | select CLKSRC_MMIO |
e3887714 | 1070 | |
1da177e4 LT |
1071 | source arch/arm/mm/Kconfig |
1072 | ||
afe4b25e LB |
1073 | config IWMMXT |
1074 | bool "Enable iWMMXt support" | |
ef6c8445 HZ |
1075 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 |
1076 | default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP | |
afe4b25e LB |
1077 | help |
1078 | Enable support for iWMMXt context switching at run time if | |
1079 | running on a CPU that supports it. | |
1080 | ||
1da177e4 LT |
1081 | # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER |
1082 | config XSCALE_PMU | |
1083 | bool | |
1084 | depends on CPU_XSCALE && !XSCALE_PMU_TIMER | |
1085 | default y | |
1086 | ||
0f4f0672 | 1087 | config CPU_HAS_PMU |
e399b1a4 | 1088 | depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ |
8954bb0d | 1089 | (!ARCH_OMAP3 || OMAP3_EMU) |
0f4f0672 JI |
1090 | default y |
1091 | bool | |
1092 | ||
52108641 | 1093 | config MULTI_IRQ_HANDLER |
1094 | bool | |
1095 | help | |
1096 | Allow each machine to specify it's own IRQ handler at run time. | |
1097 | ||
3b93e7b0 HC |
1098 | if !MMU |
1099 | source "arch/arm/Kconfig-nommu" | |
1100 | endif | |
1101 | ||
9cba3ccc CM |
1102 | config ARM_ERRATA_411920 |
1103 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 1104 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
1105 | help |
1106 | Invalidation of the Instruction Cache operation can | |
1107 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1108 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1109 | recommended workaround. | |
1110 | ||
7ce236fc CM |
1111 | config ARM_ERRATA_430973 |
1112 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1113 | depends on CPU_V7 | |
1114 | help | |
1115 | This option enables the workaround for the 430973 Cortex-A8 | |
1116 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1117 | interworking branch is replaced with another code sequence at the | |
1118 | same virtual address, whether due to self-modifying code or virtual | |
1119 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1120 | stale interworking branch prediction. This results in Cortex-A8 | |
1121 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1122 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1123 | and also flushes the branch target cache at every context switch. | |
1124 | Note that setting specific bits in the ACTLR register may not be | |
1125 | available in non-secure mode. | |
1126 | ||
855c551f CM |
1127 | config ARM_ERRATA_458693 |
1128 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1129 | depends on CPU_V7 | |
1130 | help | |
1131 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1132 | erratum. For very specific sequences of memory operations, it is | |
1133 | possible for a hazard condition intended for a cache line to instead | |
1134 | be incorrectly associated with a different cache line. This false | |
1135 | hazard might then cause a processor deadlock. The workaround enables | |
1136 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1137 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1138 | register may not be available in non-secure mode. | |
1139 | ||
0516e464 CM |
1140 | config ARM_ERRATA_460075 |
1141 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1142 | depends on CPU_V7 | |
1143 | help | |
1144 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1145 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1146 | situation in which recent store transactions to the L2 cache are lost | |
1147 | and overwritten with stale memory contents from external memory. The | |
1148 | workaround disables the write-allocate mode for the L2 cache via the | |
1149 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1150 | may not be available in non-secure mode. | |
1151 | ||
9f05027c WD |
1152 | config ARM_ERRATA_742230 |
1153 | bool "ARM errata: DMB operation may be faulty" | |
1154 | depends on CPU_V7 && SMP | |
1155 | help | |
1156 | This option enables the workaround for the 742230 Cortex-A9 | |
1157 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1158 | between two write operations may not ensure the correct visibility | |
1159 | ordering of the two writes. This workaround sets a specific bit in | |
1160 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1161 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1162 | the two writes. | |
1163 | ||
a672e99b WD |
1164 | config ARM_ERRATA_742231 |
1165 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1166 | depends on CPU_V7 && SMP | |
1167 | help | |
1168 | This option enables the workaround for the 742231 Cortex-A9 | |
1169 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1170 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1171 | accessing some data located in the same cache line, may get corrupted | |
1172 | data due to bad handling of the address hazard when the line gets | |
1173 | replaced from one of the CPUs at the same time as another CPU is | |
1174 | accessing it. This workaround sets specific bits in the diagnostic | |
1175 | register of the Cortex-A9 which reduces the linefill issuing | |
1176 | capabilities of the processor. | |
1177 | ||
9e65582a SS |
1178 | config PL310_ERRATA_588369 |
1179 | bool "Clean & Invalidate maintenance operations do not invalidate clean lines" | |
2839e06c | 1180 | depends on CACHE_L2X0 |
9e65582a SS |
1181 | help |
1182 | The PL310 L2 cache controller implements three types of Clean & | |
1183 | Invalidate maintenance operations: by Physical Address | |
1184 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
1185 | They are architecturally defined to behave as the execution of a | |
1186 | clean operation followed immediately by an invalidate operation, | |
1187 | both performing to the same memory location. This functionality | |
1188 | is not correctly implemented in PL310 as clean lines are not | |
2839e06c | 1189 | invalidated as a result of these operations. |
cdf357f1 WD |
1190 | |
1191 | config ARM_ERRATA_720789 | |
1192 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
1193 | depends on CPU_V7 && SMP | |
1194 | help | |
1195 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1196 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1197 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1198 | As a consequence of this erratum, some TLB entries which should be | |
1199 | invalidated are not, resulting in an incoherency in the system page | |
1200 | tables. The workaround changes the TLB flushing routines to invalidate | |
1201 | entries regardless of the ASID. | |
475d92fc | 1202 | |
1f0090a1 RK |
1203 | config PL310_ERRATA_727915 |
1204 | bool "Background Clean & Invalidate by Way operation can cause data corruption" | |
1205 | depends on CACHE_L2X0 | |
1206 | help | |
1207 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
1208 | operation (offset 0x7FC). This operation runs in background so that | |
1209 | PL310 can handle normal accesses while it is in progress. Under very | |
1210 | rare circumstances, due to this erratum, write data can be lost when | |
1211 | PL310 treats a cacheable write transaction during a Clean & | |
1212 | Invalidate by Way operation. | |
1213 | ||
475d92fc WD |
1214 | config ARM_ERRATA_743622 |
1215 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1216 | depends on CPU_V7 | |
1217 | help | |
1218 | This option enables the workaround for the 743622 Cortex-A9 | |
1219 | (r2p0..r2p2) erratum. Under very rare conditions, a faulty | |
1220 | optimisation in the Cortex-A9 Store Buffer may lead to data | |
1221 | corruption. This workaround sets a specific bit in the diagnostic | |
1222 | register of the Cortex-A9 which disables the Store Buffer | |
1223 | optimisation, preventing the defect from occurring. This has no | |
1224 | visible impact on the overall performance or power consumption of the | |
1225 | processor. | |
1226 | ||
9a27c27c WD |
1227 | config ARM_ERRATA_751472 |
1228 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
1229 | depends on CPU_V7 && SMP | |
1230 | help | |
1231 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1232 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1233 | completion of a following broadcasted operation if the second | |
1234 | operation is received by a CPU before the ICIALLUIS has completed, | |
1235 | potentially leading to corrupted entries in the cache or TLB. | |
1236 | ||
885028e4 SK |
1237 | config ARM_ERRATA_753970 |
1238 | bool "ARM errata: cache sync operation may be faulty" | |
1239 | depends on CACHE_PL310 | |
1240 | help | |
1241 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
1242 | ||
1243 | Under some condition the effect of cache sync operation on | |
1244 | the store buffer still remains when the operation completes. | |
1245 | This means that the store buffer is always asked to drain and | |
1246 | this prevents it from merging any further writes. The workaround | |
1247 | is to replace the normal offset of cache sync operation (0x730) | |
1248 | by another offset targeting an unmapped PL310 register 0x740. | |
1249 | This has the same effect as the cache sync operation: store buffer | |
1250 | drain and waiting for all buffers empty. | |
1251 | ||
fcbdc5fe WD |
1252 | config ARM_ERRATA_754322 |
1253 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1254 | depends on CPU_V7 | |
1255 | help | |
1256 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1257 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1258 | which starts prior to an ASID switch but completes afterwards. This | |
1259 | can populate the micro-TLB with a stale entry which may be hit with | |
1260 | the new ASID. This workaround places two dsb instructions in the mm | |
1261 | switching code so that no page table walks can cross the ASID switch. | |
1262 | ||
5dab26af WD |
1263 | config ARM_ERRATA_754327 |
1264 | bool "ARM errata: no automatic Store Buffer drain" | |
1265 | depends on CPU_V7 && SMP | |
1266 | help | |
1267 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1268 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1269 | mechanism and therefore a livelock may occur if an external agent | |
1270 | continuously polls a memory location waiting to observe an update. | |
1271 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1272 | written polling loops from denying visibility of updates to memory. | |
1273 | ||
145e10e1 CM |
1274 | config ARM_ERRATA_364296 |
1275 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
1276 | depends on CPU_V6 && !SMP | |
1277 | help | |
1278 | This options enables the workaround for the 364296 ARM1136 | |
1279 | r0p2 erratum (possible cache data corruption with | |
1280 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1281 | the auxiliary control register and the FI bit in the control | |
1282 | register, thus disabling hit-under-miss without putting the | |
1283 | processor into full low interrupt latency mode. ARM11MPCore | |
1284 | is not affected. | |
1285 | ||
1da177e4 LT |
1286 | endmenu |
1287 | ||
1288 | source "arch/arm/common/Kconfig" | |
1289 | ||
1da177e4 LT |
1290 | menu "Bus support" |
1291 | ||
1292 | config ARM_AMBA | |
1293 | bool | |
1294 | ||
1295 | config ISA | |
1296 | bool | |
1da177e4 LT |
1297 | help |
1298 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1299 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1300 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1301 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1302 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1303 | ||
065909b9 | 1304 | # Select ISA DMA controller support |
1da177e4 LT |
1305 | config ISA_DMA |
1306 | bool | |
065909b9 | 1307 | select ISA_DMA_API |
1da177e4 | 1308 | |
065909b9 | 1309 | # Select ISA DMA interface |
5cae841b AV |
1310 | config ISA_DMA_API |
1311 | bool | |
5cae841b | 1312 | |
1da177e4 | 1313 | config PCI |
0b05da72 | 1314 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1315 | help |
1316 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1317 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1318 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1319 | VESA. If you have PCI, say Y, otherwise N. | |
1320 | ||
52882173 AV |
1321 | config PCI_DOMAINS |
1322 | bool | |
1323 | depends on PCI | |
1324 | ||
b080ac8a MRJ |
1325 | config PCI_NANOENGINE |
1326 | bool "BSE nanoEngine PCI support" | |
1327 | depends on SA1100_NANOENGINE | |
1328 | help | |
1329 | Enable PCI on the BSE nanoEngine board. | |
1330 | ||
36e23590 MW |
1331 | config PCI_SYSCALL |
1332 | def_bool PCI | |
1333 | ||
1da177e4 LT |
1334 | # Select the host bridge type |
1335 | config PCI_HOST_VIA82C505 | |
1336 | bool | |
1337 | depends on PCI && ARCH_SHARK | |
1338 | default y | |
1339 | ||
a0113a99 MR |
1340 | config PCI_HOST_ITE8152 |
1341 | bool | |
1342 | depends on PCI && MACH_ARMCORE | |
1343 | default y | |
1344 | select DMABOUNCE | |
1345 | ||
1da177e4 LT |
1346 | source "drivers/pci/Kconfig" |
1347 | ||
1348 | source "drivers/pcmcia/Kconfig" | |
1349 | ||
1350 | endmenu | |
1351 | ||
1352 | menu "Kernel Features" | |
1353 | ||
0567a0c0 KH |
1354 | source "kernel/time/Kconfig" |
1355 | ||
1da177e4 | 1356 | config SMP |
bb2d8130 | 1357 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1358 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1359 | depends on GENERIC_CLOCKEVENTS |
971acb9b | 1360 | depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ |
89c3dedf | 1361 | MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ |
10606aad | 1362 | ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ |
e9d728f5 | 1363 | ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE |
f6dd9fa5 | 1364 | select USE_GENERIC_SMP_HELPERS |
89c3dedf | 1365 | select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP |
1da177e4 LT |
1366 | help |
1367 | This enables support for systems with more than one CPU. If you have | |
1368 | a system with only one CPU, like most personal computers, say N. If | |
1369 | you have a system with more than one CPU, say Y. | |
1370 | ||
1371 | If you say N here, the kernel will run on single and multiprocessor | |
1372 | machines, but will use only one CPU of a multiprocessor machine. If | |
1373 | you say Y here, the kernel will run on many, but not all, single | |
1374 | processor machines. On a single processor machine, the kernel will | |
1375 | run faster if you say N here. | |
1376 | ||
395cf969 | 1377 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1378 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1379 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1380 | |
1381 | If you don't know what to do here, say N. | |
1382 | ||
f00ec48f RK |
1383 | config SMP_ON_UP |
1384 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
1385 | depends on EXPERIMENTAL | |
4d2692a7 | 1386 | depends on SMP && !XIP_KERNEL |
f00ec48f RK |
1387 | default y |
1388 | help | |
1389 | SMP kernels contain instructions which fail on non-SMP processors. | |
1390 | Enabling this option allows the kernel to modify itself to make | |
1391 | these instructions safe. Disabling it allows about 1K of space | |
1392 | savings. | |
1393 | ||
1394 | If you don't know what to do here, say Y. | |
1395 | ||
a8cbcd92 RK |
1396 | config HAVE_ARM_SCU |
1397 | bool | |
a8cbcd92 RK |
1398 | help |
1399 | This option enables support for the ARM system coherency unit | |
1400 | ||
f32f4ce2 RK |
1401 | config HAVE_ARM_TWD |
1402 | bool | |
1403 | depends on SMP | |
15095bb0 | 1404 | select TICK_ONESHOT |
f32f4ce2 RK |
1405 | help |
1406 | This options enables support for the ARM timer and watchdog unit | |
1407 | ||
8d5796d2 LB |
1408 | choice |
1409 | prompt "Memory split" | |
1410 | default VMSPLIT_3G | |
1411 | help | |
1412 | Select the desired split between kernel and user memory. | |
1413 | ||
1414 | If you are not absolutely sure what you are doing, leave this | |
1415 | option alone! | |
1416 | ||
1417 | config VMSPLIT_3G | |
1418 | bool "3G/1G user/kernel split" | |
1419 | config VMSPLIT_2G | |
1420 | bool "2G/2G user/kernel split" | |
1421 | config VMSPLIT_1G | |
1422 | bool "1G/3G user/kernel split" | |
1423 | endchoice | |
1424 | ||
1425 | config PAGE_OFFSET | |
1426 | hex | |
1427 | default 0x40000000 if VMSPLIT_1G | |
1428 | default 0x80000000 if VMSPLIT_2G | |
1429 | default 0xC0000000 | |
1430 | ||
1da177e4 LT |
1431 | config NR_CPUS |
1432 | int "Maximum number of CPUs (2-32)" | |
1433 | range 2 32 | |
1434 | depends on SMP | |
1435 | default "4" | |
1436 | ||
a054a811 RK |
1437 | config HOTPLUG_CPU |
1438 | bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" | |
1439 | depends on SMP && HOTPLUG && EXPERIMENTAL | |
1440 | help | |
1441 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1442 | can be controlled through /sys/devices/system/cpu. | |
1443 | ||
37ee16ae RK |
1444 | config LOCAL_TIMERS |
1445 | bool "Use local timer interrupts" | |
971acb9b | 1446 | depends on SMP |
37ee16ae | 1447 | default y |
30d8bead | 1448 | select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) |
37ee16ae RK |
1449 | help |
1450 | Enable support for local timers on SMP platforms, rather then the | |
1451 | legacy IPI broadcast method. Local timers allows the system | |
1452 | accounting to be spread across the timer interval, preventing a | |
1453 | "thundering herd" at every timer tick. | |
1454 | ||
d45a398f | 1455 | source kernel/Kconfig.preempt |
1da177e4 | 1456 | |
f8065813 RK |
1457 | config HZ |
1458 | int | |
49b7a491 | 1459 | default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ |
a73ddc61 | 1460 | ARCH_S5PV210 || ARCH_EXYNOS4 |
bfe65704 | 1461 | default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER |
5248c657 | 1462 | default AT91_TIMER_HZ if ARCH_AT91 |
5da3e714 | 1463 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE |
f8065813 RK |
1464 | default 100 |
1465 | ||
16c79651 | 1466 | config THUMB2_KERNEL |
4a50bfe3 | 1467 | bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" |
e399b1a4 | 1468 | depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL |
16c79651 CM |
1469 | select AEABI |
1470 | select ARM_ASM_UNIFIED | |
1471 | help | |
1472 | By enabling this option, the kernel will be compiled in | |
1473 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1474 | ARM-Thumb syntax is needed. | |
1475 | ||
1476 | If unsure, say N. | |
1477 | ||
6f685c5c DM |
1478 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1479 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1480 | depends on THUMB2_KERNEL && MODULES | |
1481 | default y | |
1482 | help | |
1483 | Various binutils versions can resolve Thumb-2 branches to | |
1484 | locally-defined, preemptible global symbols as short-range "b.n" | |
1485 | branch instructions. | |
1486 | ||
1487 | This is a problem, because there's no guarantee the final | |
1488 | destination of the symbol, or any candidate locations for a | |
1489 | trampoline, are within range of the branch. For this reason, the | |
1490 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1491 | relocation in modules at all, and it makes little sense to add | |
1492 | support. | |
1493 | ||
1494 | The symptom is that the kernel fails with an "unsupported | |
1495 | relocation" error when loading some modules. | |
1496 | ||
1497 | Until fixed tools are available, passing | |
1498 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1499 | code which hits this problem, at the cost of a bit of extra runtime | |
1500 | stack usage in some cases. | |
1501 | ||
1502 | The problem is described in more detail at: | |
1503 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1504 | ||
1505 | Only Thumb-2 kernels are affected. | |
1506 | ||
1507 | Unless you are sure your tools don't have this problem, say Y. | |
1508 | ||
0becb088 CM |
1509 | config ARM_ASM_UNIFIED |
1510 | bool | |
1511 | ||
704bdda0 NP |
1512 | config AEABI |
1513 | bool "Use the ARM EABI to compile the kernel" | |
1514 | help | |
1515 | This option allows for the kernel to be compiled using the latest | |
1516 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1517 | space environment that is also compiled with EABI. | |
1518 | ||
1519 | Since there are major incompatibilities between the legacy ABI and | |
1520 | EABI, especially with regard to structure member alignment, this | |
1521 | option also changes the kernel syscall calling convention to | |
1522 | disambiguate both ABIs and allow for backward compatibility support | |
1523 | (selected with CONFIG_OABI_COMPAT). | |
1524 | ||
1525 | To use this you need GCC version 4.0.0 or later. | |
1526 | ||
6c90c872 | 1527 | config OABI_COMPAT |
a73a3ff1 | 1528 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
9bc433a1 | 1529 | depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL |
6c90c872 NP |
1530 | default y |
1531 | help | |
1532 | This option preserves the old syscall interface along with the | |
1533 | new (ARM EABI) one. It also provides a compatibility layer to | |
1534 | intercept syscalls that have structure arguments which layout | |
1535 | in memory differs between the legacy ABI and the new ARM EABI | |
1536 | (only for non "thumb" binaries). This option adds a tiny | |
1537 | overhead to all syscalls and produces a slightly larger kernel. | |
1538 | If you know you'll be using only pure EABI user space then you | |
1539 | can say N here. If this option is not selected and you attempt | |
1540 | to execute a legacy ABI binary then the result will be | |
1541 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
1542 | at all). If in doubt say Y. | |
1543 | ||
eb33575c | 1544 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1545 | bool |
e80d6a24 | 1546 | |
05944d74 RK |
1547 | config ARCH_SPARSEMEM_ENABLE |
1548 | bool | |
1549 | ||
07a2f737 RK |
1550 | config ARCH_SPARSEMEM_DEFAULT |
1551 | def_bool ARCH_SPARSEMEM_ENABLE | |
1552 | ||
05944d74 | 1553 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1554 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1555 | |
7b7bf499 WD |
1556 | config HAVE_ARCH_PFN_VALID |
1557 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1558 | ||
053a96ca | 1559 | config HIGHMEM |
e8db89a2 RK |
1560 | bool "High Memory Support" |
1561 | depends on MMU | |
053a96ca NP |
1562 | help |
1563 | The address space of ARM processors is only 4 Gigabytes large | |
1564 | and it has to accommodate user address space, kernel address | |
1565 | space as well as some memory mapped IO. That means that, if you | |
1566 | have a large amount of physical memory and/or IO, not all of the | |
1567 | memory can be "permanently mapped" by the kernel. The physical | |
1568 | memory that is not permanently mapped is called "high memory". | |
1569 | ||
1570 | Depending on the selected kernel/user memory split, minimum | |
1571 | vmalloc space and actual amount of RAM, you may not need this | |
1572 | option which should result in a slightly faster kernel. | |
1573 | ||
1574 | If unsure, say n. | |
1575 | ||
65cec8e3 RK |
1576 | config HIGHPTE |
1577 | bool "Allocate 2nd-level pagetables from highmem" | |
1578 | depends on HIGHMEM | |
65cec8e3 | 1579 | |
1b8873a0 JI |
1580 | config HW_PERF_EVENTS |
1581 | bool "Enable hardware performance counter support for perf events" | |
fe166148 | 1582 | depends on PERF_EVENTS && CPU_HAS_PMU |
1b8873a0 JI |
1583 | default y |
1584 | help | |
1585 | Enable hardware performance counter support for perf events. If | |
1586 | disabled, perf events will use software events only. | |
1587 | ||
3f22ab27 DH |
1588 | source "mm/Kconfig" |
1589 | ||
c1b2d970 MD |
1590 | config FORCE_MAX_ZONEORDER |
1591 | int "Maximum zone order" if ARCH_SHMOBILE | |
1592 | range 11 64 if ARCH_SHMOBILE | |
1593 | default "9" if SA1111 | |
1594 | default "11" | |
1595 | help | |
1596 | The kernel memory allocator divides physically contiguous memory | |
1597 | blocks into "zones", where each zone is a power of two number of | |
1598 | pages. This option selects the largest power of two that the kernel | |
1599 | keeps in the memory allocator. If you need to allocate very large | |
1600 | blocks of physically contiguous memory, then you may need to | |
1601 | increase this value. | |
1602 | ||
1603 | This config option is actually maximum order plus one. For example, | |
1604 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1605 | ||
1da177e4 LT |
1606 | config LEDS |
1607 | bool "Timer and CPU usage LEDs" | |
e055d5bf | 1608 | depends on ARCH_CDB89712 || ARCH_EBSA110 || \ |
8c8fdbc9 | 1609 | ARCH_EBSA285 || ARCH_INTEGRATOR || \ |
1da177e4 LT |
1610 | ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ |
1611 | ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ | |
73a59c1c | 1612 | ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ |
25329671 | 1613 | ARCH_AT91 || ARCH_DAVINCI || \ |
ff3042fb | 1614 | ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW |
1da177e4 LT |
1615 | help |
1616 | If you say Y here, the LEDs on your machine will be used | |
1617 | to provide useful information about your current system status. | |
1618 | ||
1619 | If you are compiling a kernel for a NetWinder or EBSA-285, you will | |
1620 | be able to select which LEDs are active using the options below. If | |
1621 | you are compiling a kernel for the EBSA-110 or the LART however, the | |
1622 | red LED will simply flash regularly to indicate that the system is | |
1623 | still functional. It is safe to say Y here if you have a CATS | |
1624 | system, but the driver will do nothing. | |
1625 | ||
1626 | config LEDS_TIMER | |
1627 | bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ | |
eebdf7d7 DB |
1628 | OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ |
1629 | || MACH_OMAP_PERSEUS2 | |
1da177e4 | 1630 | depends on LEDS |
0567a0c0 | 1631 | depends on !GENERIC_CLOCKEVENTS |
1da177e4 LT |
1632 | default y if ARCH_EBSA110 |
1633 | help | |
1634 | If you say Y here, one of the system LEDs (the green one on the | |
1635 | NetWinder, the amber one on the EBSA285, or the red one on the LART) | |
1636 | will flash regularly to indicate that the system is still | |
1637 | operational. This is mainly useful to kernel hackers who are | |
1638 | debugging unstable kernels. | |
1639 | ||
1640 | The LART uses the same LED for both Timer LED and CPU usage LED | |
1641 | functions. You may choose to use both, but the Timer LED function | |
1642 | will overrule the CPU usage LED. | |
1643 | ||
1644 | config LEDS_CPU | |
1645 | bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ | |
eebdf7d7 DB |
1646 | !ARCH_OMAP) \ |
1647 | || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ | |
1648 | || MACH_OMAP_PERSEUS2 | |
1da177e4 LT |
1649 | depends on LEDS |
1650 | help | |
1651 | If you say Y here, the red LED will be used to give a good real | |
1652 | time indication of CPU usage, by lighting whenever the idle task | |
1653 | is not currently executing. | |
1654 | ||
1655 | The LART uses the same LED for both Timer LED and CPU usage LED | |
1656 | functions. You may choose to use both, but the Timer LED function | |
1657 | will overrule the CPU usage LED. | |
1658 | ||
1659 | config ALIGNMENT_TRAP | |
1660 | bool | |
f12d0d7c | 1661 | depends on CPU_CP15_MMU |
1da177e4 | 1662 | default y if !ARCH_EBSA110 |
e119bfff | 1663 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1664 | help |
84eb8d06 | 1665 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1666 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1667 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1668 | fetch/store instructions will be emulated in software if you say | |
1669 | here, which has a severe performance impact. This is necessary for | |
1670 | correct operation of some network protocols. With an IP-only | |
1671 | configuration it is safe to say N, otherwise say Y. | |
1672 | ||
39ec58f3 LB |
1673 | config UACCESS_WITH_MEMCPY |
1674 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" | |
1675 | depends on MMU && EXPERIMENTAL | |
1676 | default y if CPU_FEROCEON | |
1677 | help | |
1678 | Implement faster copy_to_user and clear_user methods for CPU | |
1679 | cores where a 8-word STM instruction give significantly higher | |
1680 | memory write throughput than a sequence of individual 32bit stores. | |
1681 | ||
1682 | A possible side effect is a slight increase in scheduling latency | |
1683 | between threads sharing the same address space if they invoke | |
1684 | such copy operations with large buffers. | |
1685 | ||
1686 | However, if the CPU data cache is using a write-allocate mode, | |
1687 | this option is unlikely to provide any performance gain. | |
1688 | ||
70c70d97 NP |
1689 | config SECCOMP |
1690 | bool | |
1691 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1692 | ---help--- | |
1693 | This kernel feature is useful for number crunching applications | |
1694 | that may need to compute untrusted bytecode during their | |
1695 | execution. By using pipes or other transports made available to | |
1696 | the process as file descriptors supporting the read/write | |
1697 | syscalls, it's possible to isolate those applications in | |
1698 | their own address space using seccomp. Once seccomp is | |
1699 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1700 | and the task is only allowed to execute a few safe syscalls | |
1701 | defined by each seccomp mode. | |
1702 | ||
c743f380 NP |
1703 | config CC_STACKPROTECTOR |
1704 | bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" | |
4a50bfe3 | 1705 | depends on EXPERIMENTAL |
c743f380 NP |
1706 | help |
1707 | This option turns on the -fstack-protector GCC feature. This | |
1708 | feature puts, at the beginning of functions, a canary value on | |
1709 | the stack just before the return address, and validates | |
1710 | the value just before actually returning. Stack based buffer | |
1711 | overflows (that need to overwrite this return address) now also | |
1712 | overwrite the canary, which gets detected and the attack is then | |
1713 | neutralized via a kernel panic. | |
1714 | This feature requires gcc version 4.2 or above. | |
1715 | ||
73a65b3f UKK |
1716 | config DEPRECATED_PARAM_STRUCT |
1717 | bool "Provide old way to pass kernel parameters" | |
1718 | help | |
1719 | This was deprecated in 2001 and announced to live on for 5 years. | |
1720 | Some old boot loaders still use this way. | |
1721 | ||
1da177e4 LT |
1722 | endmenu |
1723 | ||
1724 | menu "Boot options" | |
1725 | ||
9eb8f674 GL |
1726 | config USE_OF |
1727 | bool "Flattened Device Tree support" | |
1728 | select OF | |
1729 | select OF_EARLY_FLATTREE | |
08a543ad | 1730 | select IRQ_DOMAIN |
9eb8f674 GL |
1731 | help |
1732 | Include support for flattened device tree machine descriptions. | |
1733 | ||
1da177e4 LT |
1734 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1735 | # TEXT and BSS so we preserve their values in the config files. | |
1736 | config ZBOOT_ROM_TEXT | |
1737 | hex "Compressed ROM boot loader base address" | |
1738 | default "0" | |
1739 | help | |
1740 | The physical address at which the ROM-able zImage is to be | |
1741 | placed in the target. Platforms which normally make use of | |
1742 | ROM-able zImage formats normally set this to a suitable | |
1743 | value in their defconfig file. | |
1744 | ||
1745 | If ZBOOT_ROM is not enabled, this has no effect. | |
1746 | ||
1747 | config ZBOOT_ROM_BSS | |
1748 | hex "Compressed ROM boot loader BSS address" | |
1749 | default "0" | |
1750 | help | |
f8c440b2 DF |
1751 | The base address of an area of read/write memory in the target |
1752 | for the ROM-able zImage which must be available while the | |
1753 | decompressor is running. It must be large enough to hold the | |
1754 | entire decompressed kernel plus an additional 128 KiB. | |
1755 | Platforms which normally make use of ROM-able zImage formats | |
1756 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1757 | |
1758 | If ZBOOT_ROM is not enabled, this has no effect. | |
1759 | ||
1760 | config ZBOOT_ROM | |
1761 | bool "Compressed boot loader in ROM/flash" | |
1762 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
1763 | help | |
1764 | Say Y here if you intend to execute your compressed kernel image | |
1765 | (zImage) directly from ROM or flash. If unsure, say N. | |
1766 | ||
090ab3ff SH |
1767 | choice |
1768 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
1769 | depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL | |
1770 | default ZBOOT_ROM_NONE | |
1771 | help | |
1772 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
1773 | With this enabled it is possible to write the the ROM-able zImage | |
1774 | kernel image to an MMC or SD card and boot the kernel straight | |
1775 | from the reset vector. At reset the processor Mask ROM will load | |
1776 | the first part of the the ROM-able zImage which in turn loads the | |
1777 | rest the kernel image to RAM. | |
1778 | ||
1779 | config ZBOOT_ROM_NONE | |
1780 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1781 | help | |
1782 | Do not load image from SD or MMC | |
1783 | ||
f45b1149 SH |
1784 | config ZBOOT_ROM_MMCIF |
1785 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
f45b1149 | 1786 | help |
090ab3ff SH |
1787 | Load image from MMCIF hardware block. |
1788 | ||
1789 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
1790 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
1791 | help | |
1792 | Load image from SDHI hardware block | |
1793 | ||
1794 | endchoice | |
f45b1149 | 1795 | |
1da177e4 LT |
1796 | config CMDLINE |
1797 | string "Default kernel command string" | |
1798 | default "" | |
1799 | help | |
1800 | On some architectures (EBSA110 and CATS), there is currently no way | |
1801 | for the boot loader to pass arguments to the kernel. For these | |
1802 | architectures, you should supply some command-line options at build | |
1803 | time by entering them here. As a minimum, you should specify the | |
1804 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1805 | ||
4394c124 VB |
1806 | choice |
1807 | prompt "Kernel command line type" if CMDLINE != "" | |
1808 | default CMDLINE_FROM_BOOTLOADER | |
1809 | ||
1810 | config CMDLINE_FROM_BOOTLOADER | |
1811 | bool "Use bootloader kernel arguments if available" | |
1812 | help | |
1813 | Uses the command-line options passed by the boot loader. If | |
1814 | the boot loader doesn't provide any, the default kernel command | |
1815 | string provided in CMDLINE will be used. | |
1816 | ||
1817 | config CMDLINE_EXTEND | |
1818 | bool "Extend bootloader kernel arguments" | |
1819 | help | |
1820 | The command-line arguments provided by the boot loader will be | |
1821 | appended to the default kernel command string. | |
1822 | ||
92d2040d AH |
1823 | config CMDLINE_FORCE |
1824 | bool "Always use the default kernel command string" | |
92d2040d AH |
1825 | help |
1826 | Always use the default kernel command string, even if the boot | |
1827 | loader passes other arguments to the kernel. | |
1828 | This is useful if you cannot or don't want to change the | |
1829 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1830 | endchoice |
92d2040d | 1831 | |
1da177e4 LT |
1832 | config XIP_KERNEL |
1833 | bool "Kernel Execute-In-Place from ROM" | |
1834 | depends on !ZBOOT_ROM | |
1835 | help | |
1836 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1837 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1838 | space since the text section of the kernel is not loaded from flash | |
1839 | to RAM. Read-write sections, such as the data section and stack, | |
1840 | are still copied to RAM. The XIP kernel is not compressed since | |
1841 | it has to run directly from flash, so it will take more space to | |
1842 | store it. The flash address used to link the kernel object files, | |
1843 | and for storing it, is configuration dependent. Therefore, if you | |
1844 | say Y here, you must know the proper physical address where to | |
1845 | store the kernel image depending on your own flash memory usage. | |
1846 | ||
1847 | Also note that the make target becomes "make xipImage" rather than | |
1848 | "make zImage" or "make Image". The final kernel binary to put in | |
1849 | ROM memory will be arch/arm/boot/xipImage. | |
1850 | ||
1851 | If unsure, say N. | |
1852 | ||
1853 | config XIP_PHYS_ADDR | |
1854 | hex "XIP Kernel Physical Location" | |
1855 | depends on XIP_KERNEL | |
1856 | default "0x00080000" | |
1857 | help | |
1858 | This is the physical address in your flash memory the kernel will | |
1859 | be linked for and stored to. This address is dependent on your | |
1860 | own flash usage. | |
1861 | ||
c587e4a6 RP |
1862 | config KEXEC |
1863 | bool "Kexec system call (EXPERIMENTAL)" | |
1864 | depends on EXPERIMENTAL | |
1865 | help | |
1866 | kexec is a system call that implements the ability to shutdown your | |
1867 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 1868 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
1869 | you can start any kernel with it, not just Linux. |
1870 | ||
1871 | It is an ongoing process to be certain the hardware in a machine | |
1872 | is properly shutdown, so do not be surprised if this code does not | |
1873 | initially work for you. It may help to enable device hotplugging | |
1874 | support. | |
1875 | ||
4cd9d6f7 RP |
1876 | config ATAGS_PROC |
1877 | bool "Export atags in procfs" | |
b98d7291 UL |
1878 | depends on KEXEC |
1879 | default y | |
4cd9d6f7 RP |
1880 | help |
1881 | Should the atags used to boot the kernel be exported in an "atags" | |
1882 | file in procfs. Useful with kexec. | |
1883 | ||
cb5d39b3 MW |
1884 | config CRASH_DUMP |
1885 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
1886 | depends on EXPERIMENTAL | |
1887 | help | |
1888 | Generate crash dump after being started by kexec. This should | |
1889 | be normally only set in special crash dump kernels which are | |
1890 | loaded in the main kernel with kexec-tools into a specially | |
1891 | reserved region and then later executed after a crash by | |
1892 | kdump/kexec. The crash dump kernel must be compiled to a | |
1893 | memory address not used by the main kernel | |
1894 | ||
1895 | For more details see Documentation/kdump/kdump.txt | |
1896 | ||
e69edc79 EM |
1897 | config AUTO_ZRELADDR |
1898 | bool "Auto calculation of the decompressed kernel image address" | |
1899 | depends on !ZBOOT_ROM && !ARCH_U300 | |
1900 | help | |
1901 | ZRELADDR is the physical address where the decompressed kernel | |
1902 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
1903 | will be determined at run-time by masking the current IP with | |
1904 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
1905 | from start of memory. | |
1906 | ||
1da177e4 LT |
1907 | endmenu |
1908 | ||
ac9d7efc | 1909 | menu "CPU Power Management" |
1da177e4 | 1910 | |
89c52ed4 | 1911 | if ARCH_HAS_CPUFREQ |
1da177e4 LT |
1912 | |
1913 | source "drivers/cpufreq/Kconfig" | |
1914 | ||
64f102b6 YS |
1915 | config CPU_FREQ_IMX |
1916 | tristate "CPUfreq driver for i.MX CPUs" | |
1917 | depends on ARCH_MXC && CPU_FREQ | |
1918 | help | |
1919 | This enables the CPUfreq driver for i.MX CPUs. | |
1920 | ||
1da177e4 LT |
1921 | config CPU_FREQ_SA1100 |
1922 | bool | |
1da177e4 LT |
1923 | |
1924 | config CPU_FREQ_SA1110 | |
1925 | bool | |
1da177e4 LT |
1926 | |
1927 | config CPU_FREQ_INTEGRATOR | |
1928 | tristate "CPUfreq driver for ARM Integrator CPUs" | |
1929 | depends on ARCH_INTEGRATOR && CPU_FREQ | |
1930 | default y | |
1931 | help | |
1932 | This enables the CPUfreq driver for ARM Integrator CPUs. | |
1933 | ||
1934 | For details, take a look at <file:Documentation/cpu-freq>. | |
1935 | ||
1936 | If in doubt, say Y. | |
1937 | ||
9e2697ff RK |
1938 | config CPU_FREQ_PXA |
1939 | bool | |
1940 | depends on CPU_FREQ && ARCH_PXA && PXA25x | |
1941 | default y | |
1942 | select CPU_FREQ_DEFAULT_GOV_USERSPACE | |
1943 | ||
9d56c02a BD |
1944 | config CPU_FREQ_S3C |
1945 | bool | |
1946 | help | |
1947 | Internal configuration node for common cpufreq on Samsung SoC | |
1948 | ||
1949 | config CPU_FREQ_S3C24XX | |
4a50bfe3 | 1950 | bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" |
9d56c02a BD |
1951 | depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL |
1952 | select CPU_FREQ_S3C | |
1953 | help | |
1954 | This enables the CPUfreq driver for the Samsung S3C24XX family | |
1955 | of CPUs. | |
1956 | ||
1957 | For details, take a look at <file:Documentation/cpu-freq>. | |
1958 | ||
1959 | If in doubt, say N. | |
1960 | ||
1961 | config CPU_FREQ_S3C24XX_PLL | |
4a50bfe3 | 1962 | bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" |
9d56c02a BD |
1963 | depends on CPU_FREQ_S3C24XX && EXPERIMENTAL |
1964 | help | |
1965 | Compile in support for changing the PLL frequency from the | |
1966 | S3C24XX series CPUfreq driver. The PLL takes time to settle | |
1967 | after a frequency change, so by default it is not enabled. | |
1968 | ||
1969 | This also means that the PLL tables for the selected CPU(s) will | |
1970 | be built which may increase the size of the kernel image. | |
1971 | ||
1972 | config CPU_FREQ_S3C24XX_DEBUG | |
1973 | bool "Debug CPUfreq Samsung driver core" | |
1974 | depends on CPU_FREQ_S3C24XX | |
1975 | help | |
1976 | Enable s3c_freq_dbg for the Samsung S3C CPUfreq core | |
1977 | ||
1978 | config CPU_FREQ_S3C24XX_IODEBUG | |
1979 | bool "Debug CPUfreq Samsung driver IO timing" | |
1980 | depends on CPU_FREQ_S3C24XX | |
1981 | help | |
1982 | Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core | |
1983 | ||
e6d197a6 BD |
1984 | config CPU_FREQ_S3C24XX_DEBUGFS |
1985 | bool "Export debugfs for CPUFreq" | |
1986 | depends on CPU_FREQ_S3C24XX && DEBUG_FS | |
1987 | help | |
1988 | Export status information via debugfs. | |
1989 | ||
1da177e4 LT |
1990 | endif |
1991 | ||
ac9d7efc RK |
1992 | source "drivers/cpuidle/Kconfig" |
1993 | ||
1994 | endmenu | |
1995 | ||
1da177e4 LT |
1996 | menu "Floating point emulation" |
1997 | ||
1998 | comment "At least one emulation must be selected" | |
1999 | ||
2000 | config FPE_NWFPE | |
2001 | bool "NWFPE math emulation" | |
593c252a | 2002 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2003 | ---help--- |
2004 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2005 | This is necessary to run most binaries. Linux does not currently | |
2006 | support floating point hardware so you need to say Y here even if | |
2007 | your machine has an FPA or floating point co-processor podule. | |
2008 | ||
2009 | You may say N here if you are going to load the Acorn FPEmulator | |
2010 | early in the bootup. | |
2011 | ||
2012 | config FPE_NWFPE_XP | |
2013 | bool "Support extended precision" | |
bedf142b | 2014 | depends on FPE_NWFPE |
1da177e4 LT |
2015 | help |
2016 | Say Y to include 80-bit support in the kernel floating-point | |
2017 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2018 | Note that gcc does not generate 80-bit operations by default, | |
2019 | so in most cases this option only enlarges the size of the | |
2020 | floating point emulator without any good reason. | |
2021 | ||
2022 | You almost surely want to say N here. | |
2023 | ||
2024 | config FPE_FASTFPE | |
2025 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
8993a44c | 2026 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL |
1da177e4 LT |
2027 | ---help--- |
2028 | Say Y here to include the FAST floating point emulator in the kernel. | |
2029 | This is an experimental much faster emulator which now also has full | |
2030 | precision for the mantissa. It does not support any exceptions. | |
2031 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2032 | ||
2033 | It should be sufficient for most programs. It may be not suitable | |
2034 | for scientific calculations, but you have to check this for yourself. | |
2035 | If you do not feel you need a faster FP emulation you should better | |
2036 | choose NWFPE. | |
2037 | ||
2038 | config VFP | |
2039 | bool "VFP-format floating point maths" | |
e399b1a4 | 2040 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2041 | help |
2042 | Say Y to include VFP support code in the kernel. This is needed | |
2043 | if your hardware includes a VFP unit. | |
2044 | ||
2045 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2046 | release notes and additional status information. | |
2047 | ||
2048 | Say N if your target does not have VFP hardware. | |
2049 | ||
25ebee02 CM |
2050 | config VFPv3 |
2051 | bool | |
2052 | depends on VFP | |
2053 | default y if CPU_V7 | |
2054 | ||
b5872db4 CM |
2055 | config NEON |
2056 | bool "Advanced SIMD (NEON) Extension support" | |
2057 | depends on VFPv3 && CPU_V7 | |
2058 | help | |
2059 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2060 | Extension. | |
2061 | ||
1da177e4 LT |
2062 | endmenu |
2063 | ||
2064 | menu "Userspace binary formats" | |
2065 | ||
2066 | source "fs/Kconfig.binfmt" | |
2067 | ||
2068 | config ARTHUR | |
2069 | tristate "RISC OS personality" | |
704bdda0 | 2070 | depends on !AEABI |
1da177e4 LT |
2071 | help |
2072 | Say Y here to include the kernel code necessary if you want to run | |
2073 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2074 | experimental; if this sounds frightening, say N and sleep in peace. | |
2075 | You can also say M here to compile this support as a module (which | |
2076 | will be called arthur). | |
2077 | ||
2078 | endmenu | |
2079 | ||
2080 | menu "Power management options" | |
2081 | ||
eceab4ac | 2082 | source "kernel/power/Kconfig" |
1da177e4 | 2083 | |
f4cb5700 | 2084 | config ARCH_SUSPEND_POSSIBLE |
586893eb | 2085 | depends on !ARCH_S5P64X0 && !ARCH_S5PC100 |
6a786182 RK |
2086 | depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ |
2087 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE | |
f4cb5700 JB |
2088 | def_bool y |
2089 | ||
1da177e4 LT |
2090 | endmenu |
2091 | ||
d5950b43 SR |
2092 | source "net/Kconfig" |
2093 | ||
ac25150f | 2094 | source "drivers/Kconfig" |
1da177e4 LT |
2095 | |
2096 | source "fs/Kconfig" | |
2097 | ||
1da177e4 LT |
2098 | source "arch/arm/Kconfig.debug" |
2099 | ||
2100 | source "security/Kconfig" | |
2101 | ||
2102 | source "crypto/Kconfig" | |
2103 | ||
2104 | source "lib/Kconfig" |