Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
b1b3f49c RK |
4 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE |
5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE | |
7563bbf8 | 6 | select ARCH_HAVE_CUSTOM_GPIO_H |
3d06770e | 7 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
b1b3f49c | 8 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 9 | select BUILDTIME_EXTABLE_SORT if MMU |
b1b3f49c | 10 | select CPU_PM if (SUSPEND || CPU_IDLE) |
39b175a0 | 11 | select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU |
4477ca45 | 12 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c RK |
13 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
14 | select GENERIC_IRQ_PROBE | |
15 | select GENERIC_IRQ_SHOW | |
b1b3f49c | 16 | select GENERIC_PCI_IOMAP |
38ff87f7 | 17 | select GENERIC_SCHED_CLOCK |
b1b3f49c | 18 | select GENERIC_SMP_IDLE_THREAD |
f7b861b7 | 19 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
20 | select GENERIC_STRNCPY_FROM_USER |
21 | select GENERIC_STRNLEN_USER | |
22 | select HARDIRQS_SW_RESEND | |
09f05d85 | 23 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL |
5cbad0eb | 24 | select HAVE_ARCH_KGDB |
4095ccc3 | 25 | select HAVE_ARCH_SECCOMP_FILTER |
0693bf68 | 26 | select HAVE_ARCH_TRACEHOOK |
b1b3f49c RK |
27 | select HAVE_BPF_JIT |
28 | select HAVE_C_RECORDMCOUNT | |
29 | select HAVE_DEBUG_KMEMLEAK | |
30 | select HAVE_DMA_API_DEBUG | |
31 | select HAVE_DMA_ATTRS | |
32 | select HAVE_DMA_CONTIGUOUS if MMU | |
80be7a7f | 33 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) |
b1b3f49c | 34 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 35 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 36 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
1fe53268 | 37 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
38 | select HAVE_GENERIC_HARDIRQS |
39 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) | |
40 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 41 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 42 | select HAVE_KERNEL_GZIP |
f9b493ac | 43 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 44 | select HAVE_KERNEL_LZMA |
b1b3f49c | 45 | select HAVE_KERNEL_LZO |
a7f464f3 | 46 | select HAVE_KERNEL_XZ |
b1b3f49c RK |
47 | select HAVE_KPROBES if !XIP_KERNEL |
48 | select HAVE_KRETPROBES if (HAVE_KPROBES) | |
49 | select HAVE_MEMBLOCK | |
50 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) | |
7ada189f | 51 | select HAVE_PERF_EVENTS |
e513f8bf | 52 | select HAVE_REGS_AND_STACK_ACCESS_API |
b1b3f49c | 53 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 54 | select HAVE_UID16 |
3d92a71a | 55 | select KTIME_SCALAR |
b1b3f49c RK |
56 | select PERF_USE_VMALLOC |
57 | select RTC_LIB | |
58 | select SYS_SUPPORTS_APM_EMULATION | |
786d35d4 DH |
59 | select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND |
60 | select MODULES_USE_ELF_REL | |
38a61b6b | 61 | select CLONE_BACKWARDS |
b68fec24 | 62 | select OLD_SIGSUSPEND3 |
50bcb7e4 | 63 | select OLD_SIGACTION |
b0088480 | 64 | select HAVE_CONTEXT_TRACKING |
1da177e4 LT |
65 | help |
66 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 67 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 68 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 69 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
70 | Europe. There is an ARM Linux project with a web page at |
71 | <http://www.arm.linux.org.uk/>. | |
72 | ||
74facffe RK |
73 | config ARM_HAS_SG_CHAIN |
74 | bool | |
75 | ||
4ce63fcd MS |
76 | config NEED_SG_DMA_LENGTH |
77 | bool | |
78 | ||
79 | config ARM_DMA_USE_IOMMU | |
4ce63fcd | 80 | bool |
b1b3f49c RK |
81 | select ARM_HAS_SG_CHAIN |
82 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 83 | |
60460abf SWK |
84 | if ARM_DMA_USE_IOMMU |
85 | ||
86 | config ARM_DMA_IOMMU_ALIGNMENT | |
87 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
88 | range 4 9 | |
89 | default 8 | |
90 | help | |
91 | DMA mapping framework by default aligns all buffers to the smallest | |
92 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
93 | size. This works well for buffers up to a few hundreds kilobytes, but | |
94 | for larger buffers it just a waste of address space. Drivers which has | |
95 | relatively small addressing window (like 64Mib) might run out of | |
96 | virtual space with just a few allocations. | |
97 | ||
98 | With this parameter you can specify the maximum PAGE_SIZE order for | |
99 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
100 | specified order. The order is expressed as a power of two multiplied | |
101 | by the PAGE_SIZE. | |
102 | ||
103 | endif | |
104 | ||
1a189b97 RK |
105 | config HAVE_PWM |
106 | bool | |
107 | ||
0b05da72 HUK |
108 | config MIGHT_HAVE_PCI |
109 | bool | |
110 | ||
75e7153a RB |
111 | config SYS_SUPPORTS_APM_EMULATION |
112 | bool | |
113 | ||
bc581770 LW |
114 | config HAVE_TCM |
115 | bool | |
116 | select GENERIC_ALLOCATOR | |
117 | ||
e119bfff RK |
118 | config HAVE_PROC_CPU |
119 | bool | |
120 | ||
5ea81769 AV |
121 | config NO_IOPORT |
122 | bool | |
5ea81769 | 123 | |
1da177e4 LT |
124 | config EISA |
125 | bool | |
126 | ---help--- | |
127 | The Extended Industry Standard Architecture (EISA) bus was | |
128 | developed as an open alternative to the IBM MicroChannel bus. | |
129 | ||
130 | The EISA bus provided some of the features of the IBM MicroChannel | |
131 | bus while maintaining backward compatibility with cards made for | |
132 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
133 | 1995 when it was made obsolete by the PCI bus. | |
134 | ||
135 | Say Y here if you are building a kernel for an EISA-based machine. | |
136 | ||
137 | Otherwise, say N. | |
138 | ||
139 | config SBUS | |
140 | bool | |
141 | ||
f16fb1ec RK |
142 | config STACKTRACE_SUPPORT |
143 | bool | |
144 | default y | |
145 | ||
f76e9154 NP |
146 | config HAVE_LATENCYTOP_SUPPORT |
147 | bool | |
148 | depends on !SMP | |
149 | default y | |
150 | ||
f16fb1ec RK |
151 | config LOCKDEP_SUPPORT |
152 | bool | |
153 | default y | |
154 | ||
7ad1bcb2 RK |
155 | config TRACE_IRQFLAGS_SUPPORT |
156 | bool | |
157 | default y | |
158 | ||
1da177e4 LT |
159 | config RWSEM_GENERIC_SPINLOCK |
160 | bool | |
161 | default y | |
162 | ||
163 | config RWSEM_XCHGADD_ALGORITHM | |
164 | bool | |
165 | ||
f0d1b0b3 DH |
166 | config ARCH_HAS_ILOG2_U32 |
167 | bool | |
f0d1b0b3 DH |
168 | |
169 | config ARCH_HAS_ILOG2_U64 | |
170 | bool | |
f0d1b0b3 | 171 | |
89c52ed4 BD |
172 | config ARCH_HAS_CPUFREQ |
173 | bool | |
174 | help | |
175 | Internal node to signify that the ARCH has CPUFREQ support | |
176 | and that the relevant menu configurations are displayed for | |
177 | it. | |
178 | ||
4a1b5733 EV |
179 | config ARCH_HAS_BANDGAP |
180 | bool | |
181 | ||
b89c3b16 AM |
182 | config GENERIC_HWEIGHT |
183 | bool | |
184 | default y | |
185 | ||
1da177e4 LT |
186 | config GENERIC_CALIBRATE_DELAY |
187 | bool | |
188 | default y | |
189 | ||
a08b6b79 Z |
190 | config ARCH_MAY_HAVE_PC_FDC |
191 | bool | |
192 | ||
5ac6da66 CL |
193 | config ZONE_DMA |
194 | bool | |
5ac6da66 | 195 | |
ccd7ab7f FT |
196 | config NEED_DMA_MAP_STATE |
197 | def_bool y | |
198 | ||
58af4a24 RH |
199 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
200 | bool | |
201 | ||
1da177e4 LT |
202 | config GENERIC_ISA_DMA |
203 | bool | |
204 | ||
1da177e4 LT |
205 | config FIQ |
206 | bool | |
207 | ||
13a5045d RH |
208 | config NEED_RET_TO_USER |
209 | bool | |
210 | ||
034d2f5a AV |
211 | config ARCH_MTD_XIP |
212 | bool | |
213 | ||
c760fc19 HC |
214 | config VECTORS_BASE |
215 | hex | |
6afd6fae | 216 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
217 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
218 | default 0x00000000 | |
219 | help | |
19accfd3 RK |
220 | The base address of exception vectors. This must be two pages |
221 | in size. | |
c760fc19 | 222 | |
dc21af99 | 223 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
224 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
225 | default y | |
b511d75d | 226 | depends on !XIP_KERNEL && MMU |
dc21af99 RK |
227 | depends on !ARCH_REALVIEW || !SPARSEMEM |
228 | help | |
111e9a5c RK |
229 | Patch phys-to-virt and virt-to-phys translation functions at |
230 | boot and module load time according to the position of the | |
231 | kernel in system memory. | |
dc21af99 | 232 | |
111e9a5c | 233 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 234 | of physical memory is at a 16MB boundary. |
dc21af99 | 235 | |
c1becedc RK |
236 | Only disable this option if you know that you do not require |
237 | this feature (eg, building a kernel for a single machine) and | |
238 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 239 | |
01464226 RH |
240 | config NEED_MACH_GPIO_H |
241 | bool | |
242 | help | |
243 | Select this when mach/gpio.h is required to provide special | |
244 | definitions for this platform. The need for mach/gpio.h should | |
245 | be avoided when possible. | |
246 | ||
c334bc15 RH |
247 | config NEED_MACH_IO_H |
248 | bool | |
249 | help | |
250 | Select this when mach/io.h is required to provide special | |
251 | definitions for this platform. The need for mach/io.h should | |
252 | be avoided when possible. | |
253 | ||
0cdc8b92 | 254 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
255 | bool |
256 | help | |
0cdc8b92 NP |
257 | Select this when mach/memory.h is required to provide special |
258 | definitions for this platform. The need for mach/memory.h should | |
259 | be avoided when possible. | |
dc21af99 | 260 | |
1b9f95f8 | 261 | config PHYS_OFFSET |
974c0724 | 262 | hex "Physical address of main memory" if MMU |
0cdc8b92 | 263 | depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H |
974c0724 | 264 | default DRAM_BASE if !MMU |
111e9a5c | 265 | help |
1b9f95f8 NP |
266 | Please provide the physical address corresponding to the |
267 | location of main memory in your system. | |
cada3c08 | 268 | |
87e040b6 SG |
269 | config GENERIC_BUG |
270 | def_bool y | |
271 | depends on BUG | |
272 | ||
1da177e4 LT |
273 | source "init/Kconfig" |
274 | ||
dc52ddc0 MH |
275 | source "kernel/Kconfig.freezer" |
276 | ||
1da177e4 LT |
277 | menu "System Type" |
278 | ||
3c427975 HC |
279 | config MMU |
280 | bool "MMU-based Paged Memory Management Support" | |
281 | default y | |
282 | help | |
283 | Select if you want MMU-based virtualised addressing space | |
284 | support by paged memory management. If unsure, say 'Y'. | |
285 | ||
ccf50e23 RK |
286 | # |
287 | # The "ARM system type" choice list is ordered alphabetically by option | |
288 | # text. Please add new entries in the option alphabetic order. | |
289 | # | |
1da177e4 LT |
290 | choice |
291 | prompt "ARM system type" | |
1420b22b AB |
292 | default ARCH_VERSATILE if !MMU |
293 | default ARCH_MULTIPLATFORM if MMU | |
1da177e4 | 294 | |
387798b3 RH |
295 | config ARCH_MULTIPLATFORM |
296 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 297 | depends on MMU |
387798b3 RH |
298 | select ARM_PATCH_PHYS_VIRT |
299 | select AUTO_ZRELADDR | |
66314223 | 300 | select COMMON_CLK |
387798b3 | 301 | select MULTI_IRQ_HANDLER |
66314223 DN |
302 | select SPARSE_IRQ |
303 | select USE_OF | |
66314223 | 304 | |
4af6fee1 DS |
305 | config ARCH_INTEGRATOR |
306 | bool "ARM Ltd. Integrator family" | |
89c52ed4 | 307 | select ARCH_HAS_CPUFREQ |
b1b3f49c | 308 | select ARM_AMBA |
a613163d | 309 | select COMMON_CLK |
f9a6aa43 | 310 | select COMMON_CLK_VERSATILE |
b1b3f49c | 311 | select GENERIC_CLOCKEVENTS |
9904f793 | 312 | select HAVE_TCM |
c5a0adb5 | 313 | select ICST |
b1b3f49c RK |
314 | select MULTI_IRQ_HANDLER |
315 | select NEED_MACH_MEMORY_H | |
f4b8b319 | 316 | select PLAT_VERSATILE |
695436e3 | 317 | select SPARSE_IRQ |
2389d501 | 318 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
319 | help |
320 | Support for ARM's Integrator platform. | |
321 | ||
322 | config ARCH_REALVIEW | |
323 | bool "ARM Ltd. RealView family" | |
b1b3f49c | 324 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 325 | select ARM_AMBA |
b1b3f49c | 326 | select ARM_TIMER_SP804 |
f9a6aa43 LW |
327 | select COMMON_CLK |
328 | select COMMON_CLK_VERSATILE | |
ae30ceac | 329 | select GENERIC_CLOCKEVENTS |
b56ba8aa | 330 | select GPIO_PL061 if GPIOLIB |
b1b3f49c | 331 | select ICST |
0cdc8b92 | 332 | select NEED_MACH_MEMORY_H |
b1b3f49c RK |
333 | select PLAT_VERSATILE |
334 | select PLAT_VERSATILE_CLCD | |
4af6fee1 DS |
335 | help |
336 | This enables support for ARM Ltd RealView boards. | |
337 | ||
338 | config ARCH_VERSATILE | |
339 | bool "ARM Ltd. Versatile family" | |
b1b3f49c | 340 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 341 | select ARM_AMBA |
b1b3f49c | 342 | select ARM_TIMER_SP804 |
4af6fee1 | 343 | select ARM_VIC |
6d803ba7 | 344 | select CLKDEV_LOOKUP |
b1b3f49c | 345 | select GENERIC_CLOCKEVENTS |
aa3831cf | 346 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 347 | select ICST |
f4b8b319 | 348 | select PLAT_VERSATILE |
3414ba8c | 349 | select PLAT_VERSATILE_CLCD |
b1b3f49c | 350 | select PLAT_VERSATILE_CLOCK |
2389d501 | 351 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
352 | help |
353 | This enables support for ARM Ltd Versatile board. | |
354 | ||
8fc5ffa0 AV |
355 | config ARCH_AT91 |
356 | bool "Atmel AT91" | |
f373e8c0 | 357 | select ARCH_REQUIRE_GPIOLIB |
bd602995 | 358 | select CLKDEV_LOOKUP |
b1b3f49c | 359 | select HAVE_CLK |
e261501d | 360 | select IRQ_DOMAIN |
01464226 | 361 | select NEED_MACH_GPIO_H |
1ac02d79 | 362 | select NEED_MACH_IO_H if PCCARD |
6732ae5c JCPV |
363 | select PINCTRL |
364 | select PINCTRL_AT91 if USE_OF | |
4af6fee1 | 365 | help |
929e994f NF |
366 | This enables support for systems based on Atmel |
367 | AT91RM9200 and AT91SAM9* processors. | |
4af6fee1 | 368 | |
93e22567 RK |
369 | config ARCH_CLPS711X |
370 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" | |
a3b8d4a5 | 371 | select ARCH_REQUIRE_GPIOLIB |
ea7d1bc9 | 372 | select AUTO_ZRELADDR |
93e22567 | 373 | select CLKDEV_LOOKUP |
c99f72ad | 374 | select CLKSRC_MMIO |
93e22567 RK |
375 | select COMMON_CLK |
376 | select CPU_ARM720T | |
4a8355c4 | 377 | select GENERIC_CLOCKEVENTS |
6597619f | 378 | select MFD_SYSCON |
99f04c8f | 379 | select MULTI_IRQ_HANDLER |
0d8be81c | 380 | select SPARSE_IRQ |
93e22567 RK |
381 | help |
382 | Support for Cirrus Logic 711x/721x/731x based boards. | |
383 | ||
788c9700 RK |
384 | config ARCH_GEMINI |
385 | bool "Cortina Systems Gemini" | |
788c9700 | 386 | select ARCH_REQUIRE_GPIOLIB |
5cfc8ee0 | 387 | select ARCH_USES_GETTIMEOFFSET |
662146b1 | 388 | select NEED_MACH_GPIO_H |
b1b3f49c | 389 | select CPU_FA526 |
788c9700 RK |
390 | help |
391 | Support for the Cortina Systems Gemini family SoCs | |
392 | ||
1da177e4 LT |
393 | config ARCH_EBSA110 |
394 | bool "EBSA-110" | |
b1b3f49c | 395 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 396 | select CPU_SA110 |
f7e68bbf | 397 | select ISA |
c334bc15 | 398 | select NEED_MACH_IO_H |
0cdc8b92 | 399 | select NEED_MACH_MEMORY_H |
b1b3f49c | 400 | select NO_IOPORT |
1da177e4 LT |
401 | help |
402 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 403 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
404 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
405 | parallel port. | |
406 | ||
e7736d47 LB |
407 | config ARCH_EP93XX |
408 | bool "EP93xx-based" | |
b1b3f49c RK |
409 | select ARCH_HAS_HOLES_MEMORYMODEL |
410 | select ARCH_REQUIRE_GPIOLIB | |
411 | select ARCH_USES_GETTIMEOFFSET | |
e7736d47 LB |
412 | select ARM_AMBA |
413 | select ARM_VIC | |
6d803ba7 | 414 | select CLKDEV_LOOKUP |
b1b3f49c | 415 | select CPU_ARM920T |
5725aeae | 416 | select NEED_MACH_MEMORY_H |
e7736d47 LB |
417 | help |
418 | This enables support for the Cirrus EP93xx series of CPUs. | |
419 | ||
1da177e4 LT |
420 | config ARCH_FOOTBRIDGE |
421 | bool "FootBridge" | |
c750815e | 422 | select CPU_SA110 |
1da177e4 | 423 | select FOOTBRIDGE |
4e8d7637 | 424 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 425 | select HAVE_IDE |
8ef6e620 | 426 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 427 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
428 | help |
429 | Support for systems based on the DC21285 companion chip | |
430 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 431 | |
4af6fee1 DS |
432 | config ARCH_NETX |
433 | bool "Hilscher NetX based" | |
b1b3f49c | 434 | select ARM_VIC |
234b6ced | 435 | select CLKSRC_MMIO |
c750815e | 436 | select CPU_ARM926T |
2fcfe6b8 | 437 | select GENERIC_CLOCKEVENTS |
f999b8bd | 438 | help |
4af6fee1 DS |
439 | This enables support for systems based on the Hilscher NetX Soc |
440 | ||
3b938be6 RK |
441 | config ARCH_IOP13XX |
442 | bool "IOP13xx-based" | |
443 | depends on MMU | |
3b938be6 | 444 | select ARCH_SUPPORTS_MSI |
b1b3f49c | 445 | select CPU_XSC3 |
0cdc8b92 | 446 | select NEED_MACH_MEMORY_H |
13a5045d | 447 | select NEED_RET_TO_USER |
b1b3f49c RK |
448 | select PCI |
449 | select PLAT_IOP | |
450 | select VMSPLIT_1G | |
3b938be6 RK |
451 | help |
452 | Support for Intel's IOP13XX (XScale) family of processors. | |
453 | ||
3f7e5815 LB |
454 | config ARCH_IOP32X |
455 | bool "IOP32x-based" | |
a4f7e763 | 456 | depends on MMU |
b1b3f49c | 457 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 458 | select CPU_XSCALE |
01464226 | 459 | select NEED_MACH_GPIO_H |
13a5045d | 460 | select NEED_RET_TO_USER |
f7e68bbf | 461 | select PCI |
b1b3f49c | 462 | select PLAT_IOP |
f999b8bd | 463 | help |
3f7e5815 LB |
464 | Support for Intel's 80219 and IOP32X (XScale) family of |
465 | processors. | |
466 | ||
467 | config ARCH_IOP33X | |
468 | bool "IOP33x-based" | |
469 | depends on MMU | |
b1b3f49c | 470 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 471 | select CPU_XSCALE |
01464226 | 472 | select NEED_MACH_GPIO_H |
13a5045d | 473 | select NEED_RET_TO_USER |
3f7e5815 | 474 | select PCI |
b1b3f49c | 475 | select PLAT_IOP |
3f7e5815 LB |
476 | help |
477 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 478 | |
3b938be6 RK |
479 | config ARCH_IXP4XX |
480 | bool "IXP4xx-based" | |
a4f7e763 | 481 | depends on MMU |
58af4a24 | 482 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
b1b3f49c | 483 | select ARCH_REQUIRE_GPIOLIB |
234b6ced | 484 | select CLKSRC_MMIO |
c750815e | 485 | select CPU_XSCALE |
b1b3f49c | 486 | select DMABOUNCE if PCI |
3b938be6 | 487 | select GENERIC_CLOCKEVENTS |
0b05da72 | 488 | select MIGHT_HAVE_PCI |
c334bc15 | 489 | select NEED_MACH_IO_H |
9296d94d FF |
490 | select USB_EHCI_BIG_ENDIAN_MMIO |
491 | select USB_EHCI_BIG_ENDIAN_DESC | |
c4713074 | 492 | help |
3b938be6 | 493 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 494 | |
edabd38e SB |
495 | config ARCH_DOVE |
496 | bool "Marvell Dove" | |
edabd38e | 497 | select ARCH_REQUIRE_GPIOLIB |
756b2531 | 498 | select CPU_PJ4 |
edabd38e | 499 | select GENERIC_CLOCKEVENTS |
0f81bd43 | 500 | select MIGHT_HAVE_PCI |
9139acd1 SH |
501 | select PINCTRL |
502 | select PINCTRL_DOVE | |
abcda1dc | 503 | select PLAT_ORION_LEGACY |
0f81bd43 | 504 | select USB_ARCH_HAS_EHCI |
7d554902 | 505 | select MVEBU_MBUS |
edabd38e SB |
506 | help |
507 | Support for the Marvell Dove SoC 88AP510 | |
508 | ||
651c74c7 SB |
509 | config ARCH_KIRKWOOD |
510 | bool "Marvell Kirkwood" | |
0e2ee0c0 | 511 | select ARCH_HAS_CPUFREQ |
a8865655 | 512 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 513 | select CPU_FEROCEON |
651c74c7 | 514 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 515 | select PCI |
1dc831bf | 516 | select PCI_QUIRKS |
f9e75922 AL |
517 | select PINCTRL |
518 | select PINCTRL_KIRKWOOD | |
abcda1dc | 519 | select PLAT_ORION_LEGACY |
5cc0673a | 520 | select MVEBU_MBUS |
651c74c7 SB |
521 | help |
522 | Support for the following Marvell Kirkwood series SoCs: | |
523 | 88F6180, 88F6192 and 88F6281. | |
524 | ||
794d15b2 SS |
525 | config ARCH_MV78XX0 |
526 | bool "Marvell MV78xx0" | |
a8865655 | 527 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 528 | select CPU_FEROCEON |
794d15b2 | 529 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 530 | select PCI |
abcda1dc | 531 | select PLAT_ORION_LEGACY |
95b80e0a | 532 | select MVEBU_MBUS |
794d15b2 SS |
533 | help |
534 | Support for the following Marvell MV78xx0 series SoCs: | |
535 | MV781x0, MV782x0. | |
536 | ||
9dd0b194 | 537 | config ARCH_ORION5X |
585cf175 TP |
538 | bool "Marvell Orion" |
539 | depends on MMU | |
a8865655 | 540 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 541 | select CPU_FEROCEON |
51cbff1d | 542 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 543 | select PCI |
abcda1dc | 544 | select PLAT_ORION_LEGACY |
5d1190ea | 545 | select MVEBU_MBUS |
585cf175 | 546 | help |
9dd0b194 | 547 | Support for the following Marvell Orion 5x series SoCs: |
d2b2a6bb | 548 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
d323ade1 | 549 | Orion-2 (5281), Orion-1-90 (6183). |
585cf175 | 550 | |
788c9700 | 551 | config ARCH_MMP |
2f7e8fae | 552 | bool "Marvell PXA168/910/MMP2" |
788c9700 | 553 | depends on MMU |
788c9700 | 554 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 555 | select CLKDEV_LOOKUP |
b1b3f49c | 556 | select GENERIC_ALLOCATOR |
788c9700 | 557 | select GENERIC_CLOCKEVENTS |
157d2644 | 558 | select GPIO_PXA |
c24b3114 | 559 | select IRQ_DOMAIN |
b1b3f49c | 560 | select NEED_MACH_GPIO_H |
7c8f86a4 | 561 | select PINCTRL |
788c9700 | 562 | select PLAT_PXA |
0bd86961 | 563 | select SPARSE_IRQ |
788c9700 | 564 | help |
2f7e8fae | 565 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. |
788c9700 RK |
566 | |
567 | config ARCH_KS8695 | |
568 | bool "Micrel/Kendin KS8695" | |
98830bc9 | 569 | select ARCH_REQUIRE_GPIOLIB |
c7e783d6 | 570 | select CLKSRC_MMIO |
b1b3f49c | 571 | select CPU_ARM922T |
c7e783d6 | 572 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 573 | select NEED_MACH_MEMORY_H |
788c9700 RK |
574 | help |
575 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
576 | System-on-Chip devices. | |
577 | ||
788c9700 RK |
578 | config ARCH_W90X900 |
579 | bool "Nuvoton W90X900 CPU" | |
c52d3d68 | 580 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 581 | select CLKDEV_LOOKUP |
6fa5d5f7 | 582 | select CLKSRC_MMIO |
b1b3f49c | 583 | select CPU_ARM926T |
58b5369e | 584 | select GENERIC_CLOCKEVENTS |
788c9700 | 585 | help |
a8bc4ead | 586 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
587 | At present, the w90x900 has been renamed nuc900, regarding | |
588 | the ARM series product line, you can login the following | |
589 | link address to know more. | |
590 | ||
591 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
592 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 593 | |
93e22567 RK |
594 | config ARCH_LPC32XX |
595 | bool "NXP LPC32XX" | |
596 | select ARCH_REQUIRE_GPIOLIB | |
597 | select ARM_AMBA | |
598 | select CLKDEV_LOOKUP | |
599 | select CLKSRC_MMIO | |
600 | select CPU_ARM926T | |
601 | select GENERIC_CLOCKEVENTS | |
602 | select HAVE_IDE | |
603 | select HAVE_PWM | |
604 | select USB_ARCH_HAS_OHCI | |
605 | select USE_OF | |
606 | help | |
607 | Support for the NXP LPC32XX family of processors | |
608 | ||
1da177e4 | 609 | config ARCH_PXA |
2c8086a5 | 610 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 611 | depends on MMU |
89c52ed4 | 612 | select ARCH_HAS_CPUFREQ |
b1b3f49c RK |
613 | select ARCH_MTD_XIP |
614 | select ARCH_REQUIRE_GPIOLIB | |
615 | select ARM_CPU_SUSPEND if PM | |
616 | select AUTO_ZRELADDR | |
6d803ba7 | 617 | select CLKDEV_LOOKUP |
234b6ced | 618 | select CLKSRC_MMIO |
981d0f39 | 619 | select GENERIC_CLOCKEVENTS |
157d2644 | 620 | select GPIO_PXA |
d0ee9f40 | 621 | select HAVE_IDE |
b1b3f49c | 622 | select MULTI_IRQ_HANDLER |
01464226 | 623 | select NEED_MACH_GPIO_H |
b1b3f49c RK |
624 | select PLAT_PXA |
625 | select SPARSE_IRQ | |
f999b8bd | 626 | help |
2c8086a5 | 627 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 | 628 | |
788c9700 RK |
629 | config ARCH_MSM |
630 | bool "Qualcomm MSM" | |
923a081c | 631 | select ARCH_REQUIRE_GPIOLIB |
bd32344a | 632 | select CLKDEV_LOOKUP |
8cc7f533 | 633 | select COMMON_CLK |
b1b3f49c | 634 | select GENERIC_CLOCKEVENTS |
49cbe786 | 635 | help |
4b53eb4f DW |
636 | Support for Qualcomm MSM/QSD based systems. This runs on the |
637 | apps processor of the MSM/QSD and depends on a shared memory | |
638 | interface to the modem processor which runs the baseband | |
639 | stack and controls some vital subsystems | |
640 | (clock and power control, etc). | |
49cbe786 | 641 | |
c793c1b0 | 642 | config ARCH_SHMOBILE |
6d72ad35 | 643 | bool "Renesas SH-Mobile / R-Mobile" |
69469995 | 644 | select ARM_PATCH_PHYS_VIRT |
5e93c6b4 | 645 | select CLKDEV_LOOKUP |
b1b3f49c | 646 | select GENERIC_CLOCKEVENTS |
4c3ffffd SB |
647 | select HAVE_ARM_SCU if SMP |
648 | select HAVE_ARM_TWD if LOCAL_TIMERS | |
b1b3f49c | 649 | select HAVE_CLK |
aa3831cf | 650 | select HAVE_MACH_CLKDEV |
3b55658a | 651 | select HAVE_SMP |
ce5ea9f3 | 652 | select MIGHT_HAVE_CACHE_L2X0 |
60f1435c | 653 | select MULTI_IRQ_HANDLER |
b1b3f49c | 654 | select NO_IOPORT |
2cd3c927 | 655 | select PINCTRL |
b1b3f49c RK |
656 | select PM_GENERIC_DOMAINS if PM |
657 | select SPARSE_IRQ | |
c793c1b0 | 658 | help |
6d72ad35 | 659 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms. |
c793c1b0 | 660 | |
1da177e4 LT |
661 | config ARCH_RPC |
662 | bool "RiscPC" | |
663 | select ARCH_ACORN | |
a08b6b79 | 664 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 665 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 666 | select ARCH_USES_GETTIMEOFFSET |
b1b3f49c | 667 | select FIQ |
d0ee9f40 | 668 | select HAVE_IDE |
b1b3f49c RK |
669 | select HAVE_PATA_PLATFORM |
670 | select ISA_DMA_API | |
c334bc15 | 671 | select NEED_MACH_IO_H |
0cdc8b92 | 672 | select NEED_MACH_MEMORY_H |
b1b3f49c | 673 | select NO_IOPORT |
b4811bac | 674 | select VIRT_TO_BUS |
1da177e4 LT |
675 | help |
676 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
677 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
678 | ||
679 | config ARCH_SA1100 | |
680 | bool "SA1100-based" | |
89c52ed4 | 681 | select ARCH_HAS_CPUFREQ |
b1b3f49c RK |
682 | select ARCH_MTD_XIP |
683 | select ARCH_REQUIRE_GPIOLIB | |
684 | select ARCH_SPARSEMEM_ENABLE | |
685 | select CLKDEV_LOOKUP | |
686 | select CLKSRC_MMIO | |
1937f5b9 | 687 | select CPU_FREQ |
b1b3f49c | 688 | select CPU_SA1100 |
3e238be2 | 689 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 690 | select HAVE_IDE |
b1b3f49c | 691 | select ISA |
01464226 | 692 | select NEED_MACH_GPIO_H |
0cdc8b92 | 693 | select NEED_MACH_MEMORY_H |
375dec92 | 694 | select SPARSE_IRQ |
f999b8bd MM |
695 | help |
696 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 697 | |
b130d5c2 KK |
698 | config ARCH_S3C24XX |
699 | bool "Samsung S3C24XX SoCs" | |
9d56c02a | 700 | select ARCH_HAS_CPUFREQ |
53650430 | 701 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 702 | select CLKDEV_LOOKUP |
7f78b6eb RN |
703 | select CLKSRC_MMIO |
704 | select GENERIC_CLOCKEVENTS | |
880cf071 | 705 | select GPIO_SAMSUNG |
b1b3f49c | 706 | select HAVE_CLK |
20676c15 | 707 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 708 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 709 | select HAVE_S3C_RTC if RTC_CLASS |
17453dd2 | 710 | select MULTI_IRQ_HANDLER |
01464226 | 711 | select NEED_MACH_GPIO_H |
c334bc15 | 712 | select NEED_MACH_IO_H |
cd8dc7ae | 713 | select SAMSUNG_ATAGS |
1da177e4 | 714 | help |
b130d5c2 KK |
715 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
716 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
717 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
718 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 719 | |
a08ab637 BD |
720 | config ARCH_S3C64XX |
721 | bool "Samsung S3C64XX" | |
b1b3f49c RK |
722 | select ARCH_HAS_CPUFREQ |
723 | select ARCH_REQUIRE_GPIOLIB | |
89f0ce72 | 724 | select ARM_VIC |
b1b3f49c | 725 | select CLKDEV_LOOKUP |
04a49b71 | 726 | select CLKSRC_MMIO |
b1b3f49c | 727 | select CPU_V6 |
04a49b71 | 728 | select GENERIC_CLOCKEVENTS |
880cf071 | 729 | select GPIO_SAMSUNG |
a08ab637 | 730 | select HAVE_CLK |
b1b3f49c RK |
731 | select HAVE_S3C2410_I2C if I2C |
732 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
6700397a | 733 | select HAVE_TCM |
b1b3f49c | 734 | select NEED_MACH_GPIO_H |
89f0ce72 | 735 | select NO_IOPORT |
b1b3f49c RK |
736 | select PLAT_SAMSUNG |
737 | select S3C_DEV_NAND | |
738 | select S3C_GPIO_TRACK | |
cd8dc7ae | 739 | select SAMSUNG_ATAGS |
89f0ce72 | 740 | select SAMSUNG_CLKSRC |
b1b3f49c | 741 | select SAMSUNG_GPIOLIB_4BIT |
89f0ce72 | 742 | select SAMSUNG_IRQ_VIC_TIMER |
88f59738 | 743 | select SAMSUNG_WDT_RESET |
89f0ce72 | 744 | select USB_ARCH_HAS_OHCI |
a08ab637 BD |
745 | help |
746 | Samsung S3C64XX series based systems | |
747 | ||
49b7a491 KK |
748 | config ARCH_S5P64X0 |
749 | bool "Samsung S5P6440 S5P6450" | |
d8b22d25 | 750 | select CLKDEV_LOOKUP |
0665ccc4 | 751 | select CLKSRC_MMIO |
b1b3f49c | 752 | select CPU_V6 |
9e65bbf2 | 753 | select GENERIC_CLOCKEVENTS |
880cf071 | 754 | select GPIO_SAMSUNG |
b1b3f49c | 755 | select HAVE_CLK |
20676c15 | 756 | select HAVE_S3C2410_I2C if I2C |
b1b3f49c | 757 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
754961a8 | 758 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 759 | select NEED_MACH_GPIO_H |
88f59738 | 760 | select SAMSUNG_WDT_RESET |
cd8dc7ae | 761 | select SAMSUNG_ATAGS |
c4ffccdd | 762 | help |
49b7a491 KK |
763 | Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, |
764 | SMDK6450. | |
c4ffccdd | 765 | |
acc84707 MS |
766 | config ARCH_S5PC100 |
767 | bool "Samsung S5PC100" | |
53650430 | 768 | select ARCH_REQUIRE_GPIOLIB |
29e8eb0f | 769 | select CLKDEV_LOOKUP |
6a5a2e3b | 770 | select CLKSRC_MMIO |
5a7652f2 | 771 | select CPU_V7 |
6a5a2e3b | 772 | select GENERIC_CLOCKEVENTS |
880cf071 | 773 | select GPIO_SAMSUNG |
b1b3f49c | 774 | select HAVE_CLK |
20676c15 | 775 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 776 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 777 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 778 | select NEED_MACH_GPIO_H |
88f59738 | 779 | select SAMSUNG_WDT_RESET |
cd8dc7ae | 780 | select SAMSUNG_ATAGS |
5a7652f2 | 781 | help |
acc84707 | 782 | Samsung S5PC100 series based systems |
5a7652f2 | 783 | |
170f4e42 KK |
784 | config ARCH_S5PV210 |
785 | bool "Samsung S5PV210/S5PC110" | |
b1b3f49c | 786 | select ARCH_HAS_CPUFREQ |
0f75a96b | 787 | select ARCH_HAS_HOLES_MEMORYMODEL |
b1b3f49c | 788 | select ARCH_SPARSEMEM_ENABLE |
b2a9dd46 | 789 | select CLKDEV_LOOKUP |
0665ccc4 | 790 | select CLKSRC_MMIO |
b1b3f49c | 791 | select CPU_V7 |
9e65bbf2 | 792 | select GENERIC_CLOCKEVENTS |
880cf071 | 793 | select GPIO_SAMSUNG |
b1b3f49c | 794 | select HAVE_CLK |
20676c15 | 795 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 796 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 797 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 798 | select NEED_MACH_GPIO_H |
0cdc8b92 | 799 | select NEED_MACH_MEMORY_H |
cd8dc7ae | 800 | select SAMSUNG_ATAGS |
170f4e42 KK |
801 | help |
802 | Samsung S5PV210/S5PC110 series based systems | |
803 | ||
83014579 | 804 | config ARCH_EXYNOS |
93e22567 | 805 | bool "Samsung EXYNOS" |
b1b3f49c | 806 | select ARCH_HAS_CPUFREQ |
0f75a96b | 807 | select ARCH_HAS_HOLES_MEMORYMODEL |
e245f969 | 808 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 809 | select ARCH_SPARSEMEM_ENABLE |
e245f969 | 810 | select ARM_GIC |
badc4f2d | 811 | select CLKDEV_LOOKUP |
340fcb5c | 812 | select COMMON_CLK |
b1b3f49c | 813 | select CPU_V7 |
cc0e72b8 | 814 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 815 | select HAVE_CLK |
20676c15 | 816 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 817 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 818 | select HAVE_S3C_RTC if RTC_CLASS |
0cdc8b92 | 819 | select NEED_MACH_MEMORY_H |
6e726ea4 | 820 | select SPARSE_IRQ |
f8b1ac01 | 821 | select USE_OF |
cc0e72b8 | 822 | help |
83014579 | 823 | Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) |
cc0e72b8 | 824 | |
1da177e4 LT |
825 | config ARCH_SHARK |
826 | bool "Shark" | |
b1b3f49c | 827 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 828 | select CPU_SA110 |
f7e68bbf RK |
829 | select ISA |
830 | select ISA_DMA | |
0cdc8b92 | 831 | select NEED_MACH_MEMORY_H |
b1b3f49c | 832 | select PCI |
b4811bac | 833 | select VIRT_TO_BUS |
b1b3f49c | 834 | select ZONE_DMA |
f999b8bd MM |
835 | help |
836 | Support for the StrongARM based Digital DNARD machine, also known | |
837 | as "Shark" (<http://www.shark-linux.de/shark.html>). | |
1da177e4 | 838 | |
7c6337e2 KH |
839 | config ARCH_DAVINCI |
840 | bool "TI DaVinci" | |
b1b3f49c | 841 | select ARCH_HAS_HOLES_MEMORYMODEL |
dce1115b | 842 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 843 | select CLKDEV_LOOKUP |
20e9969b | 844 | select GENERIC_ALLOCATOR |
b1b3f49c | 845 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 846 | select GENERIC_IRQ_CHIP |
b1b3f49c | 847 | select HAVE_IDE |
01464226 | 848 | select NEED_MACH_GPIO_H |
3ad7a42d | 849 | select TI_PRIV_EDMA |
689e331f | 850 | select USE_OF |
b1b3f49c | 851 | select ZONE_DMA |
7c6337e2 KH |
852 | help |
853 | Support for TI's DaVinci platform. | |
854 | ||
a0694861 TL |
855 | config ARCH_OMAP1 |
856 | bool "TI OMAP1" | |
00a36698 | 857 | depends on MMU |
89c52ed4 | 858 | select ARCH_HAS_CPUFREQ |
9af915da | 859 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 860 | select ARCH_OMAP |
21f47fbc | 861 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 862 | select CLKDEV_LOOKUP |
d6e15d78 | 863 | select CLKSRC_MMIO |
b1b3f49c | 864 | select GENERIC_CLOCKEVENTS |
a0694861 | 865 | select GENERIC_IRQ_CHIP |
e9a91de7 | 866 | select HAVE_CLK |
a0694861 TL |
867 | select HAVE_IDE |
868 | select IRQ_DOMAIN | |
869 | select NEED_MACH_IO_H if PCCARD | |
870 | select NEED_MACH_MEMORY_H | |
21f47fbc | 871 | help |
a0694861 | 872 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 873 | |
1da177e4 LT |
874 | endchoice |
875 | ||
387798b3 RH |
876 | menu "Multiple platform selection" |
877 | depends on ARCH_MULTIPLATFORM | |
878 | ||
879 | comment "CPU Core family selection" | |
880 | ||
387798b3 RH |
881 | config ARCH_MULTI_V4T |
882 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 883 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 884 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
885 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
886 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
887 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
888 | |
889 | config ARCH_MULTI_V5 | |
890 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 891 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 892 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
893 | select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ |
894 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ | |
895 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
896 | |
897 | config ARCH_MULTI_V4_V5 | |
898 | bool | |
899 | ||
900 | config ARCH_MULTI_V6 | |
8dda05cc | 901 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 902 | select ARCH_MULTI_V6_V7 |
b1b3f49c | 903 | select CPU_V6 |
387798b3 RH |
904 | |
905 | config ARCH_MULTI_V7 | |
8dda05cc | 906 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
907 | default y |
908 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 909 | select CPU_V7 |
387798b3 RH |
910 | |
911 | config ARCH_MULTI_V6_V7 | |
912 | bool | |
913 | ||
914 | config ARCH_MULTI_CPU_AUTO | |
915 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
916 | select ARCH_MULTI_V5 | |
917 | ||
918 | endmenu | |
919 | ||
ccf50e23 RK |
920 | # |
921 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
922 | # Kconfigs may be included either alphabetically (according to the | |
923 | # plat- suffix) or along side the corresponding mach-* source. | |
924 | # | |
3e93a22b GC |
925 | source "arch/arm/mach-mvebu/Kconfig" |
926 | ||
95b8f20f RK |
927 | source "arch/arm/mach-at91/Kconfig" |
928 | ||
8ac49e04 CD |
929 | source "arch/arm/mach-bcm/Kconfig" |
930 | ||
f1ac922d SW |
931 | source "arch/arm/mach-bcm2835/Kconfig" |
932 | ||
1da177e4 LT |
933 | source "arch/arm/mach-clps711x/Kconfig" |
934 | ||
d94f944e AV |
935 | source "arch/arm/mach-cns3xxx/Kconfig" |
936 | ||
95b8f20f RK |
937 | source "arch/arm/mach-davinci/Kconfig" |
938 | ||
939 | source "arch/arm/mach-dove/Kconfig" | |
940 | ||
e7736d47 LB |
941 | source "arch/arm/mach-ep93xx/Kconfig" |
942 | ||
1da177e4 LT |
943 | source "arch/arm/mach-footbridge/Kconfig" |
944 | ||
59d3a193 PZ |
945 | source "arch/arm/mach-gemini/Kconfig" |
946 | ||
387798b3 RH |
947 | source "arch/arm/mach-highbank/Kconfig" |
948 | ||
1da177e4 LT |
949 | source "arch/arm/mach-integrator/Kconfig" |
950 | ||
3f7e5815 LB |
951 | source "arch/arm/mach-iop32x/Kconfig" |
952 | ||
953 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 954 | |
285f5fa7 DW |
955 | source "arch/arm/mach-iop13xx/Kconfig" |
956 | ||
1da177e4 LT |
957 | source "arch/arm/mach-ixp4xx/Kconfig" |
958 | ||
828989ad SS |
959 | source "arch/arm/mach-keystone/Kconfig" |
960 | ||
95b8f20f RK |
961 | source "arch/arm/mach-kirkwood/Kconfig" |
962 | ||
963 | source "arch/arm/mach-ks8695/Kconfig" | |
964 | ||
95b8f20f RK |
965 | source "arch/arm/mach-msm/Kconfig" |
966 | ||
794d15b2 SS |
967 | source "arch/arm/mach-mv78xx0/Kconfig" |
968 | ||
3995eb82 | 969 | source "arch/arm/mach-imx/Kconfig" |
1da177e4 | 970 | |
1d3f33d5 SG |
971 | source "arch/arm/mach-mxs/Kconfig" |
972 | ||
95b8f20f | 973 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 974 | |
95b8f20f | 975 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 976 | |
9851ca57 DT |
977 | source "arch/arm/mach-nspire/Kconfig" |
978 | ||
d48af15e TL |
979 | source "arch/arm/plat-omap/Kconfig" |
980 | ||
981 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 982 | |
1dbae815 TL |
983 | source "arch/arm/mach-omap2/Kconfig" |
984 | ||
9dd0b194 | 985 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 986 | |
387798b3 RH |
987 | source "arch/arm/mach-picoxcell/Kconfig" |
988 | ||
95b8f20f RK |
989 | source "arch/arm/mach-pxa/Kconfig" |
990 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 991 | |
95b8f20f RK |
992 | source "arch/arm/mach-mmp/Kconfig" |
993 | ||
994 | source "arch/arm/mach-realview/Kconfig" | |
995 | ||
d63dc051 HS |
996 | source "arch/arm/mach-rockchip/Kconfig" |
997 | ||
95b8f20f | 998 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 999 | |
cf383678 | 1000 | source "arch/arm/plat-samsung/Kconfig" |
a21765a7 | 1001 | |
387798b3 RH |
1002 | source "arch/arm/mach-socfpga/Kconfig" |
1003 | ||
a7ed099f | 1004 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 1005 | |
65ebcc11 SK |
1006 | source "arch/arm/mach-sti/Kconfig" |
1007 | ||
85fd6d63 | 1008 | source "arch/arm/mach-s3c24xx/Kconfig" |
1da177e4 | 1009 | |
a08ab637 | 1010 | if ARCH_S3C64XX |
431107ea | 1011 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 BD |
1012 | endif |
1013 | ||
49b7a491 | 1014 | source "arch/arm/mach-s5p64x0/Kconfig" |
c4ffccdd | 1015 | |
5a7652f2 | 1016 | source "arch/arm/mach-s5pc100/Kconfig" |
5a7652f2 | 1017 | |
170f4e42 KK |
1018 | source "arch/arm/mach-s5pv210/Kconfig" |
1019 | ||
83014579 | 1020 | source "arch/arm/mach-exynos/Kconfig" |
cc0e72b8 | 1021 | |
882d01f9 | 1022 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 1023 | |
3b52634f MR |
1024 | source "arch/arm/mach-sunxi/Kconfig" |
1025 | ||
156a0997 BS |
1026 | source "arch/arm/mach-prima2/Kconfig" |
1027 | ||
c5f80065 EG |
1028 | source "arch/arm/mach-tegra/Kconfig" |
1029 | ||
95b8f20f | 1030 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 1031 | |
95b8f20f | 1032 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
1033 | |
1034 | source "arch/arm/mach-versatile/Kconfig" | |
1035 | ||
ceade897 | 1036 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 1037 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 1038 | |
2a0ba738 MZ |
1039 | source "arch/arm/mach-virt/Kconfig" |
1040 | ||
6f35f9a9 TP |
1041 | source "arch/arm/mach-vt8500/Kconfig" |
1042 | ||
7ec80ddf | 1043 | source "arch/arm/mach-w90x900/Kconfig" |
1044 | ||
9a45eb69 JC |
1045 | source "arch/arm/mach-zynq/Kconfig" |
1046 | ||
1da177e4 LT |
1047 | # Definitions to make life easier |
1048 | config ARCH_ACORN | |
1049 | bool | |
1050 | ||
7ae1f7ec LB |
1051 | config PLAT_IOP |
1052 | bool | |
469d3044 | 1053 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 1054 | |
69b02f6a LB |
1055 | config PLAT_ORION |
1056 | bool | |
bfe45e0b | 1057 | select CLKSRC_MMIO |
b1b3f49c | 1058 | select COMMON_CLK |
dc7ad3b3 | 1059 | select GENERIC_IRQ_CHIP |
278b45b0 | 1060 | select IRQ_DOMAIN |
69b02f6a | 1061 | |
abcda1dc TP |
1062 | config PLAT_ORION_LEGACY |
1063 | bool | |
1064 | select PLAT_ORION | |
1065 | ||
bd5ce433 EM |
1066 | config PLAT_PXA |
1067 | bool | |
1068 | ||
f4b8b319 RK |
1069 | config PLAT_VERSATILE |
1070 | bool | |
1071 | ||
e3887714 RK |
1072 | config ARM_TIMER_SP804 |
1073 | bool | |
bfe45e0b | 1074 | select CLKSRC_MMIO |
7a0eca71 | 1075 | select CLKSRC_OF if OF |
e3887714 | 1076 | |
1da177e4 LT |
1077 | source arch/arm/mm/Kconfig |
1078 | ||
958cab0f RK |
1079 | config ARM_NR_BANKS |
1080 | int | |
1081 | default 16 if ARCH_EP93XX | |
1082 | default 8 | |
1083 | ||
afe4b25e | 1084 | config IWMMXT |
698613b6 | 1085 | bool "Enable iWMMXt support" if !CPU_PJ4 |
ef6c8445 | 1086 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 |
698613b6 | 1087 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 |
afe4b25e LB |
1088 | help |
1089 | Enable support for iWMMXt context switching at run time if | |
1090 | running on a CPU that supports it. | |
1091 | ||
1da177e4 LT |
1092 | config XSCALE_PMU |
1093 | bool | |
bfc994b5 | 1094 | depends on CPU_XSCALE |
1da177e4 LT |
1095 | default y |
1096 | ||
52108641 | 1097 | config MULTI_IRQ_HANDLER |
1098 | bool | |
1099 | help | |
1100 | Allow each machine to specify it's own IRQ handler at run time. | |
1101 | ||
3b93e7b0 HC |
1102 | if !MMU |
1103 | source "arch/arm/Kconfig-nommu" | |
1104 | endif | |
1105 | ||
3e0a07f8 GC |
1106 | config PJ4B_ERRATA_4742 |
1107 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
1108 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
1109 | default y | |
1110 | help | |
1111 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
1112 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
1113 | the retiring WFI/WFE instructions and the newly issued subsequent | |
1114 | instructions. This sensitivity can result in a CPU hang scenario. | |
1115 | Workaround: | |
1116 | The software must insert either a Data Synchronization Barrier (DSB) | |
1117 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
1118 | instruction | |
1119 | ||
f0c4b8d6 WD |
1120 | config ARM_ERRATA_326103 |
1121 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
1122 | depends on CPU_V6 | |
1123 | help | |
1124 | Executing a SWP instruction to read-only memory does not set bit 11 | |
1125 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
1126 | treat the access as a read, preventing a COW from occurring and | |
1127 | causing the faulting task to livelock. | |
1128 | ||
9cba3ccc CM |
1129 | config ARM_ERRATA_411920 |
1130 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 1131 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
1132 | help |
1133 | Invalidation of the Instruction Cache operation can | |
1134 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1135 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1136 | recommended workaround. | |
1137 | ||
7ce236fc CM |
1138 | config ARM_ERRATA_430973 |
1139 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1140 | depends on CPU_V7 | |
1141 | help | |
1142 | This option enables the workaround for the 430973 Cortex-A8 | |
1143 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1144 | interworking branch is replaced with another code sequence at the | |
1145 | same virtual address, whether due to self-modifying code or virtual | |
1146 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1147 | stale interworking branch prediction. This results in Cortex-A8 | |
1148 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1149 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1150 | and also flushes the branch target cache at every context switch. | |
1151 | Note that setting specific bits in the ACTLR register may not be | |
1152 | available in non-secure mode. | |
1153 | ||
855c551f CM |
1154 | config ARM_ERRATA_458693 |
1155 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1156 | depends on CPU_V7 | |
62e4d357 | 1157 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
1158 | help |
1159 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1160 | erratum. For very specific sequences of memory operations, it is | |
1161 | possible for a hazard condition intended for a cache line to instead | |
1162 | be incorrectly associated with a different cache line. This false | |
1163 | hazard might then cause a processor deadlock. The workaround enables | |
1164 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1165 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1166 | register may not be available in non-secure mode. | |
1167 | ||
0516e464 CM |
1168 | config ARM_ERRATA_460075 |
1169 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1170 | depends on CPU_V7 | |
62e4d357 | 1171 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
1172 | help |
1173 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1174 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1175 | situation in which recent store transactions to the L2 cache are lost | |
1176 | and overwritten with stale memory contents from external memory. The | |
1177 | workaround disables the write-allocate mode for the L2 cache via the | |
1178 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1179 | may not be available in non-secure mode. | |
1180 | ||
9f05027c WD |
1181 | config ARM_ERRATA_742230 |
1182 | bool "ARM errata: DMB operation may be faulty" | |
1183 | depends on CPU_V7 && SMP | |
62e4d357 | 1184 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1185 | help |
1186 | This option enables the workaround for the 742230 Cortex-A9 | |
1187 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1188 | between two write operations may not ensure the correct visibility | |
1189 | ordering of the two writes. This workaround sets a specific bit in | |
1190 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1191 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1192 | the two writes. | |
1193 | ||
a672e99b WD |
1194 | config ARM_ERRATA_742231 |
1195 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1196 | depends on CPU_V7 && SMP | |
62e4d357 | 1197 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1198 | help |
1199 | This option enables the workaround for the 742231 Cortex-A9 | |
1200 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1201 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1202 | accessing some data located in the same cache line, may get corrupted | |
1203 | data due to bad handling of the address hazard when the line gets | |
1204 | replaced from one of the CPUs at the same time as another CPU is | |
1205 | accessing it. This workaround sets specific bits in the diagnostic | |
1206 | register of the Cortex-A9 which reduces the linefill issuing | |
1207 | capabilities of the processor. | |
1208 | ||
9e65582a | 1209 | config PL310_ERRATA_588369 |
fa0ce403 | 1210 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" |
2839e06c | 1211 | depends on CACHE_L2X0 |
9e65582a SS |
1212 | help |
1213 | The PL310 L2 cache controller implements three types of Clean & | |
1214 | Invalidate maintenance operations: by Physical Address | |
1215 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
1216 | They are architecturally defined to behave as the execution of a | |
1217 | clean operation followed immediately by an invalidate operation, | |
1218 | both performing to the same memory location. This functionality | |
1219 | is not correctly implemented in PL310 as clean lines are not | |
2839e06c | 1220 | invalidated as a result of these operations. |
cdf357f1 | 1221 | |
69155794 JM |
1222 | config ARM_ERRATA_643719 |
1223 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1224 | depends on CPU_V7 && SMP | |
1225 | help | |
1226 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1227 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1228 | register returns zero when it should return one. The workaround | |
1229 | corrects this value, ensuring cache maintenance operations which use | |
1230 | it behave as intended and avoiding data corruption. | |
1231 | ||
cdf357f1 WD |
1232 | config ARM_ERRATA_720789 |
1233 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1234 | depends on CPU_V7 |
cdf357f1 WD |
1235 | help |
1236 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1237 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1238 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1239 | As a consequence of this erratum, some TLB entries which should be | |
1240 | invalidated are not, resulting in an incoherency in the system page | |
1241 | tables. The workaround changes the TLB flushing routines to invalidate | |
1242 | entries regardless of the ASID. | |
475d92fc | 1243 | |
1f0090a1 | 1244 | config PL310_ERRATA_727915 |
fa0ce403 | 1245 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" |
1f0090a1 RK |
1246 | depends on CACHE_L2X0 |
1247 | help | |
1248 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
1249 | operation (offset 0x7FC). This operation runs in background so that | |
1250 | PL310 can handle normal accesses while it is in progress. Under very | |
1251 | rare circumstances, due to this erratum, write data can be lost when | |
1252 | PL310 treats a cacheable write transaction during a Clean & | |
1253 | Invalidate by Way operation. | |
1254 | ||
475d92fc WD |
1255 | config ARM_ERRATA_743622 |
1256 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1257 | depends on CPU_V7 | |
62e4d357 | 1258 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1259 | help |
1260 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1261 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1262 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1263 | corruption. This workaround sets a specific bit in the diagnostic | |
1264 | register of the Cortex-A9 which disables the Store Buffer | |
1265 | optimisation, preventing the defect from occurring. This has no | |
1266 | visible impact on the overall performance or power consumption of the | |
1267 | processor. | |
1268 | ||
9a27c27c WD |
1269 | config ARM_ERRATA_751472 |
1270 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1271 | depends on CPU_V7 |
62e4d357 | 1272 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1273 | help |
1274 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1275 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1276 | completion of a following broadcasted operation if the second | |
1277 | operation is received by a CPU before the ICIALLUIS has completed, | |
1278 | potentially leading to corrupted entries in the cache or TLB. | |
1279 | ||
fa0ce403 WD |
1280 | config PL310_ERRATA_753970 |
1281 | bool "PL310 errata: cache sync operation may be faulty" | |
885028e4 SK |
1282 | depends on CACHE_PL310 |
1283 | help | |
1284 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
1285 | ||
1286 | Under some condition the effect of cache sync operation on | |
1287 | the store buffer still remains when the operation completes. | |
1288 | This means that the store buffer is always asked to drain and | |
1289 | this prevents it from merging any further writes. The workaround | |
1290 | is to replace the normal offset of cache sync operation (0x730) | |
1291 | by another offset targeting an unmapped PL310 register 0x740. | |
1292 | This has the same effect as the cache sync operation: store buffer | |
1293 | drain and waiting for all buffers empty. | |
1294 | ||
fcbdc5fe WD |
1295 | config ARM_ERRATA_754322 |
1296 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1297 | depends on CPU_V7 | |
1298 | help | |
1299 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1300 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1301 | which starts prior to an ASID switch but completes afterwards. This | |
1302 | can populate the micro-TLB with a stale entry which may be hit with | |
1303 | the new ASID. This workaround places two dsb instructions in the mm | |
1304 | switching code so that no page table walks can cross the ASID switch. | |
1305 | ||
5dab26af WD |
1306 | config ARM_ERRATA_754327 |
1307 | bool "ARM errata: no automatic Store Buffer drain" | |
1308 | depends on CPU_V7 && SMP | |
1309 | help | |
1310 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1311 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1312 | mechanism and therefore a livelock may occur if an external agent | |
1313 | continuously polls a memory location waiting to observe an update. | |
1314 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1315 | written polling loops from denying visibility of updates to memory. | |
1316 | ||
145e10e1 CM |
1317 | config ARM_ERRATA_364296 |
1318 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 1319 | depends on CPU_V6 |
145e10e1 CM |
1320 | help |
1321 | This options enables the workaround for the 364296 ARM1136 | |
1322 | r0p2 erratum (possible cache data corruption with | |
1323 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1324 | the auxiliary control register and the FI bit in the control | |
1325 | register, thus disabling hit-under-miss without putting the | |
1326 | processor into full low interrupt latency mode. ARM11MPCore | |
1327 | is not affected. | |
1328 | ||
f630c1bd WD |
1329 | config ARM_ERRATA_764369 |
1330 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1331 | depends on CPU_V7 && SMP | |
1332 | help | |
1333 | This option enables the workaround for erratum 764369 | |
1334 | affecting Cortex-A9 MPCore with two or more processors (all | |
1335 | current revisions). Under certain timing circumstances, a data | |
1336 | cache line maintenance operation by MVA targeting an Inner | |
1337 | Shareable memory region may fail to proceed up to either the | |
1338 | Point of Coherency or to the Point of Unification of the | |
1339 | system. This workaround adds a DSB instruction before the | |
1340 | relevant cache maintenance functions and sets a specific bit | |
1341 | in the diagnostic control register of the SCU. | |
1342 | ||
11ed0ba1 WD |
1343 | config PL310_ERRATA_769419 |
1344 | bool "PL310 errata: no automatic Store Buffer drain" | |
1345 | depends on CACHE_L2X0 | |
1346 | help | |
1347 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
1348 | not automatically drain. This can cause normal, non-cacheable | |
1349 | writes to be retained when the memory system is idle, leading | |
1350 | to suboptimal I/O performance for drivers using coherent DMA. | |
1351 | This option adds a write barrier to the cpu_idle loop so that, | |
1352 | on systems with an outer cache, the store buffer is drained | |
1353 | explicitly. | |
1354 | ||
7253b85c SH |
1355 | config ARM_ERRATA_775420 |
1356 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1357 | depends on CPU_V7 | |
1358 | help | |
1359 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1360 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1361 | operation aborts with MMU exception, it might cause the processor | |
1362 | to deadlock. This workaround puts DSB before executing ISB if | |
1363 | an abort may occur on cache maintenance. | |
1364 | ||
93dc6887 CM |
1365 | config ARM_ERRATA_798181 |
1366 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1367 | depends on CPU_V7 && SMP | |
1368 | help | |
1369 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1370 | adequately shooting down all use of the old entries. This | |
1371 | option enables the Linux kernel workaround for this erratum | |
1372 | which sends an IPI to the CPUs that are running the same ASID | |
1373 | as the one being invalidated. | |
1374 | ||
1da177e4 LT |
1375 | endmenu |
1376 | ||
1377 | source "arch/arm/common/Kconfig" | |
1378 | ||
1da177e4 LT |
1379 | menu "Bus support" |
1380 | ||
1381 | config ARM_AMBA | |
1382 | bool | |
1383 | ||
1384 | config ISA | |
1385 | bool | |
1da177e4 LT |
1386 | help |
1387 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1388 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1389 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1390 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1391 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1392 | ||
065909b9 | 1393 | # Select ISA DMA controller support |
1da177e4 LT |
1394 | config ISA_DMA |
1395 | bool | |
065909b9 | 1396 | select ISA_DMA_API |
1da177e4 | 1397 | |
065909b9 | 1398 | # Select ISA DMA interface |
5cae841b AV |
1399 | config ISA_DMA_API |
1400 | bool | |
5cae841b | 1401 | |
1da177e4 | 1402 | config PCI |
0b05da72 | 1403 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1404 | help |
1405 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1406 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1407 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1408 | VESA. If you have PCI, say Y, otherwise N. | |
1409 | ||
52882173 AV |
1410 | config PCI_DOMAINS |
1411 | bool | |
1412 | depends on PCI | |
1413 | ||
b080ac8a MRJ |
1414 | config PCI_NANOENGINE |
1415 | bool "BSE nanoEngine PCI support" | |
1416 | depends on SA1100_NANOENGINE | |
1417 | help | |
1418 | Enable PCI on the BSE nanoEngine board. | |
1419 | ||
36e23590 MW |
1420 | config PCI_SYSCALL |
1421 | def_bool PCI | |
1422 | ||
1da177e4 LT |
1423 | # Select the host bridge type |
1424 | config PCI_HOST_VIA82C505 | |
1425 | bool | |
1426 | depends on PCI && ARCH_SHARK | |
1427 | default y | |
1428 | ||
a0113a99 MR |
1429 | config PCI_HOST_ITE8152 |
1430 | bool | |
1431 | depends on PCI && MACH_ARMCORE | |
1432 | default y | |
1433 | select DMABOUNCE | |
1434 | ||
1da177e4 | 1435 | source "drivers/pci/Kconfig" |
3f06d157 | 1436 | source "drivers/pci/pcie/Kconfig" |
1da177e4 LT |
1437 | |
1438 | source "drivers/pcmcia/Kconfig" | |
1439 | ||
1440 | endmenu | |
1441 | ||
1442 | menu "Kernel Features" | |
1443 | ||
3b55658a DM |
1444 | config HAVE_SMP |
1445 | bool | |
1446 | help | |
1447 | This option should be selected by machines which have an SMP- | |
1448 | capable CPU. | |
1449 | ||
1450 | The only effect of this option is to make the SMP-related | |
1451 | options available to the user for configuration. | |
1452 | ||
1da177e4 | 1453 | config SMP |
bb2d8130 | 1454 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1455 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1456 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1457 | depends on HAVE_SMP |
801bb21c | 1458 | depends on MMU || ARM_MPU |
b1b3f49c | 1459 | select USE_GENERIC_SMP_HELPERS |
1da177e4 LT |
1460 | help |
1461 | This enables support for systems with more than one CPU. If you have | |
1462 | a system with only one CPU, like most personal computers, say N. If | |
1463 | you have a system with more than one CPU, say Y. | |
1464 | ||
1465 | If you say N here, the kernel will run on single and multiprocessor | |
1466 | machines, but will use only one CPU of a multiprocessor machine. If | |
1467 | you say Y here, the kernel will run on many, but not all, single | |
1468 | processor machines. On a single processor machine, the kernel will | |
1469 | run faster if you say N here. | |
1470 | ||
395cf969 | 1471 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1472 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1473 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1474 | |
1475 | If you don't know what to do here, say N. | |
1476 | ||
f00ec48f RK |
1477 | config SMP_ON_UP |
1478 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
801bb21c | 1479 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1480 | default y |
1481 | help | |
1482 | SMP kernels contain instructions which fail on non-SMP processors. | |
1483 | Enabling this option allows the kernel to modify itself to make | |
1484 | these instructions safe. Disabling it allows about 1K of space | |
1485 | savings. | |
1486 | ||
1487 | If you don't know what to do here, say Y. | |
1488 | ||
c9018aab VG |
1489 | config ARM_CPU_TOPOLOGY |
1490 | bool "Support cpu topology definition" | |
1491 | depends on SMP && CPU_V7 | |
1492 | default y | |
1493 | help | |
1494 | Support ARM cpu topology definition. The MPIDR register defines | |
1495 | affinity between processors which is then used to describe the cpu | |
1496 | topology of an ARM System. | |
1497 | ||
1498 | config SCHED_MC | |
1499 | bool "Multi-core scheduler support" | |
1500 | depends on ARM_CPU_TOPOLOGY | |
1501 | help | |
1502 | Multi-core scheduler support improves the CPU scheduler's decision | |
1503 | making when dealing with multi-core CPU chips at a cost of slightly | |
1504 | increased overhead in some places. If unsure say N here. | |
1505 | ||
1506 | config SCHED_SMT | |
1507 | bool "SMT scheduler support" | |
1508 | depends on ARM_CPU_TOPOLOGY | |
1509 | help | |
1510 | Improves the CPU scheduler's decision making when dealing with | |
1511 | MultiThreading at a cost of slightly increased overhead in some | |
1512 | places. If unsure say N here. | |
1513 | ||
a8cbcd92 RK |
1514 | config HAVE_ARM_SCU |
1515 | bool | |
a8cbcd92 RK |
1516 | help |
1517 | This option enables support for the ARM system coherency unit | |
1518 | ||
8a4da6e3 | 1519 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1520 | bool "Architected timer support" |
1521 | depends on CPU_V7 | |
8a4da6e3 | 1522 | select ARM_ARCH_TIMER |
022c03a2 MZ |
1523 | help |
1524 | This option enables support for the ARM architected timer | |
1525 | ||
f32f4ce2 RK |
1526 | config HAVE_ARM_TWD |
1527 | bool | |
1528 | depends on SMP | |
da4a686a | 1529 | select CLKSRC_OF if OF |
f32f4ce2 RK |
1530 | help |
1531 | This options enables support for the ARM timer and watchdog unit | |
1532 | ||
e8db288e NP |
1533 | config MCPM |
1534 | bool "Multi-Cluster Power Management" | |
1535 | depends on CPU_V7 && SMP | |
1536 | help | |
1537 | This option provides the common power management infrastructure | |
1538 | for (multi-)cluster based systems, such as big.LITTLE based | |
1539 | systems. | |
1540 | ||
8d5796d2 LB |
1541 | choice |
1542 | prompt "Memory split" | |
1543 | default VMSPLIT_3G | |
1544 | help | |
1545 | Select the desired split between kernel and user memory. | |
1546 | ||
1547 | If you are not absolutely sure what you are doing, leave this | |
1548 | option alone! | |
1549 | ||
1550 | config VMSPLIT_3G | |
1551 | bool "3G/1G user/kernel split" | |
1552 | config VMSPLIT_2G | |
1553 | bool "2G/2G user/kernel split" | |
1554 | config VMSPLIT_1G | |
1555 | bool "1G/3G user/kernel split" | |
1556 | endchoice | |
1557 | ||
1558 | config PAGE_OFFSET | |
1559 | hex | |
1560 | default 0x40000000 if VMSPLIT_1G | |
1561 | default 0x80000000 if VMSPLIT_2G | |
1562 | default 0xC0000000 | |
1563 | ||
1da177e4 LT |
1564 | config NR_CPUS |
1565 | int "Maximum number of CPUs (2-32)" | |
1566 | range 2 32 | |
1567 | depends on SMP | |
1568 | default "4" | |
1569 | ||
a054a811 | 1570 | config HOTPLUG_CPU |
00b7dede | 1571 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1572 | depends on SMP |
a054a811 RK |
1573 | help |
1574 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1575 | can be controlled through /sys/devices/system/cpu. | |
1576 | ||
2bdd424f WD |
1577 | config ARM_PSCI |
1578 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
1579 | depends on CPU_V7 | |
1580 | help | |
1581 | Say Y here if you want Linux to communicate with system firmware | |
1582 | implementing the PSCI specification for CPU-centric power | |
1583 | management operations described in ARM document number ARM DEN | |
1584 | 0022A ("Power State Coordination Interface System Software on | |
1585 | ARM processors"). | |
1586 | ||
37ee16ae RK |
1587 | config LOCAL_TIMERS |
1588 | bool "Use local timer interrupts" | |
971acb9b | 1589 | depends on SMP |
37ee16ae RK |
1590 | default y |
1591 | help | |
1592 | Enable support for local timers on SMP platforms, rather then the | |
1593 | legacy IPI broadcast method. Local timers allows the system | |
1594 | accounting to be spread across the timer interval, preventing a | |
1595 | "thundering herd" at every timer tick. | |
1596 | ||
2a6ad871 MR |
1597 | # The GPIO number here must be sorted by descending number. In case of |
1598 | # a multiplatform kernel, we just want the highest value required by the | |
1599 | # selected platforms. | |
44986ab0 PDSN |
1600 | config ARCH_NR_GPIO |
1601 | int | |
3dea19e8 | 1602 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
53302bf6 | 1603 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 |
06b851e5 | 1604 | default 392 if ARCH_U8500 |
01bb914c TP |
1605 | default 352 if ARCH_VT8500 |
1606 | default 288 if ARCH_SUNXI | |
2a6ad871 | 1607 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1608 | default 0 |
1609 | help | |
1610 | Maximum number of GPIOs in the system. | |
1611 | ||
1612 | If unsure, leave the default value. | |
1613 | ||
d45a398f | 1614 | source kernel/Kconfig.preempt |
1da177e4 | 1615 | |
f8065813 RK |
1616 | config HZ |
1617 | int | |
b130d5c2 | 1618 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ |
a73ddc61 | 1619 | ARCH_S5PV210 || ARCH_EXYNOS4 |
5248c657 | 1620 | default AT91_TIMER_HZ if ARCH_AT91 |
5da3e714 | 1621 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE |
f8065813 RK |
1622 | default 100 |
1623 | ||
b28748fb RK |
1624 | config SCHED_HRTICK |
1625 | def_bool HIGH_RES_TIMERS | |
1626 | ||
16c79651 | 1627 | config THUMB2_KERNEL |
bc7dea00 | 1628 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1629 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1630 | default y if CPU_THUMBONLY |
16c79651 CM |
1631 | select AEABI |
1632 | select ARM_ASM_UNIFIED | |
89bace65 | 1633 | select ARM_UNWIND |
16c79651 CM |
1634 | help |
1635 | By enabling this option, the kernel will be compiled in | |
1636 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1637 | ARM-Thumb syntax is needed. | |
1638 | ||
1639 | If unsure, say N. | |
1640 | ||
6f685c5c DM |
1641 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1642 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1643 | depends on THUMB2_KERNEL && MODULES | |
1644 | default y | |
1645 | help | |
1646 | Various binutils versions can resolve Thumb-2 branches to | |
1647 | locally-defined, preemptible global symbols as short-range "b.n" | |
1648 | branch instructions. | |
1649 | ||
1650 | This is a problem, because there's no guarantee the final | |
1651 | destination of the symbol, or any candidate locations for a | |
1652 | trampoline, are within range of the branch. For this reason, the | |
1653 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1654 | relocation in modules at all, and it makes little sense to add | |
1655 | support. | |
1656 | ||
1657 | The symptom is that the kernel fails with an "unsupported | |
1658 | relocation" error when loading some modules. | |
1659 | ||
1660 | Until fixed tools are available, passing | |
1661 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1662 | code which hits this problem, at the cost of a bit of extra runtime | |
1663 | stack usage in some cases. | |
1664 | ||
1665 | The problem is described in more detail at: | |
1666 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1667 | ||
1668 | Only Thumb-2 kernels are affected. | |
1669 | ||
1670 | Unless you are sure your tools don't have this problem, say Y. | |
1671 | ||
0becb088 CM |
1672 | config ARM_ASM_UNIFIED |
1673 | bool | |
1674 | ||
704bdda0 NP |
1675 | config AEABI |
1676 | bool "Use the ARM EABI to compile the kernel" | |
1677 | help | |
1678 | This option allows for the kernel to be compiled using the latest | |
1679 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1680 | space environment that is also compiled with EABI. | |
1681 | ||
1682 | Since there are major incompatibilities between the legacy ABI and | |
1683 | EABI, especially with regard to structure member alignment, this | |
1684 | option also changes the kernel syscall calling convention to | |
1685 | disambiguate both ABIs and allow for backward compatibility support | |
1686 | (selected with CONFIG_OABI_COMPAT). | |
1687 | ||
1688 | To use this you need GCC version 4.0.0 or later. | |
1689 | ||
6c90c872 | 1690 | config OABI_COMPAT |
a73a3ff1 | 1691 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1692 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1693 | default y |
1694 | help | |
1695 | This option preserves the old syscall interface along with the | |
1696 | new (ARM EABI) one. It also provides a compatibility layer to | |
1697 | intercept syscalls that have structure arguments which layout | |
1698 | in memory differs between the legacy ABI and the new ARM EABI | |
1699 | (only for non "thumb" binaries). This option adds a tiny | |
1700 | overhead to all syscalls and produces a slightly larger kernel. | |
1701 | If you know you'll be using only pure EABI user space then you | |
1702 | can say N here. If this option is not selected and you attempt | |
1703 | to execute a legacy ABI binary then the result will be | |
1704 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
1705 | at all). If in doubt say Y. | |
1706 | ||
eb33575c | 1707 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1708 | bool |
e80d6a24 | 1709 | |
05944d74 RK |
1710 | config ARCH_SPARSEMEM_ENABLE |
1711 | bool | |
1712 | ||
07a2f737 RK |
1713 | config ARCH_SPARSEMEM_DEFAULT |
1714 | def_bool ARCH_SPARSEMEM_ENABLE | |
1715 | ||
05944d74 | 1716 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1717 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1718 | |
7b7bf499 WD |
1719 | config HAVE_ARCH_PFN_VALID |
1720 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1721 | ||
053a96ca | 1722 | config HIGHMEM |
e8db89a2 RK |
1723 | bool "High Memory Support" |
1724 | depends on MMU | |
053a96ca NP |
1725 | help |
1726 | The address space of ARM processors is only 4 Gigabytes large | |
1727 | and it has to accommodate user address space, kernel address | |
1728 | space as well as some memory mapped IO. That means that, if you | |
1729 | have a large amount of physical memory and/or IO, not all of the | |
1730 | memory can be "permanently mapped" by the kernel. The physical | |
1731 | memory that is not permanently mapped is called "high memory". | |
1732 | ||
1733 | Depending on the selected kernel/user memory split, minimum | |
1734 | vmalloc space and actual amount of RAM, you may not need this | |
1735 | option which should result in a slightly faster kernel. | |
1736 | ||
1737 | If unsure, say n. | |
1738 | ||
65cec8e3 RK |
1739 | config HIGHPTE |
1740 | bool "Allocate 2nd-level pagetables from highmem" | |
1741 | depends on HIGHMEM | |
65cec8e3 | 1742 | |
1b8873a0 JI |
1743 | config HW_PERF_EVENTS |
1744 | bool "Enable hardware performance counter support for perf events" | |
f0d1bc47 | 1745 | depends on PERF_EVENTS |
1b8873a0 JI |
1746 | default y |
1747 | help | |
1748 | Enable hardware performance counter support for perf events. If | |
1749 | disabled, perf events will use software events only. | |
1750 | ||
1355e2a6 CM |
1751 | config SYS_SUPPORTS_HUGETLBFS |
1752 | def_bool y | |
1753 | depends on ARM_LPAE | |
1754 | ||
8d962507 CM |
1755 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1756 | def_bool y | |
1757 | depends on ARM_LPAE | |
1758 | ||
3f22ab27 DH |
1759 | source "mm/Kconfig" |
1760 | ||
c1b2d970 MD |
1761 | config FORCE_MAX_ZONEORDER |
1762 | int "Maximum zone order" if ARCH_SHMOBILE | |
1763 | range 11 64 if ARCH_SHMOBILE | |
898f08e1 | 1764 | default "12" if SOC_AM33XX |
c1b2d970 MD |
1765 | default "9" if SA1111 |
1766 | default "11" | |
1767 | help | |
1768 | The kernel memory allocator divides physically contiguous memory | |
1769 | blocks into "zones", where each zone is a power of two number of | |
1770 | pages. This option selects the largest power of two that the kernel | |
1771 | keeps in the memory allocator. If you need to allocate very large | |
1772 | blocks of physically contiguous memory, then you may need to | |
1773 | increase this value. | |
1774 | ||
1775 | This config option is actually maximum order plus one. For example, | |
1776 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1777 | ||
1da177e4 LT |
1778 | config ALIGNMENT_TRAP |
1779 | bool | |
f12d0d7c | 1780 | depends on CPU_CP15_MMU |
1da177e4 | 1781 | default y if !ARCH_EBSA110 |
e119bfff | 1782 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1783 | help |
84eb8d06 | 1784 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1785 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1786 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1787 | fetch/store instructions will be emulated in software if you say | |
1788 | here, which has a severe performance impact. This is necessary for | |
1789 | correct operation of some network protocols. With an IP-only | |
1790 | configuration it is safe to say N, otherwise say Y. | |
1791 | ||
39ec58f3 | 1792 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1793 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1794 | depends on MMU | |
39ec58f3 LB |
1795 | default y if CPU_FEROCEON |
1796 | help | |
1797 | Implement faster copy_to_user and clear_user methods for CPU | |
1798 | cores where a 8-word STM instruction give significantly higher | |
1799 | memory write throughput than a sequence of individual 32bit stores. | |
1800 | ||
1801 | A possible side effect is a slight increase in scheduling latency | |
1802 | between threads sharing the same address space if they invoke | |
1803 | such copy operations with large buffers. | |
1804 | ||
1805 | However, if the CPU data cache is using a write-allocate mode, | |
1806 | this option is unlikely to provide any performance gain. | |
1807 | ||
70c70d97 NP |
1808 | config SECCOMP |
1809 | bool | |
1810 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1811 | ---help--- | |
1812 | This kernel feature is useful for number crunching applications | |
1813 | that may need to compute untrusted bytecode during their | |
1814 | execution. By using pipes or other transports made available to | |
1815 | the process as file descriptors supporting the read/write | |
1816 | syscalls, it's possible to isolate those applications in | |
1817 | their own address space using seccomp. Once seccomp is | |
1818 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1819 | and the task is only allowed to execute a few safe syscalls | |
1820 | defined by each seccomp mode. | |
1821 | ||
c743f380 NP |
1822 | config CC_STACKPROTECTOR |
1823 | bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" | |
1824 | help | |
1825 | This option turns on the -fstack-protector GCC feature. This | |
1826 | feature puts, at the beginning of functions, a canary value on | |
1827 | the stack just before the return address, and validates | |
1828 | the value just before actually returning. Stack based buffer | |
1829 | overflows (that need to overwrite this return address) now also | |
1830 | overwrite the canary, which gets detected and the attack is then | |
1831 | neutralized via a kernel panic. | |
1832 | This feature requires gcc version 4.2 or above. | |
1833 | ||
eff8d644 SS |
1834 | config XEN_DOM0 |
1835 | def_bool y | |
1836 | depends on XEN | |
1837 | ||
1838 | config XEN | |
1839 | bool "Xen guest support on ARM (EXPERIMENTAL)" | |
85323a99 | 1840 | depends on ARM && AEABI && OF |
f880b67d | 1841 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1842 | depends on !GENERIC_ATOMIC64 |
17b7ab80 | 1843 | select ARM_PSCI |
eff8d644 SS |
1844 | help |
1845 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1846 | ||
1da177e4 LT |
1847 | endmenu |
1848 | ||
1849 | menu "Boot options" | |
1850 | ||
9eb8f674 GL |
1851 | config USE_OF |
1852 | bool "Flattened Device Tree support" | |
b1b3f49c | 1853 | select IRQ_DOMAIN |
9eb8f674 GL |
1854 | select OF |
1855 | select OF_EARLY_FLATTREE | |
1856 | help | |
1857 | Include support for flattened device tree machine descriptions. | |
1858 | ||
bd51e2f5 NP |
1859 | config ATAGS |
1860 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1861 | default y | |
1862 | help | |
1863 | This is the traditional way of passing data to the kernel at boot | |
1864 | time. If you are solely relying on the flattened device tree (or | |
1865 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1866 | to remove ATAGS support from your kernel binary. If unsure, | |
1867 | leave this to y. | |
1868 | ||
1869 | config DEPRECATED_PARAM_STRUCT | |
1870 | bool "Provide old way to pass kernel parameters" | |
1871 | depends on ATAGS | |
1872 | help | |
1873 | This was deprecated in 2001 and announced to live on for 5 years. | |
1874 | Some old boot loaders still use this way. | |
1875 | ||
1da177e4 LT |
1876 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1877 | # TEXT and BSS so we preserve their values in the config files. | |
1878 | config ZBOOT_ROM_TEXT | |
1879 | hex "Compressed ROM boot loader base address" | |
1880 | default "0" | |
1881 | help | |
1882 | The physical address at which the ROM-able zImage is to be | |
1883 | placed in the target. Platforms which normally make use of | |
1884 | ROM-able zImage formats normally set this to a suitable | |
1885 | value in their defconfig file. | |
1886 | ||
1887 | If ZBOOT_ROM is not enabled, this has no effect. | |
1888 | ||
1889 | config ZBOOT_ROM_BSS | |
1890 | hex "Compressed ROM boot loader BSS address" | |
1891 | default "0" | |
1892 | help | |
f8c440b2 DF |
1893 | The base address of an area of read/write memory in the target |
1894 | for the ROM-able zImage which must be available while the | |
1895 | decompressor is running. It must be large enough to hold the | |
1896 | entire decompressed kernel plus an additional 128 KiB. | |
1897 | Platforms which normally make use of ROM-able zImage formats | |
1898 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1899 | |
1900 | If ZBOOT_ROM is not enabled, this has no effect. | |
1901 | ||
1902 | config ZBOOT_ROM | |
1903 | bool "Compressed boot loader in ROM/flash" | |
1904 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
1905 | help | |
1906 | Say Y here if you intend to execute your compressed kernel image | |
1907 | (zImage) directly from ROM or flash. If unsure, say N. | |
1908 | ||
090ab3ff SH |
1909 | choice |
1910 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1911 | depends on ZBOOT_ROM && ARCH_SH7372 |
090ab3ff SH |
1912 | default ZBOOT_ROM_NONE |
1913 | help | |
1914 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
59bf8964 | 1915 | With this enabled it is possible to write the ROM-able zImage |
090ab3ff SH |
1916 | kernel image to an MMC or SD card and boot the kernel straight |
1917 | from the reset vector. At reset the processor Mask ROM will load | |
59bf8964 | 1918 | the first part of the ROM-able zImage which in turn loads the |
090ab3ff SH |
1919 | rest the kernel image to RAM. |
1920 | ||
1921 | config ZBOOT_ROM_NONE | |
1922 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1923 | help | |
1924 | Do not load image from SD or MMC | |
1925 | ||
f45b1149 SH |
1926 | config ZBOOT_ROM_MMCIF |
1927 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
f45b1149 | 1928 | help |
090ab3ff SH |
1929 | Load image from MMCIF hardware block. |
1930 | ||
1931 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
1932 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
1933 | help | |
1934 | Load image from SDHI hardware block | |
1935 | ||
1936 | endchoice | |
f45b1149 | 1937 | |
e2a6a3aa JB |
1938 | config ARM_APPENDED_DTB |
1939 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1940 | depends on OF && !ZBOOT_ROM |
e2a6a3aa JB |
1941 | help |
1942 | With this option, the boot code will look for a device tree binary | |
1943 | (DTB) appended to zImage | |
1944 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1945 | ||
1946 | This is meant as a backward compatibility convenience for those | |
1947 | systems with a bootloader that can't be upgraded to accommodate | |
1948 | the documented boot protocol using a device tree. | |
1949 | ||
1950 | Beware that there is very little in terms of protection against | |
1951 | this option being confused by leftover garbage in memory that might | |
1952 | look like a DTB header after a reboot if no actual DTB is appended | |
1953 | to zImage. Do not leave this option active in a production kernel | |
1954 | if you don't intend to always append a DTB. Proper passing of the | |
1955 | location into r2 of a bootloader provided DTB is always preferable | |
1956 | to this option. | |
1957 | ||
b90b9a38 NP |
1958 | config ARM_ATAG_DTB_COMPAT |
1959 | bool "Supplement the appended DTB with traditional ATAG information" | |
1960 | depends on ARM_APPENDED_DTB | |
1961 | help | |
1962 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1963 | they provide ATAGs with memory configuration, the ramdisk address, | |
1964 | the kernel cmdline string, etc. Such information is dynamically | |
1965 | provided by the bootloader and can't always be stored in a static | |
1966 | DTB. To allow a device tree enabled kernel to be used with such | |
1967 | bootloaders, this option allows zImage to extract the information | |
1968 | from the ATAG list and store it at run time into the appended DTB. | |
1969 | ||
d0f34a11 GR |
1970 | choice |
1971 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1972 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1973 | ||
1974 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1975 | bool "Use bootloader kernel arguments if available" | |
1976 | help | |
1977 | Uses the command-line options passed by the boot loader instead of | |
1978 | the device tree bootargs property. If the boot loader doesn't provide | |
1979 | any, the device tree bootargs property will be used. | |
1980 | ||
1981 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1982 | bool "Extend with bootloader kernel arguments" | |
1983 | help | |
1984 | The command-line arguments provided by the boot loader will be | |
1985 | appended to the the device tree bootargs property. | |
1986 | ||
1987 | endchoice | |
1988 | ||
1da177e4 LT |
1989 | config CMDLINE |
1990 | string "Default kernel command string" | |
1991 | default "" | |
1992 | help | |
1993 | On some architectures (EBSA110 and CATS), there is currently no way | |
1994 | for the boot loader to pass arguments to the kernel. For these | |
1995 | architectures, you should supply some command-line options at build | |
1996 | time by entering them here. As a minimum, you should specify the | |
1997 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1998 | ||
4394c124 VB |
1999 | choice |
2000 | prompt "Kernel command line type" if CMDLINE != "" | |
2001 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 2002 | depends on ATAGS |
4394c124 VB |
2003 | |
2004 | config CMDLINE_FROM_BOOTLOADER | |
2005 | bool "Use bootloader kernel arguments if available" | |
2006 | help | |
2007 | Uses the command-line options passed by the boot loader. If | |
2008 | the boot loader doesn't provide any, the default kernel command | |
2009 | string provided in CMDLINE will be used. | |
2010 | ||
2011 | config CMDLINE_EXTEND | |
2012 | bool "Extend bootloader kernel arguments" | |
2013 | help | |
2014 | The command-line arguments provided by the boot loader will be | |
2015 | appended to the default kernel command string. | |
2016 | ||
92d2040d AH |
2017 | config CMDLINE_FORCE |
2018 | bool "Always use the default kernel command string" | |
92d2040d AH |
2019 | help |
2020 | Always use the default kernel command string, even if the boot | |
2021 | loader passes other arguments to the kernel. | |
2022 | This is useful if you cannot or don't want to change the | |
2023 | command-line options your boot loader passes to the kernel. | |
4394c124 | 2024 | endchoice |
92d2040d | 2025 | |
1da177e4 LT |
2026 | config XIP_KERNEL |
2027 | bool "Kernel Execute-In-Place from ROM" | |
387798b3 | 2028 | depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
2029 | help |
2030 | Execute-In-Place allows the kernel to run from non-volatile storage | |
2031 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
2032 | space since the text section of the kernel is not loaded from flash | |
2033 | to RAM. Read-write sections, such as the data section and stack, | |
2034 | are still copied to RAM. The XIP kernel is not compressed since | |
2035 | it has to run directly from flash, so it will take more space to | |
2036 | store it. The flash address used to link the kernel object files, | |
2037 | and for storing it, is configuration dependent. Therefore, if you | |
2038 | say Y here, you must know the proper physical address where to | |
2039 | store the kernel image depending on your own flash memory usage. | |
2040 | ||
2041 | Also note that the make target becomes "make xipImage" rather than | |
2042 | "make zImage" or "make Image". The final kernel binary to put in | |
2043 | ROM memory will be arch/arm/boot/xipImage. | |
2044 | ||
2045 | If unsure, say N. | |
2046 | ||
2047 | config XIP_PHYS_ADDR | |
2048 | hex "XIP Kernel Physical Location" | |
2049 | depends on XIP_KERNEL | |
2050 | default "0x00080000" | |
2051 | help | |
2052 | This is the physical address in your flash memory the kernel will | |
2053 | be linked for and stored to. This address is dependent on your | |
2054 | own flash usage. | |
2055 | ||
c587e4a6 RP |
2056 | config KEXEC |
2057 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 2058 | depends on (!SMP || PM_SLEEP_SMP) |
c587e4a6 RP |
2059 | help |
2060 | kexec is a system call that implements the ability to shutdown your | |
2061 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 2062 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
2063 | you can start any kernel with it, not just Linux. |
2064 | ||
2065 | It is an ongoing process to be certain the hardware in a machine | |
2066 | is properly shutdown, so do not be surprised if this code does not | |
2067 | initially work for you. It may help to enable device hotplugging | |
2068 | support. | |
2069 | ||
4cd9d6f7 RP |
2070 | config ATAGS_PROC |
2071 | bool "Export atags in procfs" | |
bd51e2f5 | 2072 | depends on ATAGS && KEXEC |
b98d7291 | 2073 | default y |
4cd9d6f7 RP |
2074 | help |
2075 | Should the atags used to boot the kernel be exported in an "atags" | |
2076 | file in procfs. Useful with kexec. | |
2077 | ||
cb5d39b3 MW |
2078 | config CRASH_DUMP |
2079 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2080 | help |
2081 | Generate crash dump after being started by kexec. This should | |
2082 | be normally only set in special crash dump kernels which are | |
2083 | loaded in the main kernel with kexec-tools into a specially | |
2084 | reserved region and then later executed after a crash by | |
2085 | kdump/kexec. The crash dump kernel must be compiled to a | |
2086 | memory address not used by the main kernel | |
2087 | ||
2088 | For more details see Documentation/kdump/kdump.txt | |
2089 | ||
e69edc79 EM |
2090 | config AUTO_ZRELADDR |
2091 | bool "Auto calculation of the decompressed kernel image address" | |
e1b31445 | 2092 | depends on !ZBOOT_ROM |
e69edc79 EM |
2093 | help |
2094 | ZRELADDR is the physical address where the decompressed kernel | |
2095 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2096 | will be determined at run-time by masking the current IP with | |
2097 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2098 | from start of memory. | |
2099 | ||
1da177e4 LT |
2100 | endmenu |
2101 | ||
ac9d7efc | 2102 | menu "CPU Power Management" |
1da177e4 | 2103 | |
89c52ed4 | 2104 | if ARCH_HAS_CPUFREQ |
1da177e4 | 2105 | source "drivers/cpufreq/Kconfig" |
1da177e4 LT |
2106 | endif |
2107 | ||
ac9d7efc RK |
2108 | source "drivers/cpuidle/Kconfig" |
2109 | ||
2110 | endmenu | |
2111 | ||
1da177e4 LT |
2112 | menu "Floating point emulation" |
2113 | ||
2114 | comment "At least one emulation must be selected" | |
2115 | ||
2116 | config FPE_NWFPE | |
2117 | bool "NWFPE math emulation" | |
593c252a | 2118 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2119 | ---help--- |
2120 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2121 | This is necessary to run most binaries. Linux does not currently | |
2122 | support floating point hardware so you need to say Y here even if | |
2123 | your machine has an FPA or floating point co-processor podule. | |
2124 | ||
2125 | You may say N here if you are going to load the Acorn FPEmulator | |
2126 | early in the bootup. | |
2127 | ||
2128 | config FPE_NWFPE_XP | |
2129 | bool "Support extended precision" | |
bedf142b | 2130 | depends on FPE_NWFPE |
1da177e4 LT |
2131 | help |
2132 | Say Y to include 80-bit support in the kernel floating-point | |
2133 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2134 | Note that gcc does not generate 80-bit operations by default, | |
2135 | so in most cases this option only enlarges the size of the | |
2136 | floating point emulator without any good reason. | |
2137 | ||
2138 | You almost surely want to say N here. | |
2139 | ||
2140 | config FPE_FASTFPE | |
2141 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2142 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2143 | ---help--- |
2144 | Say Y here to include the FAST floating point emulator in the kernel. | |
2145 | This is an experimental much faster emulator which now also has full | |
2146 | precision for the mantissa. It does not support any exceptions. | |
2147 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2148 | ||
2149 | It should be sufficient for most programs. It may be not suitable | |
2150 | for scientific calculations, but you have to check this for yourself. | |
2151 | If you do not feel you need a faster FP emulation you should better | |
2152 | choose NWFPE. | |
2153 | ||
2154 | config VFP | |
2155 | bool "VFP-format floating point maths" | |
e399b1a4 | 2156 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2157 | help |
2158 | Say Y to include VFP support code in the kernel. This is needed | |
2159 | if your hardware includes a VFP unit. | |
2160 | ||
2161 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2162 | release notes and additional status information. | |
2163 | ||
2164 | Say N if your target does not have VFP hardware. | |
2165 | ||
25ebee02 CM |
2166 | config VFPv3 |
2167 | bool | |
2168 | depends on VFP | |
2169 | default y if CPU_V7 | |
2170 | ||
b5872db4 CM |
2171 | config NEON |
2172 | bool "Advanced SIMD (NEON) Extension support" | |
2173 | depends on VFPv3 && CPU_V7 | |
2174 | help | |
2175 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2176 | Extension. | |
2177 | ||
1da177e4 LT |
2178 | endmenu |
2179 | ||
2180 | menu "Userspace binary formats" | |
2181 | ||
2182 | source "fs/Kconfig.binfmt" | |
2183 | ||
2184 | config ARTHUR | |
2185 | tristate "RISC OS personality" | |
704bdda0 | 2186 | depends on !AEABI |
1da177e4 LT |
2187 | help |
2188 | Say Y here to include the kernel code necessary if you want to run | |
2189 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2190 | experimental; if this sounds frightening, say N and sleep in peace. | |
2191 | You can also say M here to compile this support as a module (which | |
2192 | will be called arthur). | |
2193 | ||
2194 | endmenu | |
2195 | ||
2196 | menu "Power management options" | |
2197 | ||
eceab4ac | 2198 | source "kernel/power/Kconfig" |
1da177e4 | 2199 | |
f4cb5700 | 2200 | config ARCH_SUSPEND_POSSIBLE |
4b1082ca | 2201 | depends on !ARCH_S5PC100 |
6a786182 | 2202 | depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ |
3f5d0819 | 2203 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2204 | def_bool y |
2205 | ||
15e0d9e3 AB |
2206 | config ARM_CPU_SUSPEND |
2207 | def_bool PM_SLEEP | |
2208 | ||
1da177e4 LT |
2209 | endmenu |
2210 | ||
d5950b43 SR |
2211 | source "net/Kconfig" |
2212 | ||
ac25150f | 2213 | source "drivers/Kconfig" |
1da177e4 LT |
2214 | |
2215 | source "fs/Kconfig" | |
2216 | ||
1da177e4 LT |
2217 | source "arch/arm/Kconfig.debug" |
2218 | ||
2219 | source "security/Kconfig" | |
2220 | ||
2221 | source "crypto/Kconfig" | |
2222 | ||
2223 | source "lib/Kconfig" | |
749cf76c CD |
2224 | |
2225 | source "arch/arm/kvm/Kconfig" |