Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
b1b3f49c RK |
4 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE |
5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE | |
7563bbf8 | 6 | select ARCH_HAVE_CUSTOM_GPIO_H |
3d06770e | 7 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
b1b3f49c | 8 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 9 | select BUILDTIME_EXTABLE_SORT if MMU |
b1b3f49c | 10 | select CPU_PM if (SUSPEND || CPU_IDLE) |
39b175a0 | 11 | select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU |
4477ca45 | 12 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c RK |
13 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
14 | select GENERIC_IRQ_PROBE | |
15 | select GENERIC_IRQ_SHOW | |
b1b3f49c RK |
16 | select GENERIC_PCI_IOMAP |
17 | select GENERIC_SMP_IDLE_THREAD | |
f7b861b7 | 18 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
19 | select GENERIC_STRNCPY_FROM_USER |
20 | select GENERIC_STRNLEN_USER | |
21 | select HARDIRQS_SW_RESEND | |
22 | select HAVE_AOUT | |
09f05d85 | 23 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL |
5cbad0eb | 24 | select HAVE_ARCH_KGDB |
4095ccc3 | 25 | select HAVE_ARCH_SECCOMP_FILTER |
0693bf68 | 26 | select HAVE_ARCH_TRACEHOOK |
b1b3f49c RK |
27 | select HAVE_BPF_JIT |
28 | select HAVE_C_RECORDMCOUNT | |
29 | select HAVE_DEBUG_KMEMLEAK | |
30 | select HAVE_DMA_API_DEBUG | |
31 | select HAVE_DMA_ATTRS | |
32 | select HAVE_DMA_CONTIGUOUS if MMU | |
80be7a7f | 33 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) |
b1b3f49c | 34 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 35 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 36 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
1fe53268 | 37 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
38 | select HAVE_GENERIC_HARDIRQS |
39 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) | |
40 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 41 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 42 | select HAVE_KERNEL_GZIP |
6e8699f7 | 43 | select HAVE_KERNEL_LZMA |
b1b3f49c | 44 | select HAVE_KERNEL_LZO |
a7f464f3 | 45 | select HAVE_KERNEL_XZ |
b1b3f49c RK |
46 | select HAVE_KPROBES if !XIP_KERNEL |
47 | select HAVE_KRETPROBES if (HAVE_KPROBES) | |
48 | select HAVE_MEMBLOCK | |
49 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) | |
7ada189f | 50 | select HAVE_PERF_EVENTS |
e513f8bf | 51 | select HAVE_REGS_AND_STACK_ACCESS_API |
b1b3f49c | 52 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 53 | select HAVE_UID16 |
3d92a71a | 54 | select KTIME_SCALAR |
b1b3f49c RK |
55 | select PERF_USE_VMALLOC |
56 | select RTC_LIB | |
57 | select SYS_SUPPORTS_APM_EMULATION | |
786d35d4 DH |
58 | select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND |
59 | select MODULES_USE_ELF_REL | |
38a61b6b | 60 | select CLONE_BACKWARDS |
b68fec24 | 61 | select OLD_SIGSUSPEND3 |
50bcb7e4 | 62 | select OLD_SIGACTION |
b0088480 | 63 | select HAVE_CONTEXT_TRACKING |
1da177e4 LT |
64 | help |
65 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 66 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 67 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 68 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
69 | Europe. There is an ARM Linux project with a web page at |
70 | <http://www.arm.linux.org.uk/>. | |
71 | ||
74facffe RK |
72 | config ARM_HAS_SG_CHAIN |
73 | bool | |
74 | ||
4ce63fcd MS |
75 | config NEED_SG_DMA_LENGTH |
76 | bool | |
77 | ||
78 | config ARM_DMA_USE_IOMMU | |
4ce63fcd | 79 | bool |
b1b3f49c RK |
80 | select ARM_HAS_SG_CHAIN |
81 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 82 | |
60460abf SWK |
83 | if ARM_DMA_USE_IOMMU |
84 | ||
85 | config ARM_DMA_IOMMU_ALIGNMENT | |
86 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
87 | range 4 9 | |
88 | default 8 | |
89 | help | |
90 | DMA mapping framework by default aligns all buffers to the smallest | |
91 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
92 | size. This works well for buffers up to a few hundreds kilobytes, but | |
93 | for larger buffers it just a waste of address space. Drivers which has | |
94 | relatively small addressing window (like 64Mib) might run out of | |
95 | virtual space with just a few allocations. | |
96 | ||
97 | With this parameter you can specify the maximum PAGE_SIZE order for | |
98 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
99 | specified order. The order is expressed as a power of two multiplied | |
100 | by the PAGE_SIZE. | |
101 | ||
102 | endif | |
103 | ||
1a189b97 RK |
104 | config HAVE_PWM |
105 | bool | |
106 | ||
0b05da72 HUK |
107 | config MIGHT_HAVE_PCI |
108 | bool | |
109 | ||
75e7153a RB |
110 | config SYS_SUPPORTS_APM_EMULATION |
111 | bool | |
112 | ||
bc581770 LW |
113 | config HAVE_TCM |
114 | bool | |
115 | select GENERIC_ALLOCATOR | |
116 | ||
e119bfff RK |
117 | config HAVE_PROC_CPU |
118 | bool | |
119 | ||
5ea81769 AV |
120 | config NO_IOPORT |
121 | bool | |
5ea81769 | 122 | |
1da177e4 LT |
123 | config EISA |
124 | bool | |
125 | ---help--- | |
126 | The Extended Industry Standard Architecture (EISA) bus was | |
127 | developed as an open alternative to the IBM MicroChannel bus. | |
128 | ||
129 | The EISA bus provided some of the features of the IBM MicroChannel | |
130 | bus while maintaining backward compatibility with cards made for | |
131 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
132 | 1995 when it was made obsolete by the PCI bus. | |
133 | ||
134 | Say Y here if you are building a kernel for an EISA-based machine. | |
135 | ||
136 | Otherwise, say N. | |
137 | ||
138 | config SBUS | |
139 | bool | |
140 | ||
f16fb1ec RK |
141 | config STACKTRACE_SUPPORT |
142 | bool | |
143 | default y | |
144 | ||
f76e9154 NP |
145 | config HAVE_LATENCYTOP_SUPPORT |
146 | bool | |
147 | depends on !SMP | |
148 | default y | |
149 | ||
f16fb1ec RK |
150 | config LOCKDEP_SUPPORT |
151 | bool | |
152 | default y | |
153 | ||
7ad1bcb2 RK |
154 | config TRACE_IRQFLAGS_SUPPORT |
155 | bool | |
156 | default y | |
157 | ||
1da177e4 LT |
158 | config RWSEM_GENERIC_SPINLOCK |
159 | bool | |
160 | default y | |
161 | ||
162 | config RWSEM_XCHGADD_ALGORITHM | |
163 | bool | |
164 | ||
f0d1b0b3 DH |
165 | config ARCH_HAS_ILOG2_U32 |
166 | bool | |
f0d1b0b3 DH |
167 | |
168 | config ARCH_HAS_ILOG2_U64 | |
169 | bool | |
f0d1b0b3 | 170 | |
89c52ed4 BD |
171 | config ARCH_HAS_CPUFREQ |
172 | bool | |
173 | help | |
174 | Internal node to signify that the ARCH has CPUFREQ support | |
175 | and that the relevant menu configurations are displayed for | |
176 | it. | |
177 | ||
4a1b5733 EV |
178 | config ARCH_HAS_BANDGAP |
179 | bool | |
180 | ||
b89c3b16 AM |
181 | config GENERIC_HWEIGHT |
182 | bool | |
183 | default y | |
184 | ||
1da177e4 LT |
185 | config GENERIC_CALIBRATE_DELAY |
186 | bool | |
187 | default y | |
188 | ||
a08b6b79 Z |
189 | config ARCH_MAY_HAVE_PC_FDC |
190 | bool | |
191 | ||
5ac6da66 CL |
192 | config ZONE_DMA |
193 | bool | |
5ac6da66 | 194 | |
ccd7ab7f FT |
195 | config NEED_DMA_MAP_STATE |
196 | def_bool y | |
197 | ||
58af4a24 RH |
198 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
199 | bool | |
200 | ||
1da177e4 LT |
201 | config GENERIC_ISA_DMA |
202 | bool | |
203 | ||
1da177e4 LT |
204 | config FIQ |
205 | bool | |
206 | ||
13a5045d RH |
207 | config NEED_RET_TO_USER |
208 | bool | |
209 | ||
034d2f5a AV |
210 | config ARCH_MTD_XIP |
211 | bool | |
212 | ||
c760fc19 HC |
213 | config VECTORS_BASE |
214 | hex | |
6afd6fae | 215 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
216 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
217 | default 0x00000000 | |
218 | help | |
219 | The base address of exception vectors. | |
220 | ||
dc21af99 | 221 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
222 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
223 | default y | |
b511d75d | 224 | depends on !XIP_KERNEL && MMU |
dc21af99 RK |
225 | depends on !ARCH_REALVIEW || !SPARSEMEM |
226 | help | |
111e9a5c RK |
227 | Patch phys-to-virt and virt-to-phys translation functions at |
228 | boot and module load time according to the position of the | |
229 | kernel in system memory. | |
dc21af99 | 230 | |
111e9a5c | 231 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 232 | of physical memory is at a 16MB boundary. |
dc21af99 | 233 | |
c1becedc RK |
234 | Only disable this option if you know that you do not require |
235 | this feature (eg, building a kernel for a single machine) and | |
236 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 237 | |
01464226 RH |
238 | config NEED_MACH_GPIO_H |
239 | bool | |
240 | help | |
241 | Select this when mach/gpio.h is required to provide special | |
242 | definitions for this platform. The need for mach/gpio.h should | |
243 | be avoided when possible. | |
244 | ||
c334bc15 RH |
245 | config NEED_MACH_IO_H |
246 | bool | |
247 | help | |
248 | Select this when mach/io.h is required to provide special | |
249 | definitions for this platform. The need for mach/io.h should | |
250 | be avoided when possible. | |
251 | ||
0cdc8b92 | 252 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
253 | bool |
254 | help | |
0cdc8b92 NP |
255 | Select this when mach/memory.h is required to provide special |
256 | definitions for this platform. The need for mach/memory.h should | |
257 | be avoided when possible. | |
dc21af99 | 258 | |
1b9f95f8 | 259 | config PHYS_OFFSET |
974c0724 | 260 | hex "Physical address of main memory" if MMU |
0cdc8b92 | 261 | depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H |
974c0724 | 262 | default DRAM_BASE if !MMU |
111e9a5c | 263 | help |
1b9f95f8 NP |
264 | Please provide the physical address corresponding to the |
265 | location of main memory in your system. | |
cada3c08 | 266 | |
87e040b6 SG |
267 | config GENERIC_BUG |
268 | def_bool y | |
269 | depends on BUG | |
270 | ||
1da177e4 LT |
271 | source "init/Kconfig" |
272 | ||
dc52ddc0 MH |
273 | source "kernel/Kconfig.freezer" |
274 | ||
1da177e4 LT |
275 | menu "System Type" |
276 | ||
3c427975 HC |
277 | config MMU |
278 | bool "MMU-based Paged Memory Management Support" | |
279 | default y | |
280 | help | |
281 | Select if you want MMU-based virtualised addressing space | |
282 | support by paged memory management. If unsure, say 'Y'. | |
283 | ||
ccf50e23 RK |
284 | # |
285 | # The "ARM system type" choice list is ordered alphabetically by option | |
286 | # text. Please add new entries in the option alphabetic order. | |
287 | # | |
1da177e4 LT |
288 | choice |
289 | prompt "ARM system type" | |
1420b22b AB |
290 | default ARCH_VERSATILE if !MMU |
291 | default ARCH_MULTIPLATFORM if MMU | |
1da177e4 | 292 | |
387798b3 RH |
293 | config ARCH_MULTIPLATFORM |
294 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 295 | depends on MMU |
387798b3 RH |
296 | select ARM_PATCH_PHYS_VIRT |
297 | select AUTO_ZRELADDR | |
66314223 | 298 | select COMMON_CLK |
387798b3 | 299 | select MULTI_IRQ_HANDLER |
66314223 DN |
300 | select SPARSE_IRQ |
301 | select USE_OF | |
66314223 | 302 | |
4af6fee1 DS |
303 | config ARCH_INTEGRATOR |
304 | bool "ARM Ltd. Integrator family" | |
89c52ed4 | 305 | select ARCH_HAS_CPUFREQ |
b1b3f49c | 306 | select ARM_AMBA |
a613163d | 307 | select COMMON_CLK |
f9a6aa43 | 308 | select COMMON_CLK_VERSATILE |
b1b3f49c | 309 | select GENERIC_CLOCKEVENTS |
9904f793 | 310 | select HAVE_TCM |
c5a0adb5 | 311 | select ICST |
b1b3f49c RK |
312 | select MULTI_IRQ_HANDLER |
313 | select NEED_MACH_MEMORY_H | |
f4b8b319 | 314 | select PLAT_VERSATILE |
695436e3 | 315 | select SPARSE_IRQ |
2389d501 | 316 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
317 | help |
318 | Support for ARM's Integrator platform. | |
319 | ||
320 | config ARCH_REALVIEW | |
321 | bool "ARM Ltd. RealView family" | |
b1b3f49c | 322 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 323 | select ARM_AMBA |
b1b3f49c | 324 | select ARM_TIMER_SP804 |
f9a6aa43 LW |
325 | select COMMON_CLK |
326 | select COMMON_CLK_VERSATILE | |
ae30ceac | 327 | select GENERIC_CLOCKEVENTS |
b56ba8aa | 328 | select GPIO_PL061 if GPIOLIB |
b1b3f49c | 329 | select ICST |
0cdc8b92 | 330 | select NEED_MACH_MEMORY_H |
b1b3f49c RK |
331 | select PLAT_VERSATILE |
332 | select PLAT_VERSATILE_CLCD | |
4af6fee1 DS |
333 | help |
334 | This enables support for ARM Ltd RealView boards. | |
335 | ||
336 | config ARCH_VERSATILE | |
337 | bool "ARM Ltd. Versatile family" | |
b1b3f49c | 338 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 339 | select ARM_AMBA |
b1b3f49c | 340 | select ARM_TIMER_SP804 |
4af6fee1 | 341 | select ARM_VIC |
6d803ba7 | 342 | select CLKDEV_LOOKUP |
b1b3f49c | 343 | select GENERIC_CLOCKEVENTS |
aa3831cf | 344 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 345 | select ICST |
f4b8b319 | 346 | select PLAT_VERSATILE |
3414ba8c | 347 | select PLAT_VERSATILE_CLCD |
b1b3f49c | 348 | select PLAT_VERSATILE_CLOCK |
2389d501 | 349 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
350 | help |
351 | This enables support for ARM Ltd Versatile board. | |
352 | ||
8fc5ffa0 AV |
353 | config ARCH_AT91 |
354 | bool "Atmel AT91" | |
f373e8c0 | 355 | select ARCH_REQUIRE_GPIOLIB |
bd602995 | 356 | select CLKDEV_LOOKUP |
b1b3f49c | 357 | select HAVE_CLK |
e261501d | 358 | select IRQ_DOMAIN |
01464226 | 359 | select NEED_MACH_GPIO_H |
1ac02d79 | 360 | select NEED_MACH_IO_H if PCCARD |
6732ae5c JCPV |
361 | select PINCTRL |
362 | select PINCTRL_AT91 if USE_OF | |
4af6fee1 | 363 | help |
929e994f NF |
364 | This enables support for systems based on Atmel |
365 | AT91RM9200 and AT91SAM9* processors. | |
4af6fee1 | 366 | |
93e22567 RK |
367 | config ARCH_CLPS711X |
368 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" | |
a3b8d4a5 | 369 | select ARCH_REQUIRE_GPIOLIB |
ea7d1bc9 | 370 | select AUTO_ZRELADDR |
93e22567 | 371 | select CLKDEV_LOOKUP |
c99f72ad | 372 | select CLKSRC_MMIO |
93e22567 RK |
373 | select COMMON_CLK |
374 | select CPU_ARM720T | |
4a8355c4 | 375 | select GENERIC_CLOCKEVENTS |
6597619f | 376 | select MFD_SYSCON |
99f04c8f | 377 | select MULTI_IRQ_HANDLER |
0d8be81c | 378 | select SPARSE_IRQ |
93e22567 RK |
379 | help |
380 | Support for Cirrus Logic 711x/721x/731x based boards. | |
381 | ||
788c9700 RK |
382 | config ARCH_GEMINI |
383 | bool "Cortina Systems Gemini" | |
788c9700 | 384 | select ARCH_REQUIRE_GPIOLIB |
5cfc8ee0 | 385 | select ARCH_USES_GETTIMEOFFSET |
662146b1 | 386 | select NEED_MACH_GPIO_H |
b1b3f49c | 387 | select CPU_FA526 |
788c9700 RK |
388 | help |
389 | Support for the Cortina Systems Gemini family SoCs | |
390 | ||
1da177e4 LT |
391 | config ARCH_EBSA110 |
392 | bool "EBSA-110" | |
b1b3f49c | 393 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 394 | select CPU_SA110 |
f7e68bbf | 395 | select ISA |
c334bc15 | 396 | select NEED_MACH_IO_H |
0cdc8b92 | 397 | select NEED_MACH_MEMORY_H |
b1b3f49c | 398 | select NO_IOPORT |
1da177e4 LT |
399 | help |
400 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 401 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
402 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
403 | parallel port. | |
404 | ||
e7736d47 LB |
405 | config ARCH_EP93XX |
406 | bool "EP93xx-based" | |
b1b3f49c RK |
407 | select ARCH_HAS_HOLES_MEMORYMODEL |
408 | select ARCH_REQUIRE_GPIOLIB | |
409 | select ARCH_USES_GETTIMEOFFSET | |
e7736d47 LB |
410 | select ARM_AMBA |
411 | select ARM_VIC | |
6d803ba7 | 412 | select CLKDEV_LOOKUP |
b1b3f49c | 413 | select CPU_ARM920T |
5725aeae | 414 | select NEED_MACH_MEMORY_H |
e7736d47 LB |
415 | help |
416 | This enables support for the Cirrus EP93xx series of CPUs. | |
417 | ||
1da177e4 LT |
418 | config ARCH_FOOTBRIDGE |
419 | bool "FootBridge" | |
c750815e | 420 | select CPU_SA110 |
1da177e4 | 421 | select FOOTBRIDGE |
4e8d7637 | 422 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 423 | select HAVE_IDE |
8ef6e620 | 424 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 425 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
426 | help |
427 | Support for systems based on the DC21285 companion chip | |
428 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 429 | |
4af6fee1 DS |
430 | config ARCH_NETX |
431 | bool "Hilscher NetX based" | |
b1b3f49c | 432 | select ARM_VIC |
234b6ced | 433 | select CLKSRC_MMIO |
c750815e | 434 | select CPU_ARM926T |
2fcfe6b8 | 435 | select GENERIC_CLOCKEVENTS |
f999b8bd | 436 | help |
4af6fee1 DS |
437 | This enables support for systems based on the Hilscher NetX Soc |
438 | ||
3b938be6 RK |
439 | config ARCH_IOP13XX |
440 | bool "IOP13xx-based" | |
441 | depends on MMU | |
3b938be6 | 442 | select ARCH_SUPPORTS_MSI |
b1b3f49c | 443 | select CPU_XSC3 |
0cdc8b92 | 444 | select NEED_MACH_MEMORY_H |
13a5045d | 445 | select NEED_RET_TO_USER |
b1b3f49c RK |
446 | select PCI |
447 | select PLAT_IOP | |
448 | select VMSPLIT_1G | |
3b938be6 RK |
449 | help |
450 | Support for Intel's IOP13XX (XScale) family of processors. | |
451 | ||
3f7e5815 LB |
452 | config ARCH_IOP32X |
453 | bool "IOP32x-based" | |
a4f7e763 | 454 | depends on MMU |
b1b3f49c | 455 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 456 | select CPU_XSCALE |
01464226 | 457 | select NEED_MACH_GPIO_H |
13a5045d | 458 | select NEED_RET_TO_USER |
f7e68bbf | 459 | select PCI |
b1b3f49c | 460 | select PLAT_IOP |
f999b8bd | 461 | help |
3f7e5815 LB |
462 | Support for Intel's 80219 and IOP32X (XScale) family of |
463 | processors. | |
464 | ||
465 | config ARCH_IOP33X | |
466 | bool "IOP33x-based" | |
467 | depends on MMU | |
b1b3f49c | 468 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 469 | select CPU_XSCALE |
01464226 | 470 | select NEED_MACH_GPIO_H |
13a5045d | 471 | select NEED_RET_TO_USER |
3f7e5815 | 472 | select PCI |
b1b3f49c | 473 | select PLAT_IOP |
3f7e5815 LB |
474 | help |
475 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 476 | |
3b938be6 RK |
477 | config ARCH_IXP4XX |
478 | bool "IXP4xx-based" | |
a4f7e763 | 479 | depends on MMU |
58af4a24 | 480 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
b1b3f49c | 481 | select ARCH_REQUIRE_GPIOLIB |
234b6ced | 482 | select CLKSRC_MMIO |
c750815e | 483 | select CPU_XSCALE |
b1b3f49c | 484 | select DMABOUNCE if PCI |
3b938be6 | 485 | select GENERIC_CLOCKEVENTS |
0b05da72 | 486 | select MIGHT_HAVE_PCI |
c334bc15 | 487 | select NEED_MACH_IO_H |
9296d94d FF |
488 | select USB_EHCI_BIG_ENDIAN_MMIO |
489 | select USB_EHCI_BIG_ENDIAN_DESC | |
c4713074 | 490 | help |
3b938be6 | 491 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 492 | |
edabd38e SB |
493 | config ARCH_DOVE |
494 | bool "Marvell Dove" | |
edabd38e | 495 | select ARCH_REQUIRE_GPIOLIB |
756b2531 | 496 | select CPU_PJ4 |
edabd38e | 497 | select GENERIC_CLOCKEVENTS |
0f81bd43 | 498 | select MIGHT_HAVE_PCI |
9139acd1 SH |
499 | select PINCTRL |
500 | select PINCTRL_DOVE | |
abcda1dc | 501 | select PLAT_ORION_LEGACY |
0f81bd43 | 502 | select USB_ARCH_HAS_EHCI |
7d554902 | 503 | select MVEBU_MBUS |
edabd38e SB |
504 | help |
505 | Support for the Marvell Dove SoC 88AP510 | |
506 | ||
651c74c7 SB |
507 | config ARCH_KIRKWOOD |
508 | bool "Marvell Kirkwood" | |
0e2ee0c0 | 509 | select ARCH_HAS_CPUFREQ |
a8865655 | 510 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 511 | select CPU_FEROCEON |
651c74c7 | 512 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 513 | select PCI |
1dc831bf | 514 | select PCI_QUIRKS |
f9e75922 AL |
515 | select PINCTRL |
516 | select PINCTRL_KIRKWOOD | |
abcda1dc | 517 | select PLAT_ORION_LEGACY |
5cc0673a | 518 | select MVEBU_MBUS |
651c74c7 SB |
519 | help |
520 | Support for the following Marvell Kirkwood series SoCs: | |
521 | 88F6180, 88F6192 and 88F6281. | |
522 | ||
794d15b2 SS |
523 | config ARCH_MV78XX0 |
524 | bool "Marvell MV78xx0" | |
a8865655 | 525 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 526 | select CPU_FEROCEON |
794d15b2 | 527 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 528 | select PCI |
abcda1dc | 529 | select PLAT_ORION_LEGACY |
95b80e0a | 530 | select MVEBU_MBUS |
794d15b2 SS |
531 | help |
532 | Support for the following Marvell MV78xx0 series SoCs: | |
533 | MV781x0, MV782x0. | |
534 | ||
9dd0b194 | 535 | config ARCH_ORION5X |
585cf175 TP |
536 | bool "Marvell Orion" |
537 | depends on MMU | |
a8865655 | 538 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 539 | select CPU_FEROCEON |
51cbff1d | 540 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 541 | select PCI |
abcda1dc | 542 | select PLAT_ORION_LEGACY |
5d1190ea | 543 | select MVEBU_MBUS |
585cf175 | 544 | help |
9dd0b194 | 545 | Support for the following Marvell Orion 5x series SoCs: |
d2b2a6bb | 546 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
d323ade1 | 547 | Orion-2 (5281), Orion-1-90 (6183). |
585cf175 | 548 | |
788c9700 | 549 | config ARCH_MMP |
2f7e8fae | 550 | bool "Marvell PXA168/910/MMP2" |
788c9700 | 551 | depends on MMU |
788c9700 | 552 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 553 | select CLKDEV_LOOKUP |
b1b3f49c | 554 | select GENERIC_ALLOCATOR |
788c9700 | 555 | select GENERIC_CLOCKEVENTS |
157d2644 | 556 | select GPIO_PXA |
c24b3114 | 557 | select IRQ_DOMAIN |
b1b3f49c | 558 | select NEED_MACH_GPIO_H |
7c8f86a4 | 559 | select PINCTRL |
788c9700 | 560 | select PLAT_PXA |
0bd86961 | 561 | select SPARSE_IRQ |
788c9700 | 562 | help |
2f7e8fae | 563 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. |
788c9700 RK |
564 | |
565 | config ARCH_KS8695 | |
566 | bool "Micrel/Kendin KS8695" | |
98830bc9 | 567 | select ARCH_REQUIRE_GPIOLIB |
c7e783d6 | 568 | select CLKSRC_MMIO |
b1b3f49c | 569 | select CPU_ARM922T |
c7e783d6 | 570 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 571 | select NEED_MACH_MEMORY_H |
788c9700 RK |
572 | help |
573 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
574 | System-on-Chip devices. | |
575 | ||
788c9700 RK |
576 | config ARCH_W90X900 |
577 | bool "Nuvoton W90X900 CPU" | |
c52d3d68 | 578 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 579 | select CLKDEV_LOOKUP |
6fa5d5f7 | 580 | select CLKSRC_MMIO |
b1b3f49c | 581 | select CPU_ARM926T |
58b5369e | 582 | select GENERIC_CLOCKEVENTS |
788c9700 | 583 | help |
a8bc4ead | 584 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
585 | At present, the w90x900 has been renamed nuc900, regarding | |
586 | the ARM series product line, you can login the following | |
587 | link address to know more. | |
588 | ||
589 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
590 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 591 | |
93e22567 RK |
592 | config ARCH_LPC32XX |
593 | bool "NXP LPC32XX" | |
594 | select ARCH_REQUIRE_GPIOLIB | |
595 | select ARM_AMBA | |
596 | select CLKDEV_LOOKUP | |
597 | select CLKSRC_MMIO | |
598 | select CPU_ARM926T | |
599 | select GENERIC_CLOCKEVENTS | |
600 | select HAVE_IDE | |
601 | select HAVE_PWM | |
602 | select USB_ARCH_HAS_OHCI | |
603 | select USE_OF | |
604 | help | |
605 | Support for the NXP LPC32XX family of processors | |
606 | ||
1da177e4 | 607 | config ARCH_PXA |
2c8086a5 | 608 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 609 | depends on MMU |
89c52ed4 | 610 | select ARCH_HAS_CPUFREQ |
b1b3f49c RK |
611 | select ARCH_MTD_XIP |
612 | select ARCH_REQUIRE_GPIOLIB | |
613 | select ARM_CPU_SUSPEND if PM | |
614 | select AUTO_ZRELADDR | |
6d803ba7 | 615 | select CLKDEV_LOOKUP |
234b6ced | 616 | select CLKSRC_MMIO |
981d0f39 | 617 | select GENERIC_CLOCKEVENTS |
157d2644 | 618 | select GPIO_PXA |
d0ee9f40 | 619 | select HAVE_IDE |
b1b3f49c | 620 | select MULTI_IRQ_HANDLER |
01464226 | 621 | select NEED_MACH_GPIO_H |
b1b3f49c RK |
622 | select PLAT_PXA |
623 | select SPARSE_IRQ | |
f999b8bd | 624 | help |
2c8086a5 | 625 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 | 626 | |
788c9700 RK |
627 | config ARCH_MSM |
628 | bool "Qualcomm MSM" | |
923a081c | 629 | select ARCH_REQUIRE_GPIOLIB |
bd32344a | 630 | select CLKDEV_LOOKUP |
8cc7f533 | 631 | select COMMON_CLK |
b1b3f49c | 632 | select GENERIC_CLOCKEVENTS |
49cbe786 | 633 | help |
4b53eb4f DW |
634 | Support for Qualcomm MSM/QSD based systems. This runs on the |
635 | apps processor of the MSM/QSD and depends on a shared memory | |
636 | interface to the modem processor which runs the baseband | |
637 | stack and controls some vital subsystems | |
638 | (clock and power control, etc). | |
49cbe786 | 639 | |
c793c1b0 | 640 | config ARCH_SHMOBILE |
6d72ad35 | 641 | bool "Renesas SH-Mobile / R-Mobile" |
69469995 | 642 | select ARM_PATCH_PHYS_VIRT |
5e93c6b4 | 643 | select CLKDEV_LOOKUP |
b1b3f49c | 644 | select GENERIC_CLOCKEVENTS |
4c3ffffd SB |
645 | select HAVE_ARM_SCU if SMP |
646 | select HAVE_ARM_TWD if LOCAL_TIMERS | |
b1b3f49c | 647 | select HAVE_CLK |
aa3831cf | 648 | select HAVE_MACH_CLKDEV |
3b55658a | 649 | select HAVE_SMP |
ce5ea9f3 | 650 | select MIGHT_HAVE_CACHE_L2X0 |
60f1435c | 651 | select MULTI_IRQ_HANDLER |
b1b3f49c | 652 | select NO_IOPORT |
2cd3c927 | 653 | select PINCTRL |
b1b3f49c RK |
654 | select PM_GENERIC_DOMAINS if PM |
655 | select SPARSE_IRQ | |
c793c1b0 | 656 | help |
6d72ad35 | 657 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms. |
c793c1b0 | 658 | |
1da177e4 LT |
659 | config ARCH_RPC |
660 | bool "RiscPC" | |
661 | select ARCH_ACORN | |
a08b6b79 | 662 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 663 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 664 | select ARCH_USES_GETTIMEOFFSET |
b1b3f49c | 665 | select FIQ |
d0ee9f40 | 666 | select HAVE_IDE |
b1b3f49c RK |
667 | select HAVE_PATA_PLATFORM |
668 | select ISA_DMA_API | |
c334bc15 | 669 | select NEED_MACH_IO_H |
0cdc8b92 | 670 | select NEED_MACH_MEMORY_H |
b1b3f49c | 671 | select NO_IOPORT |
b4811bac | 672 | select VIRT_TO_BUS |
1da177e4 LT |
673 | help |
674 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
675 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
676 | ||
677 | config ARCH_SA1100 | |
678 | bool "SA1100-based" | |
89c52ed4 | 679 | select ARCH_HAS_CPUFREQ |
b1b3f49c RK |
680 | select ARCH_MTD_XIP |
681 | select ARCH_REQUIRE_GPIOLIB | |
682 | select ARCH_SPARSEMEM_ENABLE | |
683 | select CLKDEV_LOOKUP | |
684 | select CLKSRC_MMIO | |
1937f5b9 | 685 | select CPU_FREQ |
b1b3f49c | 686 | select CPU_SA1100 |
3e238be2 | 687 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 688 | select HAVE_IDE |
b1b3f49c | 689 | select ISA |
01464226 | 690 | select NEED_MACH_GPIO_H |
0cdc8b92 | 691 | select NEED_MACH_MEMORY_H |
375dec92 | 692 | select SPARSE_IRQ |
f999b8bd MM |
693 | help |
694 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 695 | |
b130d5c2 KK |
696 | config ARCH_S3C24XX |
697 | bool "Samsung S3C24XX SoCs" | |
9d56c02a | 698 | select ARCH_HAS_CPUFREQ |
53650430 | 699 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 700 | select CLKDEV_LOOKUP |
7f78b6eb RN |
701 | select CLKSRC_MMIO |
702 | select GENERIC_CLOCKEVENTS | |
880cf071 | 703 | select GPIO_SAMSUNG |
b1b3f49c | 704 | select HAVE_CLK |
20676c15 | 705 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 706 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 707 | select HAVE_S3C_RTC if RTC_CLASS |
17453dd2 | 708 | select MULTI_IRQ_HANDLER |
01464226 | 709 | select NEED_MACH_GPIO_H |
c334bc15 | 710 | select NEED_MACH_IO_H |
cd8dc7ae | 711 | select SAMSUNG_ATAGS |
1da177e4 | 712 | help |
b130d5c2 KK |
713 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
714 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
715 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
716 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 717 | |
a08ab637 BD |
718 | config ARCH_S3C64XX |
719 | bool "Samsung S3C64XX" | |
b1b3f49c RK |
720 | select ARCH_HAS_CPUFREQ |
721 | select ARCH_REQUIRE_GPIOLIB | |
89f0ce72 | 722 | select ARM_VIC |
b1b3f49c | 723 | select CLKDEV_LOOKUP |
04a49b71 | 724 | select CLKSRC_MMIO |
b1b3f49c | 725 | select CPU_V6 |
04a49b71 | 726 | select GENERIC_CLOCKEVENTS |
880cf071 | 727 | select GPIO_SAMSUNG |
a08ab637 | 728 | select HAVE_CLK |
b1b3f49c RK |
729 | select HAVE_S3C2410_I2C if I2C |
730 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
6700397a | 731 | select HAVE_TCM |
b1b3f49c | 732 | select NEED_MACH_GPIO_H |
89f0ce72 | 733 | select NO_IOPORT |
b1b3f49c RK |
734 | select PLAT_SAMSUNG |
735 | select S3C_DEV_NAND | |
736 | select S3C_GPIO_TRACK | |
cd8dc7ae | 737 | select SAMSUNG_ATAGS |
89f0ce72 | 738 | select SAMSUNG_CLKSRC |
b1b3f49c | 739 | select SAMSUNG_GPIOLIB_4BIT |
89f0ce72 | 740 | select SAMSUNG_IRQ_VIC_TIMER |
88f59738 | 741 | select SAMSUNG_WDT_RESET |
89f0ce72 | 742 | select USB_ARCH_HAS_OHCI |
a08ab637 BD |
743 | help |
744 | Samsung S3C64XX series based systems | |
745 | ||
49b7a491 KK |
746 | config ARCH_S5P64X0 |
747 | bool "Samsung S5P6440 S5P6450" | |
d8b22d25 | 748 | select CLKDEV_LOOKUP |
0665ccc4 | 749 | select CLKSRC_MMIO |
b1b3f49c | 750 | select CPU_V6 |
9e65bbf2 | 751 | select GENERIC_CLOCKEVENTS |
880cf071 | 752 | select GPIO_SAMSUNG |
b1b3f49c | 753 | select HAVE_CLK |
20676c15 | 754 | select HAVE_S3C2410_I2C if I2C |
b1b3f49c | 755 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
754961a8 | 756 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 757 | select NEED_MACH_GPIO_H |
88f59738 | 758 | select SAMSUNG_WDT_RESET |
cd8dc7ae | 759 | select SAMSUNG_ATAGS |
c4ffccdd | 760 | help |
49b7a491 KK |
761 | Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, |
762 | SMDK6450. | |
c4ffccdd | 763 | |
acc84707 MS |
764 | config ARCH_S5PC100 |
765 | bool "Samsung S5PC100" | |
53650430 | 766 | select ARCH_REQUIRE_GPIOLIB |
29e8eb0f | 767 | select CLKDEV_LOOKUP |
6a5a2e3b | 768 | select CLKSRC_MMIO |
5a7652f2 | 769 | select CPU_V7 |
6a5a2e3b | 770 | select GENERIC_CLOCKEVENTS |
880cf071 | 771 | select GPIO_SAMSUNG |
b1b3f49c | 772 | select HAVE_CLK |
20676c15 | 773 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 774 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 775 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 776 | select NEED_MACH_GPIO_H |
88f59738 | 777 | select SAMSUNG_WDT_RESET |
cd8dc7ae | 778 | select SAMSUNG_ATAGS |
5a7652f2 | 779 | help |
acc84707 | 780 | Samsung S5PC100 series based systems |
5a7652f2 | 781 | |
170f4e42 KK |
782 | config ARCH_S5PV210 |
783 | bool "Samsung S5PV210/S5PC110" | |
b1b3f49c | 784 | select ARCH_HAS_CPUFREQ |
0f75a96b | 785 | select ARCH_HAS_HOLES_MEMORYMODEL |
b1b3f49c | 786 | select ARCH_SPARSEMEM_ENABLE |
b2a9dd46 | 787 | select CLKDEV_LOOKUP |
0665ccc4 | 788 | select CLKSRC_MMIO |
b1b3f49c | 789 | select CPU_V7 |
9e65bbf2 | 790 | select GENERIC_CLOCKEVENTS |
880cf071 | 791 | select GPIO_SAMSUNG |
b1b3f49c | 792 | select HAVE_CLK |
20676c15 | 793 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 794 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 795 | select HAVE_S3C_RTC if RTC_CLASS |
01464226 | 796 | select NEED_MACH_GPIO_H |
0cdc8b92 | 797 | select NEED_MACH_MEMORY_H |
cd8dc7ae | 798 | select SAMSUNG_ATAGS |
170f4e42 KK |
799 | help |
800 | Samsung S5PV210/S5PC110 series based systems | |
801 | ||
83014579 | 802 | config ARCH_EXYNOS |
93e22567 | 803 | bool "Samsung EXYNOS" |
b1b3f49c | 804 | select ARCH_HAS_CPUFREQ |
0f75a96b | 805 | select ARCH_HAS_HOLES_MEMORYMODEL |
e245f969 | 806 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 807 | select ARCH_SPARSEMEM_ENABLE |
e245f969 | 808 | select ARM_GIC |
badc4f2d | 809 | select CLKDEV_LOOKUP |
340fcb5c | 810 | select COMMON_CLK |
b1b3f49c | 811 | select CPU_V7 |
cc0e72b8 | 812 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 813 | select HAVE_CLK |
20676c15 | 814 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 815 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 816 | select HAVE_S3C_RTC if RTC_CLASS |
0cdc8b92 | 817 | select NEED_MACH_MEMORY_H |
6e726ea4 | 818 | select SPARSE_IRQ |
f8b1ac01 | 819 | select USE_OF |
cc0e72b8 | 820 | help |
83014579 | 821 | Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) |
cc0e72b8 | 822 | |
1da177e4 LT |
823 | config ARCH_SHARK |
824 | bool "Shark" | |
b1b3f49c | 825 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 826 | select CPU_SA110 |
f7e68bbf RK |
827 | select ISA |
828 | select ISA_DMA | |
0cdc8b92 | 829 | select NEED_MACH_MEMORY_H |
b1b3f49c | 830 | select PCI |
b4811bac | 831 | select VIRT_TO_BUS |
b1b3f49c | 832 | select ZONE_DMA |
f999b8bd MM |
833 | help |
834 | Support for the StrongARM based Digital DNARD machine, also known | |
835 | as "Shark" (<http://www.shark-linux.de/shark.html>). | |
1da177e4 | 836 | |
7c6337e2 KH |
837 | config ARCH_DAVINCI |
838 | bool "TI DaVinci" | |
b1b3f49c | 839 | select ARCH_HAS_HOLES_MEMORYMODEL |
dce1115b | 840 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 841 | select CLKDEV_LOOKUP |
20e9969b | 842 | select GENERIC_ALLOCATOR |
b1b3f49c | 843 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 844 | select GENERIC_IRQ_CHIP |
b1b3f49c | 845 | select HAVE_IDE |
01464226 | 846 | select NEED_MACH_GPIO_H |
3ad7a42d | 847 | select TI_PRIV_EDMA |
689e331f | 848 | select USE_OF |
b1b3f49c | 849 | select ZONE_DMA |
7c6337e2 KH |
850 | help |
851 | Support for TI's DaVinci platform. | |
852 | ||
a0694861 TL |
853 | config ARCH_OMAP1 |
854 | bool "TI OMAP1" | |
00a36698 | 855 | depends on MMU |
89c52ed4 | 856 | select ARCH_HAS_CPUFREQ |
9af915da | 857 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 858 | select ARCH_OMAP |
21f47fbc | 859 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 860 | select CLKDEV_LOOKUP |
d6e15d78 | 861 | select CLKSRC_MMIO |
b1b3f49c | 862 | select GENERIC_CLOCKEVENTS |
a0694861 | 863 | select GENERIC_IRQ_CHIP |
e9a91de7 | 864 | select HAVE_CLK |
a0694861 TL |
865 | select HAVE_IDE |
866 | select IRQ_DOMAIN | |
867 | select NEED_MACH_IO_H if PCCARD | |
868 | select NEED_MACH_MEMORY_H | |
21f47fbc | 869 | help |
a0694861 | 870 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 871 | |
1da177e4 LT |
872 | endchoice |
873 | ||
387798b3 RH |
874 | menu "Multiple platform selection" |
875 | depends on ARCH_MULTIPLATFORM | |
876 | ||
877 | comment "CPU Core family selection" | |
878 | ||
387798b3 RH |
879 | config ARCH_MULTI_V4T |
880 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 881 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 882 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
883 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
884 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
885 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
886 | |
887 | config ARCH_MULTI_V5 | |
888 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 889 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 890 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
891 | select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ |
892 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ | |
893 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
894 | |
895 | config ARCH_MULTI_V4_V5 | |
896 | bool | |
897 | ||
898 | config ARCH_MULTI_V6 | |
8dda05cc | 899 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 900 | select ARCH_MULTI_V6_V7 |
b1b3f49c | 901 | select CPU_V6 |
387798b3 RH |
902 | |
903 | config ARCH_MULTI_V7 | |
8dda05cc | 904 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
905 | default y |
906 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 907 | select CPU_V7 |
387798b3 RH |
908 | |
909 | config ARCH_MULTI_V6_V7 | |
910 | bool | |
911 | ||
912 | config ARCH_MULTI_CPU_AUTO | |
913 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
914 | select ARCH_MULTI_V5 | |
915 | ||
916 | endmenu | |
917 | ||
ccf50e23 RK |
918 | # |
919 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
920 | # Kconfigs may be included either alphabetically (according to the | |
921 | # plat- suffix) or along side the corresponding mach-* source. | |
922 | # | |
3e93a22b GC |
923 | source "arch/arm/mach-mvebu/Kconfig" |
924 | ||
95b8f20f RK |
925 | source "arch/arm/mach-at91/Kconfig" |
926 | ||
8ac49e04 CD |
927 | source "arch/arm/mach-bcm/Kconfig" |
928 | ||
f1ac922d SW |
929 | source "arch/arm/mach-bcm2835/Kconfig" |
930 | ||
1da177e4 LT |
931 | source "arch/arm/mach-clps711x/Kconfig" |
932 | ||
d94f944e AV |
933 | source "arch/arm/mach-cns3xxx/Kconfig" |
934 | ||
95b8f20f RK |
935 | source "arch/arm/mach-davinci/Kconfig" |
936 | ||
937 | source "arch/arm/mach-dove/Kconfig" | |
938 | ||
e7736d47 LB |
939 | source "arch/arm/mach-ep93xx/Kconfig" |
940 | ||
1da177e4 LT |
941 | source "arch/arm/mach-footbridge/Kconfig" |
942 | ||
59d3a193 PZ |
943 | source "arch/arm/mach-gemini/Kconfig" |
944 | ||
387798b3 RH |
945 | source "arch/arm/mach-highbank/Kconfig" |
946 | ||
1da177e4 LT |
947 | source "arch/arm/mach-integrator/Kconfig" |
948 | ||
3f7e5815 LB |
949 | source "arch/arm/mach-iop32x/Kconfig" |
950 | ||
951 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 952 | |
285f5fa7 DW |
953 | source "arch/arm/mach-iop13xx/Kconfig" |
954 | ||
1da177e4 LT |
955 | source "arch/arm/mach-ixp4xx/Kconfig" |
956 | ||
828989ad SS |
957 | source "arch/arm/mach-keystone/Kconfig" |
958 | ||
95b8f20f RK |
959 | source "arch/arm/mach-kirkwood/Kconfig" |
960 | ||
961 | source "arch/arm/mach-ks8695/Kconfig" | |
962 | ||
95b8f20f RK |
963 | source "arch/arm/mach-msm/Kconfig" |
964 | ||
794d15b2 SS |
965 | source "arch/arm/mach-mv78xx0/Kconfig" |
966 | ||
3995eb82 | 967 | source "arch/arm/mach-imx/Kconfig" |
1da177e4 | 968 | |
1d3f33d5 SG |
969 | source "arch/arm/mach-mxs/Kconfig" |
970 | ||
95b8f20f | 971 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 972 | |
95b8f20f | 973 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 974 | |
9851ca57 DT |
975 | source "arch/arm/mach-nspire/Kconfig" |
976 | ||
d48af15e TL |
977 | source "arch/arm/plat-omap/Kconfig" |
978 | ||
979 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 980 | |
1dbae815 TL |
981 | source "arch/arm/mach-omap2/Kconfig" |
982 | ||
9dd0b194 | 983 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 984 | |
387798b3 RH |
985 | source "arch/arm/mach-picoxcell/Kconfig" |
986 | ||
95b8f20f RK |
987 | source "arch/arm/mach-pxa/Kconfig" |
988 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 989 | |
95b8f20f RK |
990 | source "arch/arm/mach-mmp/Kconfig" |
991 | ||
992 | source "arch/arm/mach-realview/Kconfig" | |
993 | ||
d63dc051 HS |
994 | source "arch/arm/mach-rockchip/Kconfig" |
995 | ||
95b8f20f | 996 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 997 | |
cf383678 | 998 | source "arch/arm/plat-samsung/Kconfig" |
a21765a7 | 999 | |
387798b3 RH |
1000 | source "arch/arm/mach-socfpga/Kconfig" |
1001 | ||
a7ed099f | 1002 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 1003 | |
65ebcc11 SK |
1004 | source "arch/arm/mach-sti/Kconfig" |
1005 | ||
85fd6d63 | 1006 | source "arch/arm/mach-s3c24xx/Kconfig" |
1da177e4 | 1007 | |
a08ab637 | 1008 | if ARCH_S3C64XX |
431107ea | 1009 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 BD |
1010 | endif |
1011 | ||
49b7a491 | 1012 | source "arch/arm/mach-s5p64x0/Kconfig" |
c4ffccdd | 1013 | |
5a7652f2 | 1014 | source "arch/arm/mach-s5pc100/Kconfig" |
5a7652f2 | 1015 | |
170f4e42 KK |
1016 | source "arch/arm/mach-s5pv210/Kconfig" |
1017 | ||
83014579 | 1018 | source "arch/arm/mach-exynos/Kconfig" |
cc0e72b8 | 1019 | |
882d01f9 | 1020 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 1021 | |
3b52634f MR |
1022 | source "arch/arm/mach-sunxi/Kconfig" |
1023 | ||
156a0997 BS |
1024 | source "arch/arm/mach-prima2/Kconfig" |
1025 | ||
c5f80065 EG |
1026 | source "arch/arm/mach-tegra/Kconfig" |
1027 | ||
95b8f20f | 1028 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 1029 | |
95b8f20f | 1030 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
1031 | |
1032 | source "arch/arm/mach-versatile/Kconfig" | |
1033 | ||
ceade897 | 1034 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 1035 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 1036 | |
2a0ba738 MZ |
1037 | source "arch/arm/mach-virt/Kconfig" |
1038 | ||
6f35f9a9 TP |
1039 | source "arch/arm/mach-vt8500/Kconfig" |
1040 | ||
7ec80ddf | 1041 | source "arch/arm/mach-w90x900/Kconfig" |
1042 | ||
9a45eb69 JC |
1043 | source "arch/arm/mach-zynq/Kconfig" |
1044 | ||
1da177e4 LT |
1045 | # Definitions to make life easier |
1046 | config ARCH_ACORN | |
1047 | bool | |
1048 | ||
7ae1f7ec LB |
1049 | config PLAT_IOP |
1050 | bool | |
469d3044 | 1051 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 1052 | |
69b02f6a LB |
1053 | config PLAT_ORION |
1054 | bool | |
bfe45e0b | 1055 | select CLKSRC_MMIO |
b1b3f49c | 1056 | select COMMON_CLK |
dc7ad3b3 | 1057 | select GENERIC_IRQ_CHIP |
278b45b0 | 1058 | select IRQ_DOMAIN |
69b02f6a | 1059 | |
abcda1dc TP |
1060 | config PLAT_ORION_LEGACY |
1061 | bool | |
1062 | select PLAT_ORION | |
1063 | ||
bd5ce433 EM |
1064 | config PLAT_PXA |
1065 | bool | |
1066 | ||
f4b8b319 RK |
1067 | config PLAT_VERSATILE |
1068 | bool | |
1069 | ||
e3887714 RK |
1070 | config ARM_TIMER_SP804 |
1071 | bool | |
bfe45e0b | 1072 | select CLKSRC_MMIO |
7a0eca71 | 1073 | select CLKSRC_OF if OF |
e3887714 | 1074 | |
1da177e4 LT |
1075 | source arch/arm/mm/Kconfig |
1076 | ||
958cab0f RK |
1077 | config ARM_NR_BANKS |
1078 | int | |
1079 | default 16 if ARCH_EP93XX | |
1080 | default 8 | |
1081 | ||
afe4b25e | 1082 | config IWMMXT |
698613b6 | 1083 | bool "Enable iWMMXt support" if !CPU_PJ4 |
ef6c8445 | 1084 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 |
698613b6 | 1085 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 |
afe4b25e LB |
1086 | help |
1087 | Enable support for iWMMXt context switching at run time if | |
1088 | running on a CPU that supports it. | |
1089 | ||
1da177e4 LT |
1090 | config XSCALE_PMU |
1091 | bool | |
bfc994b5 | 1092 | depends on CPU_XSCALE |
1da177e4 LT |
1093 | default y |
1094 | ||
52108641 | 1095 | config MULTI_IRQ_HANDLER |
1096 | bool | |
1097 | help | |
1098 | Allow each machine to specify it's own IRQ handler at run time. | |
1099 | ||
3b93e7b0 HC |
1100 | if !MMU |
1101 | source "arch/arm/Kconfig-nommu" | |
1102 | endif | |
1103 | ||
3e0a07f8 GC |
1104 | config PJ4B_ERRATA_4742 |
1105 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
1106 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
1107 | default y | |
1108 | help | |
1109 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
1110 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
1111 | the retiring WFI/WFE instructions and the newly issued subsequent | |
1112 | instructions. This sensitivity can result in a CPU hang scenario. | |
1113 | Workaround: | |
1114 | The software must insert either a Data Synchronization Barrier (DSB) | |
1115 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
1116 | instruction | |
1117 | ||
f0c4b8d6 WD |
1118 | config ARM_ERRATA_326103 |
1119 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
1120 | depends on CPU_V6 | |
1121 | help | |
1122 | Executing a SWP instruction to read-only memory does not set bit 11 | |
1123 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
1124 | treat the access as a read, preventing a COW from occurring and | |
1125 | causing the faulting task to livelock. | |
1126 | ||
9cba3ccc CM |
1127 | config ARM_ERRATA_411920 |
1128 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 1129 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
1130 | help |
1131 | Invalidation of the Instruction Cache operation can | |
1132 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1133 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1134 | recommended workaround. | |
1135 | ||
7ce236fc CM |
1136 | config ARM_ERRATA_430973 |
1137 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1138 | depends on CPU_V7 | |
1139 | help | |
1140 | This option enables the workaround for the 430973 Cortex-A8 | |
1141 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1142 | interworking branch is replaced with another code sequence at the | |
1143 | same virtual address, whether due to self-modifying code or virtual | |
1144 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1145 | stale interworking branch prediction. This results in Cortex-A8 | |
1146 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1147 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1148 | and also flushes the branch target cache at every context switch. | |
1149 | Note that setting specific bits in the ACTLR register may not be | |
1150 | available in non-secure mode. | |
1151 | ||
855c551f CM |
1152 | config ARM_ERRATA_458693 |
1153 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1154 | depends on CPU_V7 | |
62e4d357 | 1155 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
1156 | help |
1157 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1158 | erratum. For very specific sequences of memory operations, it is | |
1159 | possible for a hazard condition intended for a cache line to instead | |
1160 | be incorrectly associated with a different cache line. This false | |
1161 | hazard might then cause a processor deadlock. The workaround enables | |
1162 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1163 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1164 | register may not be available in non-secure mode. | |
1165 | ||
0516e464 CM |
1166 | config ARM_ERRATA_460075 |
1167 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1168 | depends on CPU_V7 | |
62e4d357 | 1169 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
1170 | help |
1171 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1172 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1173 | situation in which recent store transactions to the L2 cache are lost | |
1174 | and overwritten with stale memory contents from external memory. The | |
1175 | workaround disables the write-allocate mode for the L2 cache via the | |
1176 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1177 | may not be available in non-secure mode. | |
1178 | ||
9f05027c WD |
1179 | config ARM_ERRATA_742230 |
1180 | bool "ARM errata: DMB operation may be faulty" | |
1181 | depends on CPU_V7 && SMP | |
62e4d357 | 1182 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1183 | help |
1184 | This option enables the workaround for the 742230 Cortex-A9 | |
1185 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1186 | between two write operations may not ensure the correct visibility | |
1187 | ordering of the two writes. This workaround sets a specific bit in | |
1188 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1189 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1190 | the two writes. | |
1191 | ||
a672e99b WD |
1192 | config ARM_ERRATA_742231 |
1193 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1194 | depends on CPU_V7 && SMP | |
62e4d357 | 1195 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1196 | help |
1197 | This option enables the workaround for the 742231 Cortex-A9 | |
1198 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1199 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1200 | accessing some data located in the same cache line, may get corrupted | |
1201 | data due to bad handling of the address hazard when the line gets | |
1202 | replaced from one of the CPUs at the same time as another CPU is | |
1203 | accessing it. This workaround sets specific bits in the diagnostic | |
1204 | register of the Cortex-A9 which reduces the linefill issuing | |
1205 | capabilities of the processor. | |
1206 | ||
9e65582a | 1207 | config PL310_ERRATA_588369 |
fa0ce403 | 1208 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" |
2839e06c | 1209 | depends on CACHE_L2X0 |
9e65582a SS |
1210 | help |
1211 | The PL310 L2 cache controller implements three types of Clean & | |
1212 | Invalidate maintenance operations: by Physical Address | |
1213 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
1214 | They are architecturally defined to behave as the execution of a | |
1215 | clean operation followed immediately by an invalidate operation, | |
1216 | both performing to the same memory location. This functionality | |
1217 | is not correctly implemented in PL310 as clean lines are not | |
2839e06c | 1218 | invalidated as a result of these operations. |
cdf357f1 | 1219 | |
69155794 JM |
1220 | config ARM_ERRATA_643719 |
1221 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1222 | depends on CPU_V7 && SMP | |
1223 | help | |
1224 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1225 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1226 | register returns zero when it should return one. The workaround | |
1227 | corrects this value, ensuring cache maintenance operations which use | |
1228 | it behave as intended and avoiding data corruption. | |
1229 | ||
cdf357f1 WD |
1230 | config ARM_ERRATA_720789 |
1231 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1232 | depends on CPU_V7 |
cdf357f1 WD |
1233 | help |
1234 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1235 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1236 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1237 | As a consequence of this erratum, some TLB entries which should be | |
1238 | invalidated are not, resulting in an incoherency in the system page | |
1239 | tables. The workaround changes the TLB flushing routines to invalidate | |
1240 | entries regardless of the ASID. | |
475d92fc | 1241 | |
1f0090a1 | 1242 | config PL310_ERRATA_727915 |
fa0ce403 | 1243 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" |
1f0090a1 RK |
1244 | depends on CACHE_L2X0 |
1245 | help | |
1246 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
1247 | operation (offset 0x7FC). This operation runs in background so that | |
1248 | PL310 can handle normal accesses while it is in progress. Under very | |
1249 | rare circumstances, due to this erratum, write data can be lost when | |
1250 | PL310 treats a cacheable write transaction during a Clean & | |
1251 | Invalidate by Way operation. | |
1252 | ||
475d92fc WD |
1253 | config ARM_ERRATA_743622 |
1254 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1255 | depends on CPU_V7 | |
62e4d357 | 1256 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1257 | help |
1258 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1259 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1260 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1261 | corruption. This workaround sets a specific bit in the diagnostic | |
1262 | register of the Cortex-A9 which disables the Store Buffer | |
1263 | optimisation, preventing the defect from occurring. This has no | |
1264 | visible impact on the overall performance or power consumption of the | |
1265 | processor. | |
1266 | ||
9a27c27c WD |
1267 | config ARM_ERRATA_751472 |
1268 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1269 | depends on CPU_V7 |
62e4d357 | 1270 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1271 | help |
1272 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1273 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1274 | completion of a following broadcasted operation if the second | |
1275 | operation is received by a CPU before the ICIALLUIS has completed, | |
1276 | potentially leading to corrupted entries in the cache or TLB. | |
1277 | ||
fa0ce403 WD |
1278 | config PL310_ERRATA_753970 |
1279 | bool "PL310 errata: cache sync operation may be faulty" | |
885028e4 SK |
1280 | depends on CACHE_PL310 |
1281 | help | |
1282 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
1283 | ||
1284 | Under some condition the effect of cache sync operation on | |
1285 | the store buffer still remains when the operation completes. | |
1286 | This means that the store buffer is always asked to drain and | |
1287 | this prevents it from merging any further writes. The workaround | |
1288 | is to replace the normal offset of cache sync operation (0x730) | |
1289 | by another offset targeting an unmapped PL310 register 0x740. | |
1290 | This has the same effect as the cache sync operation: store buffer | |
1291 | drain and waiting for all buffers empty. | |
1292 | ||
fcbdc5fe WD |
1293 | config ARM_ERRATA_754322 |
1294 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1295 | depends on CPU_V7 | |
1296 | help | |
1297 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1298 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1299 | which starts prior to an ASID switch but completes afterwards. This | |
1300 | can populate the micro-TLB with a stale entry which may be hit with | |
1301 | the new ASID. This workaround places two dsb instructions in the mm | |
1302 | switching code so that no page table walks can cross the ASID switch. | |
1303 | ||
5dab26af WD |
1304 | config ARM_ERRATA_754327 |
1305 | bool "ARM errata: no automatic Store Buffer drain" | |
1306 | depends on CPU_V7 && SMP | |
1307 | help | |
1308 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1309 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1310 | mechanism and therefore a livelock may occur if an external agent | |
1311 | continuously polls a memory location waiting to observe an update. | |
1312 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1313 | written polling loops from denying visibility of updates to memory. | |
1314 | ||
145e10e1 CM |
1315 | config ARM_ERRATA_364296 |
1316 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
1317 | depends on CPU_V6 && !SMP | |
1318 | help | |
1319 | This options enables the workaround for the 364296 ARM1136 | |
1320 | r0p2 erratum (possible cache data corruption with | |
1321 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1322 | the auxiliary control register and the FI bit in the control | |
1323 | register, thus disabling hit-under-miss without putting the | |
1324 | processor into full low interrupt latency mode. ARM11MPCore | |
1325 | is not affected. | |
1326 | ||
f630c1bd WD |
1327 | config ARM_ERRATA_764369 |
1328 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1329 | depends on CPU_V7 && SMP | |
1330 | help | |
1331 | This option enables the workaround for erratum 764369 | |
1332 | affecting Cortex-A9 MPCore with two or more processors (all | |
1333 | current revisions). Under certain timing circumstances, a data | |
1334 | cache line maintenance operation by MVA targeting an Inner | |
1335 | Shareable memory region may fail to proceed up to either the | |
1336 | Point of Coherency or to the Point of Unification of the | |
1337 | system. This workaround adds a DSB instruction before the | |
1338 | relevant cache maintenance functions and sets a specific bit | |
1339 | in the diagnostic control register of the SCU. | |
1340 | ||
11ed0ba1 WD |
1341 | config PL310_ERRATA_769419 |
1342 | bool "PL310 errata: no automatic Store Buffer drain" | |
1343 | depends on CACHE_L2X0 | |
1344 | help | |
1345 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
1346 | not automatically drain. This can cause normal, non-cacheable | |
1347 | writes to be retained when the memory system is idle, leading | |
1348 | to suboptimal I/O performance for drivers using coherent DMA. | |
1349 | This option adds a write barrier to the cpu_idle loop so that, | |
1350 | on systems with an outer cache, the store buffer is drained | |
1351 | explicitly. | |
1352 | ||
7253b85c SH |
1353 | config ARM_ERRATA_775420 |
1354 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1355 | depends on CPU_V7 | |
1356 | help | |
1357 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1358 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1359 | operation aborts with MMU exception, it might cause the processor | |
1360 | to deadlock. This workaround puts DSB before executing ISB if | |
1361 | an abort may occur on cache maintenance. | |
1362 | ||
93dc6887 CM |
1363 | config ARM_ERRATA_798181 |
1364 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1365 | depends on CPU_V7 && SMP | |
1366 | help | |
1367 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1368 | adequately shooting down all use of the old entries. This | |
1369 | option enables the Linux kernel workaround for this erratum | |
1370 | which sends an IPI to the CPUs that are running the same ASID | |
1371 | as the one being invalidated. | |
1372 | ||
1da177e4 LT |
1373 | endmenu |
1374 | ||
1375 | source "arch/arm/common/Kconfig" | |
1376 | ||
1da177e4 LT |
1377 | menu "Bus support" |
1378 | ||
1379 | config ARM_AMBA | |
1380 | bool | |
1381 | ||
1382 | config ISA | |
1383 | bool | |
1da177e4 LT |
1384 | help |
1385 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1386 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1387 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1388 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1389 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1390 | ||
065909b9 | 1391 | # Select ISA DMA controller support |
1da177e4 LT |
1392 | config ISA_DMA |
1393 | bool | |
065909b9 | 1394 | select ISA_DMA_API |
1da177e4 | 1395 | |
065909b9 | 1396 | # Select ISA DMA interface |
5cae841b AV |
1397 | config ISA_DMA_API |
1398 | bool | |
5cae841b | 1399 | |
1da177e4 | 1400 | config PCI |
0b05da72 | 1401 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1402 | help |
1403 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1404 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1405 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1406 | VESA. If you have PCI, say Y, otherwise N. | |
1407 | ||
52882173 AV |
1408 | config PCI_DOMAINS |
1409 | bool | |
1410 | depends on PCI | |
1411 | ||
b080ac8a MRJ |
1412 | config PCI_NANOENGINE |
1413 | bool "BSE nanoEngine PCI support" | |
1414 | depends on SA1100_NANOENGINE | |
1415 | help | |
1416 | Enable PCI on the BSE nanoEngine board. | |
1417 | ||
36e23590 MW |
1418 | config PCI_SYSCALL |
1419 | def_bool PCI | |
1420 | ||
1da177e4 LT |
1421 | # Select the host bridge type |
1422 | config PCI_HOST_VIA82C505 | |
1423 | bool | |
1424 | depends on PCI && ARCH_SHARK | |
1425 | default y | |
1426 | ||
a0113a99 MR |
1427 | config PCI_HOST_ITE8152 |
1428 | bool | |
1429 | depends on PCI && MACH_ARMCORE | |
1430 | default y | |
1431 | select DMABOUNCE | |
1432 | ||
1da177e4 | 1433 | source "drivers/pci/Kconfig" |
3f06d157 | 1434 | source "drivers/pci/pcie/Kconfig" |
1da177e4 LT |
1435 | |
1436 | source "drivers/pcmcia/Kconfig" | |
1437 | ||
1438 | endmenu | |
1439 | ||
1440 | menu "Kernel Features" | |
1441 | ||
3b55658a DM |
1442 | config HAVE_SMP |
1443 | bool | |
1444 | help | |
1445 | This option should be selected by machines which have an SMP- | |
1446 | capable CPU. | |
1447 | ||
1448 | The only effect of this option is to make the SMP-related | |
1449 | options available to the user for configuration. | |
1450 | ||
1da177e4 | 1451 | config SMP |
bb2d8130 | 1452 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1453 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1454 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1455 | depends on HAVE_SMP |
801bb21c | 1456 | depends on MMU || ARM_MPU |
b1b3f49c | 1457 | select USE_GENERIC_SMP_HELPERS |
1da177e4 LT |
1458 | help |
1459 | This enables support for systems with more than one CPU. If you have | |
1460 | a system with only one CPU, like most personal computers, say N. If | |
1461 | you have a system with more than one CPU, say Y. | |
1462 | ||
1463 | If you say N here, the kernel will run on single and multiprocessor | |
1464 | machines, but will use only one CPU of a multiprocessor machine. If | |
1465 | you say Y here, the kernel will run on many, but not all, single | |
1466 | processor machines. On a single processor machine, the kernel will | |
1467 | run faster if you say N here. | |
1468 | ||
395cf969 | 1469 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1470 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1471 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1472 | |
1473 | If you don't know what to do here, say N. | |
1474 | ||
f00ec48f RK |
1475 | config SMP_ON_UP |
1476 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
801bb21c | 1477 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1478 | default y |
1479 | help | |
1480 | SMP kernels contain instructions which fail on non-SMP processors. | |
1481 | Enabling this option allows the kernel to modify itself to make | |
1482 | these instructions safe. Disabling it allows about 1K of space | |
1483 | savings. | |
1484 | ||
1485 | If you don't know what to do here, say Y. | |
1486 | ||
c9018aab VG |
1487 | config ARM_CPU_TOPOLOGY |
1488 | bool "Support cpu topology definition" | |
1489 | depends on SMP && CPU_V7 | |
1490 | default y | |
1491 | help | |
1492 | Support ARM cpu topology definition. The MPIDR register defines | |
1493 | affinity between processors which is then used to describe the cpu | |
1494 | topology of an ARM System. | |
1495 | ||
1496 | config SCHED_MC | |
1497 | bool "Multi-core scheduler support" | |
1498 | depends on ARM_CPU_TOPOLOGY | |
1499 | help | |
1500 | Multi-core scheduler support improves the CPU scheduler's decision | |
1501 | making when dealing with multi-core CPU chips at a cost of slightly | |
1502 | increased overhead in some places. If unsure say N here. | |
1503 | ||
1504 | config SCHED_SMT | |
1505 | bool "SMT scheduler support" | |
1506 | depends on ARM_CPU_TOPOLOGY | |
1507 | help | |
1508 | Improves the CPU scheduler's decision making when dealing with | |
1509 | MultiThreading at a cost of slightly increased overhead in some | |
1510 | places. If unsure say N here. | |
1511 | ||
a8cbcd92 RK |
1512 | config HAVE_ARM_SCU |
1513 | bool | |
a8cbcd92 RK |
1514 | help |
1515 | This option enables support for the ARM system coherency unit | |
1516 | ||
8a4da6e3 | 1517 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1518 | bool "Architected timer support" |
1519 | depends on CPU_V7 | |
8a4da6e3 | 1520 | select ARM_ARCH_TIMER |
022c03a2 MZ |
1521 | help |
1522 | This option enables support for the ARM architected timer | |
1523 | ||
f32f4ce2 RK |
1524 | config HAVE_ARM_TWD |
1525 | bool | |
1526 | depends on SMP | |
da4a686a | 1527 | select CLKSRC_OF if OF |
f32f4ce2 RK |
1528 | help |
1529 | This options enables support for the ARM timer and watchdog unit | |
1530 | ||
e8db288e NP |
1531 | config MCPM |
1532 | bool "Multi-Cluster Power Management" | |
1533 | depends on CPU_V7 && SMP | |
1534 | help | |
1535 | This option provides the common power management infrastructure | |
1536 | for (multi-)cluster based systems, such as big.LITTLE based | |
1537 | systems. | |
1538 | ||
8d5796d2 LB |
1539 | choice |
1540 | prompt "Memory split" | |
1541 | default VMSPLIT_3G | |
1542 | help | |
1543 | Select the desired split between kernel and user memory. | |
1544 | ||
1545 | If you are not absolutely sure what you are doing, leave this | |
1546 | option alone! | |
1547 | ||
1548 | config VMSPLIT_3G | |
1549 | bool "3G/1G user/kernel split" | |
1550 | config VMSPLIT_2G | |
1551 | bool "2G/2G user/kernel split" | |
1552 | config VMSPLIT_1G | |
1553 | bool "1G/3G user/kernel split" | |
1554 | endchoice | |
1555 | ||
1556 | config PAGE_OFFSET | |
1557 | hex | |
1558 | default 0x40000000 if VMSPLIT_1G | |
1559 | default 0x80000000 if VMSPLIT_2G | |
1560 | default 0xC0000000 | |
1561 | ||
1da177e4 LT |
1562 | config NR_CPUS |
1563 | int "Maximum number of CPUs (2-32)" | |
1564 | range 2 32 | |
1565 | depends on SMP | |
1566 | default "4" | |
1567 | ||
a054a811 | 1568 | config HOTPLUG_CPU |
00b7dede | 1569 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1570 | depends on SMP |
a054a811 RK |
1571 | help |
1572 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1573 | can be controlled through /sys/devices/system/cpu. | |
1574 | ||
2bdd424f WD |
1575 | config ARM_PSCI |
1576 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
1577 | depends on CPU_V7 | |
1578 | help | |
1579 | Say Y here if you want Linux to communicate with system firmware | |
1580 | implementing the PSCI specification for CPU-centric power | |
1581 | management operations described in ARM document number ARM DEN | |
1582 | 0022A ("Power State Coordination Interface System Software on | |
1583 | ARM processors"). | |
1584 | ||
37ee16ae RK |
1585 | config LOCAL_TIMERS |
1586 | bool "Use local timer interrupts" | |
971acb9b | 1587 | depends on SMP |
37ee16ae RK |
1588 | default y |
1589 | help | |
1590 | Enable support for local timers on SMP platforms, rather then the | |
1591 | legacy IPI broadcast method. Local timers allows the system | |
1592 | accounting to be spread across the timer interval, preventing a | |
1593 | "thundering herd" at every timer tick. | |
1594 | ||
2a6ad871 MR |
1595 | # The GPIO number here must be sorted by descending number. In case of |
1596 | # a multiplatform kernel, we just want the highest value required by the | |
1597 | # selected platforms. | |
44986ab0 PDSN |
1598 | config ARCH_NR_GPIO |
1599 | int | |
3dea19e8 | 1600 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
39f47d9f | 1601 | default 512 if SOC_OMAP5 |
828989ad | 1602 | default 512 if ARCH_KEYSTONE |
06b851e5 | 1603 | default 392 if ARCH_U8500 |
01bb914c TP |
1604 | default 352 if ARCH_VT8500 |
1605 | default 288 if ARCH_SUNXI | |
2a6ad871 | 1606 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1607 | default 0 |
1608 | help | |
1609 | Maximum number of GPIOs in the system. | |
1610 | ||
1611 | If unsure, leave the default value. | |
1612 | ||
d45a398f | 1613 | source kernel/Kconfig.preempt |
1da177e4 | 1614 | |
f8065813 RK |
1615 | config HZ |
1616 | int | |
b130d5c2 | 1617 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ |
a73ddc61 | 1618 | ARCH_S5PV210 || ARCH_EXYNOS4 |
5248c657 | 1619 | default AT91_TIMER_HZ if ARCH_AT91 |
5da3e714 | 1620 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE |
f8065813 RK |
1621 | default 100 |
1622 | ||
b28748fb RK |
1623 | config SCHED_HRTICK |
1624 | def_bool HIGH_RES_TIMERS | |
1625 | ||
16c79651 | 1626 | config THUMB2_KERNEL |
bc7dea00 | 1627 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1628 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1629 | default y if CPU_THUMBONLY |
16c79651 CM |
1630 | select AEABI |
1631 | select ARM_ASM_UNIFIED | |
89bace65 | 1632 | select ARM_UNWIND |
16c79651 CM |
1633 | help |
1634 | By enabling this option, the kernel will be compiled in | |
1635 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1636 | ARM-Thumb syntax is needed. | |
1637 | ||
1638 | If unsure, say N. | |
1639 | ||
6f685c5c DM |
1640 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1641 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1642 | depends on THUMB2_KERNEL && MODULES | |
1643 | default y | |
1644 | help | |
1645 | Various binutils versions can resolve Thumb-2 branches to | |
1646 | locally-defined, preemptible global symbols as short-range "b.n" | |
1647 | branch instructions. | |
1648 | ||
1649 | This is a problem, because there's no guarantee the final | |
1650 | destination of the symbol, or any candidate locations for a | |
1651 | trampoline, are within range of the branch. For this reason, the | |
1652 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1653 | relocation in modules at all, and it makes little sense to add | |
1654 | support. | |
1655 | ||
1656 | The symptom is that the kernel fails with an "unsupported | |
1657 | relocation" error when loading some modules. | |
1658 | ||
1659 | Until fixed tools are available, passing | |
1660 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1661 | code which hits this problem, at the cost of a bit of extra runtime | |
1662 | stack usage in some cases. | |
1663 | ||
1664 | The problem is described in more detail at: | |
1665 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1666 | ||
1667 | Only Thumb-2 kernels are affected. | |
1668 | ||
1669 | Unless you are sure your tools don't have this problem, say Y. | |
1670 | ||
0becb088 CM |
1671 | config ARM_ASM_UNIFIED |
1672 | bool | |
1673 | ||
704bdda0 NP |
1674 | config AEABI |
1675 | bool "Use the ARM EABI to compile the kernel" | |
1676 | help | |
1677 | This option allows for the kernel to be compiled using the latest | |
1678 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1679 | space environment that is also compiled with EABI. | |
1680 | ||
1681 | Since there are major incompatibilities between the legacy ABI and | |
1682 | EABI, especially with regard to structure member alignment, this | |
1683 | option also changes the kernel syscall calling convention to | |
1684 | disambiguate both ABIs and allow for backward compatibility support | |
1685 | (selected with CONFIG_OABI_COMPAT). | |
1686 | ||
1687 | To use this you need GCC version 4.0.0 or later. | |
1688 | ||
6c90c872 | 1689 | config OABI_COMPAT |
a73a3ff1 | 1690 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1691 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1692 | default y |
1693 | help | |
1694 | This option preserves the old syscall interface along with the | |
1695 | new (ARM EABI) one. It also provides a compatibility layer to | |
1696 | intercept syscalls that have structure arguments which layout | |
1697 | in memory differs between the legacy ABI and the new ARM EABI | |
1698 | (only for non "thumb" binaries). This option adds a tiny | |
1699 | overhead to all syscalls and produces a slightly larger kernel. | |
1700 | If you know you'll be using only pure EABI user space then you | |
1701 | can say N here. If this option is not selected and you attempt | |
1702 | to execute a legacy ABI binary then the result will be | |
1703 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
1704 | at all). If in doubt say Y. | |
1705 | ||
eb33575c | 1706 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1707 | bool |
e80d6a24 | 1708 | |
05944d74 RK |
1709 | config ARCH_SPARSEMEM_ENABLE |
1710 | bool | |
1711 | ||
07a2f737 RK |
1712 | config ARCH_SPARSEMEM_DEFAULT |
1713 | def_bool ARCH_SPARSEMEM_ENABLE | |
1714 | ||
05944d74 | 1715 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1716 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1717 | |
7b7bf499 WD |
1718 | config HAVE_ARCH_PFN_VALID |
1719 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1720 | ||
053a96ca | 1721 | config HIGHMEM |
e8db89a2 RK |
1722 | bool "High Memory Support" |
1723 | depends on MMU | |
053a96ca NP |
1724 | help |
1725 | The address space of ARM processors is only 4 Gigabytes large | |
1726 | and it has to accommodate user address space, kernel address | |
1727 | space as well as some memory mapped IO. That means that, if you | |
1728 | have a large amount of physical memory and/or IO, not all of the | |
1729 | memory can be "permanently mapped" by the kernel. The physical | |
1730 | memory that is not permanently mapped is called "high memory". | |
1731 | ||
1732 | Depending on the selected kernel/user memory split, minimum | |
1733 | vmalloc space and actual amount of RAM, you may not need this | |
1734 | option which should result in a slightly faster kernel. | |
1735 | ||
1736 | If unsure, say n. | |
1737 | ||
65cec8e3 RK |
1738 | config HIGHPTE |
1739 | bool "Allocate 2nd-level pagetables from highmem" | |
1740 | depends on HIGHMEM | |
65cec8e3 | 1741 | |
1b8873a0 JI |
1742 | config HW_PERF_EVENTS |
1743 | bool "Enable hardware performance counter support for perf events" | |
f0d1bc47 | 1744 | depends on PERF_EVENTS |
1b8873a0 JI |
1745 | default y |
1746 | help | |
1747 | Enable hardware performance counter support for perf events. If | |
1748 | disabled, perf events will use software events only. | |
1749 | ||
1355e2a6 CM |
1750 | config SYS_SUPPORTS_HUGETLBFS |
1751 | def_bool y | |
1752 | depends on ARM_LPAE | |
1753 | ||
8d962507 CM |
1754 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1755 | def_bool y | |
1756 | depends on ARM_LPAE | |
1757 | ||
3f22ab27 DH |
1758 | source "mm/Kconfig" |
1759 | ||
c1b2d970 MD |
1760 | config FORCE_MAX_ZONEORDER |
1761 | int "Maximum zone order" if ARCH_SHMOBILE | |
1762 | range 11 64 if ARCH_SHMOBILE | |
898f08e1 | 1763 | default "12" if SOC_AM33XX |
c1b2d970 MD |
1764 | default "9" if SA1111 |
1765 | default "11" | |
1766 | help | |
1767 | The kernel memory allocator divides physically contiguous memory | |
1768 | blocks into "zones", where each zone is a power of two number of | |
1769 | pages. This option selects the largest power of two that the kernel | |
1770 | keeps in the memory allocator. If you need to allocate very large | |
1771 | blocks of physically contiguous memory, then you may need to | |
1772 | increase this value. | |
1773 | ||
1774 | This config option is actually maximum order plus one. For example, | |
1775 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1776 | ||
1da177e4 LT |
1777 | config ALIGNMENT_TRAP |
1778 | bool | |
f12d0d7c | 1779 | depends on CPU_CP15_MMU |
1da177e4 | 1780 | default y if !ARCH_EBSA110 |
e119bfff | 1781 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1782 | help |
84eb8d06 | 1783 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1784 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1785 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1786 | fetch/store instructions will be emulated in software if you say | |
1787 | here, which has a severe performance impact. This is necessary for | |
1788 | correct operation of some network protocols. With an IP-only | |
1789 | configuration it is safe to say N, otherwise say Y. | |
1790 | ||
39ec58f3 | 1791 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1792 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1793 | depends on MMU | |
39ec58f3 LB |
1794 | default y if CPU_FEROCEON |
1795 | help | |
1796 | Implement faster copy_to_user and clear_user methods for CPU | |
1797 | cores where a 8-word STM instruction give significantly higher | |
1798 | memory write throughput than a sequence of individual 32bit stores. | |
1799 | ||
1800 | A possible side effect is a slight increase in scheduling latency | |
1801 | between threads sharing the same address space if they invoke | |
1802 | such copy operations with large buffers. | |
1803 | ||
1804 | However, if the CPU data cache is using a write-allocate mode, | |
1805 | this option is unlikely to provide any performance gain. | |
1806 | ||
70c70d97 NP |
1807 | config SECCOMP |
1808 | bool | |
1809 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1810 | ---help--- | |
1811 | This kernel feature is useful for number crunching applications | |
1812 | that may need to compute untrusted bytecode during their | |
1813 | execution. By using pipes or other transports made available to | |
1814 | the process as file descriptors supporting the read/write | |
1815 | syscalls, it's possible to isolate those applications in | |
1816 | their own address space using seccomp. Once seccomp is | |
1817 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1818 | and the task is only allowed to execute a few safe syscalls | |
1819 | defined by each seccomp mode. | |
1820 | ||
c743f380 NP |
1821 | config CC_STACKPROTECTOR |
1822 | bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" | |
1823 | help | |
1824 | This option turns on the -fstack-protector GCC feature. This | |
1825 | feature puts, at the beginning of functions, a canary value on | |
1826 | the stack just before the return address, and validates | |
1827 | the value just before actually returning. Stack based buffer | |
1828 | overflows (that need to overwrite this return address) now also | |
1829 | overwrite the canary, which gets detected and the attack is then | |
1830 | neutralized via a kernel panic. | |
1831 | This feature requires gcc version 4.2 or above. | |
1832 | ||
eff8d644 SS |
1833 | config XEN_DOM0 |
1834 | def_bool y | |
1835 | depends on XEN | |
1836 | ||
1837 | config XEN | |
1838 | bool "Xen guest support on ARM (EXPERIMENTAL)" | |
85323a99 | 1839 | depends on ARM && AEABI && OF |
f880b67d | 1840 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1841 | depends on !GENERIC_ATOMIC64 |
17b7ab80 | 1842 | select ARM_PSCI |
eff8d644 SS |
1843 | help |
1844 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1845 | ||
1da177e4 LT |
1846 | endmenu |
1847 | ||
1848 | menu "Boot options" | |
1849 | ||
9eb8f674 GL |
1850 | config USE_OF |
1851 | bool "Flattened Device Tree support" | |
b1b3f49c | 1852 | select IRQ_DOMAIN |
9eb8f674 GL |
1853 | select OF |
1854 | select OF_EARLY_FLATTREE | |
1855 | help | |
1856 | Include support for flattened device tree machine descriptions. | |
1857 | ||
bd51e2f5 NP |
1858 | config ATAGS |
1859 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1860 | default y | |
1861 | help | |
1862 | This is the traditional way of passing data to the kernel at boot | |
1863 | time. If you are solely relying on the flattened device tree (or | |
1864 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1865 | to remove ATAGS support from your kernel binary. If unsure, | |
1866 | leave this to y. | |
1867 | ||
1868 | config DEPRECATED_PARAM_STRUCT | |
1869 | bool "Provide old way to pass kernel parameters" | |
1870 | depends on ATAGS | |
1871 | help | |
1872 | This was deprecated in 2001 and announced to live on for 5 years. | |
1873 | Some old boot loaders still use this way. | |
1874 | ||
1da177e4 LT |
1875 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1876 | # TEXT and BSS so we preserve their values in the config files. | |
1877 | config ZBOOT_ROM_TEXT | |
1878 | hex "Compressed ROM boot loader base address" | |
1879 | default "0" | |
1880 | help | |
1881 | The physical address at which the ROM-able zImage is to be | |
1882 | placed in the target. Platforms which normally make use of | |
1883 | ROM-able zImage formats normally set this to a suitable | |
1884 | value in their defconfig file. | |
1885 | ||
1886 | If ZBOOT_ROM is not enabled, this has no effect. | |
1887 | ||
1888 | config ZBOOT_ROM_BSS | |
1889 | hex "Compressed ROM boot loader BSS address" | |
1890 | default "0" | |
1891 | help | |
f8c440b2 DF |
1892 | The base address of an area of read/write memory in the target |
1893 | for the ROM-able zImage which must be available while the | |
1894 | decompressor is running. It must be large enough to hold the | |
1895 | entire decompressed kernel plus an additional 128 KiB. | |
1896 | Platforms which normally make use of ROM-able zImage formats | |
1897 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1898 | |
1899 | If ZBOOT_ROM is not enabled, this has no effect. | |
1900 | ||
1901 | config ZBOOT_ROM | |
1902 | bool "Compressed boot loader in ROM/flash" | |
1903 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
1904 | help | |
1905 | Say Y here if you intend to execute your compressed kernel image | |
1906 | (zImage) directly from ROM or flash. If unsure, say N. | |
1907 | ||
090ab3ff SH |
1908 | choice |
1909 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1910 | depends on ZBOOT_ROM && ARCH_SH7372 |
090ab3ff SH |
1911 | default ZBOOT_ROM_NONE |
1912 | help | |
1913 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
59bf8964 | 1914 | With this enabled it is possible to write the ROM-able zImage |
090ab3ff SH |
1915 | kernel image to an MMC or SD card and boot the kernel straight |
1916 | from the reset vector. At reset the processor Mask ROM will load | |
59bf8964 | 1917 | the first part of the ROM-able zImage which in turn loads the |
090ab3ff SH |
1918 | rest the kernel image to RAM. |
1919 | ||
1920 | config ZBOOT_ROM_NONE | |
1921 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1922 | help | |
1923 | Do not load image from SD or MMC | |
1924 | ||
f45b1149 SH |
1925 | config ZBOOT_ROM_MMCIF |
1926 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
f45b1149 | 1927 | help |
090ab3ff SH |
1928 | Load image from MMCIF hardware block. |
1929 | ||
1930 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
1931 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
1932 | help | |
1933 | Load image from SDHI hardware block | |
1934 | ||
1935 | endchoice | |
f45b1149 | 1936 | |
e2a6a3aa JB |
1937 | config ARM_APPENDED_DTB |
1938 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1939 | depends on OF && !ZBOOT_ROM |
e2a6a3aa JB |
1940 | help |
1941 | With this option, the boot code will look for a device tree binary | |
1942 | (DTB) appended to zImage | |
1943 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1944 | ||
1945 | This is meant as a backward compatibility convenience for those | |
1946 | systems with a bootloader that can't be upgraded to accommodate | |
1947 | the documented boot protocol using a device tree. | |
1948 | ||
1949 | Beware that there is very little in terms of protection against | |
1950 | this option being confused by leftover garbage in memory that might | |
1951 | look like a DTB header after a reboot if no actual DTB is appended | |
1952 | to zImage. Do not leave this option active in a production kernel | |
1953 | if you don't intend to always append a DTB. Proper passing of the | |
1954 | location into r2 of a bootloader provided DTB is always preferable | |
1955 | to this option. | |
1956 | ||
b90b9a38 NP |
1957 | config ARM_ATAG_DTB_COMPAT |
1958 | bool "Supplement the appended DTB with traditional ATAG information" | |
1959 | depends on ARM_APPENDED_DTB | |
1960 | help | |
1961 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1962 | they provide ATAGs with memory configuration, the ramdisk address, | |
1963 | the kernel cmdline string, etc. Such information is dynamically | |
1964 | provided by the bootloader and can't always be stored in a static | |
1965 | DTB. To allow a device tree enabled kernel to be used with such | |
1966 | bootloaders, this option allows zImage to extract the information | |
1967 | from the ATAG list and store it at run time into the appended DTB. | |
1968 | ||
d0f34a11 GR |
1969 | choice |
1970 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1971 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1972 | ||
1973 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1974 | bool "Use bootloader kernel arguments if available" | |
1975 | help | |
1976 | Uses the command-line options passed by the boot loader instead of | |
1977 | the device tree bootargs property. If the boot loader doesn't provide | |
1978 | any, the device tree bootargs property will be used. | |
1979 | ||
1980 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1981 | bool "Extend with bootloader kernel arguments" | |
1982 | help | |
1983 | The command-line arguments provided by the boot loader will be | |
1984 | appended to the the device tree bootargs property. | |
1985 | ||
1986 | endchoice | |
1987 | ||
1da177e4 LT |
1988 | config CMDLINE |
1989 | string "Default kernel command string" | |
1990 | default "" | |
1991 | help | |
1992 | On some architectures (EBSA110 and CATS), there is currently no way | |
1993 | for the boot loader to pass arguments to the kernel. For these | |
1994 | architectures, you should supply some command-line options at build | |
1995 | time by entering them here. As a minimum, you should specify the | |
1996 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1997 | ||
4394c124 VB |
1998 | choice |
1999 | prompt "Kernel command line type" if CMDLINE != "" | |
2000 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 2001 | depends on ATAGS |
4394c124 VB |
2002 | |
2003 | config CMDLINE_FROM_BOOTLOADER | |
2004 | bool "Use bootloader kernel arguments if available" | |
2005 | help | |
2006 | Uses the command-line options passed by the boot loader. If | |
2007 | the boot loader doesn't provide any, the default kernel command | |
2008 | string provided in CMDLINE will be used. | |
2009 | ||
2010 | config CMDLINE_EXTEND | |
2011 | bool "Extend bootloader kernel arguments" | |
2012 | help | |
2013 | The command-line arguments provided by the boot loader will be | |
2014 | appended to the default kernel command string. | |
2015 | ||
92d2040d AH |
2016 | config CMDLINE_FORCE |
2017 | bool "Always use the default kernel command string" | |
92d2040d AH |
2018 | help |
2019 | Always use the default kernel command string, even if the boot | |
2020 | loader passes other arguments to the kernel. | |
2021 | This is useful if you cannot or don't want to change the | |
2022 | command-line options your boot loader passes to the kernel. | |
4394c124 | 2023 | endchoice |
92d2040d | 2024 | |
1da177e4 LT |
2025 | config XIP_KERNEL |
2026 | bool "Kernel Execute-In-Place from ROM" | |
387798b3 | 2027 | depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
2028 | help |
2029 | Execute-In-Place allows the kernel to run from non-volatile storage | |
2030 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
2031 | space since the text section of the kernel is not loaded from flash | |
2032 | to RAM. Read-write sections, such as the data section and stack, | |
2033 | are still copied to RAM. The XIP kernel is not compressed since | |
2034 | it has to run directly from flash, so it will take more space to | |
2035 | store it. The flash address used to link the kernel object files, | |
2036 | and for storing it, is configuration dependent. Therefore, if you | |
2037 | say Y here, you must know the proper physical address where to | |
2038 | store the kernel image depending on your own flash memory usage. | |
2039 | ||
2040 | Also note that the make target becomes "make xipImage" rather than | |
2041 | "make zImage" or "make Image". The final kernel binary to put in | |
2042 | ROM memory will be arch/arm/boot/xipImage. | |
2043 | ||
2044 | If unsure, say N. | |
2045 | ||
2046 | config XIP_PHYS_ADDR | |
2047 | hex "XIP Kernel Physical Location" | |
2048 | depends on XIP_KERNEL | |
2049 | default "0x00080000" | |
2050 | help | |
2051 | This is the physical address in your flash memory the kernel will | |
2052 | be linked for and stored to. This address is dependent on your | |
2053 | own flash usage. | |
2054 | ||
c587e4a6 RP |
2055 | config KEXEC |
2056 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 2057 | depends on (!SMP || PM_SLEEP_SMP) |
c587e4a6 RP |
2058 | help |
2059 | kexec is a system call that implements the ability to shutdown your | |
2060 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 2061 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
2062 | you can start any kernel with it, not just Linux. |
2063 | ||
2064 | It is an ongoing process to be certain the hardware in a machine | |
2065 | is properly shutdown, so do not be surprised if this code does not | |
2066 | initially work for you. It may help to enable device hotplugging | |
2067 | support. | |
2068 | ||
4cd9d6f7 RP |
2069 | config ATAGS_PROC |
2070 | bool "Export atags in procfs" | |
bd51e2f5 | 2071 | depends on ATAGS && KEXEC |
b98d7291 | 2072 | default y |
4cd9d6f7 RP |
2073 | help |
2074 | Should the atags used to boot the kernel be exported in an "atags" | |
2075 | file in procfs. Useful with kexec. | |
2076 | ||
cb5d39b3 MW |
2077 | config CRASH_DUMP |
2078 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2079 | help |
2080 | Generate crash dump after being started by kexec. This should | |
2081 | be normally only set in special crash dump kernels which are | |
2082 | loaded in the main kernel with kexec-tools into a specially | |
2083 | reserved region and then later executed after a crash by | |
2084 | kdump/kexec. The crash dump kernel must be compiled to a | |
2085 | memory address not used by the main kernel | |
2086 | ||
2087 | For more details see Documentation/kdump/kdump.txt | |
2088 | ||
e69edc79 EM |
2089 | config AUTO_ZRELADDR |
2090 | bool "Auto calculation of the decompressed kernel image address" | |
e1b31445 | 2091 | depends on !ZBOOT_ROM |
e69edc79 EM |
2092 | help |
2093 | ZRELADDR is the physical address where the decompressed kernel | |
2094 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2095 | will be determined at run-time by masking the current IP with | |
2096 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2097 | from start of memory. | |
2098 | ||
1da177e4 LT |
2099 | endmenu |
2100 | ||
ac9d7efc | 2101 | menu "CPU Power Management" |
1da177e4 | 2102 | |
89c52ed4 | 2103 | if ARCH_HAS_CPUFREQ |
1da177e4 | 2104 | source "drivers/cpufreq/Kconfig" |
1da177e4 LT |
2105 | endif |
2106 | ||
ac9d7efc RK |
2107 | source "drivers/cpuidle/Kconfig" |
2108 | ||
2109 | endmenu | |
2110 | ||
1da177e4 LT |
2111 | menu "Floating point emulation" |
2112 | ||
2113 | comment "At least one emulation must be selected" | |
2114 | ||
2115 | config FPE_NWFPE | |
2116 | bool "NWFPE math emulation" | |
593c252a | 2117 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2118 | ---help--- |
2119 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2120 | This is necessary to run most binaries. Linux does not currently | |
2121 | support floating point hardware so you need to say Y here even if | |
2122 | your machine has an FPA or floating point co-processor podule. | |
2123 | ||
2124 | You may say N here if you are going to load the Acorn FPEmulator | |
2125 | early in the bootup. | |
2126 | ||
2127 | config FPE_NWFPE_XP | |
2128 | bool "Support extended precision" | |
bedf142b | 2129 | depends on FPE_NWFPE |
1da177e4 LT |
2130 | help |
2131 | Say Y to include 80-bit support in the kernel floating-point | |
2132 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2133 | Note that gcc does not generate 80-bit operations by default, | |
2134 | so in most cases this option only enlarges the size of the | |
2135 | floating point emulator without any good reason. | |
2136 | ||
2137 | You almost surely want to say N here. | |
2138 | ||
2139 | config FPE_FASTFPE | |
2140 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2141 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2142 | ---help--- |
2143 | Say Y here to include the FAST floating point emulator in the kernel. | |
2144 | This is an experimental much faster emulator which now also has full | |
2145 | precision for the mantissa. It does not support any exceptions. | |
2146 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2147 | ||
2148 | It should be sufficient for most programs. It may be not suitable | |
2149 | for scientific calculations, but you have to check this for yourself. | |
2150 | If you do not feel you need a faster FP emulation you should better | |
2151 | choose NWFPE. | |
2152 | ||
2153 | config VFP | |
2154 | bool "VFP-format floating point maths" | |
e399b1a4 | 2155 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2156 | help |
2157 | Say Y to include VFP support code in the kernel. This is needed | |
2158 | if your hardware includes a VFP unit. | |
2159 | ||
2160 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2161 | release notes and additional status information. | |
2162 | ||
2163 | Say N if your target does not have VFP hardware. | |
2164 | ||
25ebee02 CM |
2165 | config VFPv3 |
2166 | bool | |
2167 | depends on VFP | |
2168 | default y if CPU_V7 | |
2169 | ||
b5872db4 CM |
2170 | config NEON |
2171 | bool "Advanced SIMD (NEON) Extension support" | |
2172 | depends on VFPv3 && CPU_V7 | |
2173 | help | |
2174 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2175 | Extension. | |
2176 | ||
1da177e4 LT |
2177 | endmenu |
2178 | ||
2179 | menu "Userspace binary formats" | |
2180 | ||
2181 | source "fs/Kconfig.binfmt" | |
2182 | ||
2183 | config ARTHUR | |
2184 | tristate "RISC OS personality" | |
704bdda0 | 2185 | depends on !AEABI |
1da177e4 LT |
2186 | help |
2187 | Say Y here to include the kernel code necessary if you want to run | |
2188 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2189 | experimental; if this sounds frightening, say N and sleep in peace. | |
2190 | You can also say M here to compile this support as a module (which | |
2191 | will be called arthur). | |
2192 | ||
2193 | endmenu | |
2194 | ||
2195 | menu "Power management options" | |
2196 | ||
eceab4ac | 2197 | source "kernel/power/Kconfig" |
1da177e4 | 2198 | |
f4cb5700 | 2199 | config ARCH_SUSPEND_POSSIBLE |
4b1082ca | 2200 | depends on !ARCH_S5PC100 |
6a786182 | 2201 | depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ |
3f5d0819 | 2202 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2203 | def_bool y |
2204 | ||
15e0d9e3 AB |
2205 | config ARM_CPU_SUSPEND |
2206 | def_bool PM_SLEEP | |
2207 | ||
1da177e4 LT |
2208 | endmenu |
2209 | ||
d5950b43 SR |
2210 | source "net/Kconfig" |
2211 | ||
ac25150f | 2212 | source "drivers/Kconfig" |
1da177e4 LT |
2213 | |
2214 | source "fs/Kconfig" | |
2215 | ||
1da177e4 LT |
2216 | source "arch/arm/Kconfig.debug" |
2217 | ||
2218 | source "security/Kconfig" | |
2219 | ||
2220 | source "crypto/Kconfig" | |
2221 | ||
2222 | source "lib/Kconfig" | |
749cf76c CD |
2223 | |
2224 | source "arch/arm/kvm/Kconfig" |