ARM: mach-davinci: clean up debug-macro.S
[deliverable/linux.git] / arch / arm / Kconfig
CommitLineData
1da177e4
LT
1config ARM
2 bool
3 default y
e17c6d56 4 select HAVE_AOUT
24056f52 5 select HAVE_DMA_API_DEBUG
2064c946 6 select HAVE_IDE
2778f620 7 select HAVE_MEMBLOCK
12b824fb 8 select RTC_LIB
75e7153a 9 select SYS_SUPPORTS_APM_EMULATION
a41297a0 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
fe166148 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
5cbad0eb 12 select HAVE_ARCH_KGDB
856bc356 13 select HAVE_KPROBES if !XIP_KERNEL
9edddaa2 14 select HAVE_KRETPROBES if (HAVE_KPROBES)
606576ce 15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
80be7a7f
RV
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
0e341af8 18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
1fe53268 19 select HAVE_GENERIC_DMA_COHERENT
e7db7b42
AT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
6e8699f7 22 select HAVE_KERNEL_LZMA
e360adbe 23 select HAVE_IRQ_WORK
7ada189f
JI
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
e513f8bf 26 select HAVE_REGS_AND_STACK_ACCESS_API
e399b1a4 27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
ed60453f 28 select HAVE_C_RECORDMCOUNT
e2a93ecc
LB
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
25a5662a 31 select GENERIC_IRQ_SHOW
1da177e4
LT
32 help
33 The ARM series is a line of low-power-consumption RISC chip designs
f6c8965a 34 licensed by ARM Ltd and targeted at embedded applications and
1da177e4 35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
f6c8965a 36 manufactured, but legacy ARM-based PC hardware remains popular in
1da177e4
LT
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
39
74facffe
RK
40config ARM_HAS_SG_CHAIN
41 bool
42
1a189b97
RK
43config HAVE_PWM
44 bool
45
0b05da72
HUK
46config MIGHT_HAVE_PCI
47 bool
48
75e7153a
RB
49config SYS_SUPPORTS_APM_EMULATION
50 bool
51
112f38a4
RK
52config HAVE_SCHED_CLOCK
53 bool
54
0a938b97
DB
55config GENERIC_GPIO
56 bool
0a938b97 57
5cfc8ee0
JS
58config ARCH_USES_GETTIMEOFFSET
59 bool
60 default n
746140c7 61
0567a0c0
KH
62config GENERIC_CLOCKEVENTS
63 bool
0567a0c0 64
a8655e83
CM
65config GENERIC_CLOCKEVENTS_BROADCAST
66 bool
67 depends on GENERIC_CLOCKEVENTS
5388a6b2 68 default y if SMP
a8655e83 69
bf9dd360
RH
70config KTIME_SCALAR
71 bool
72 default y
73
bc581770
LW
74config HAVE_TCM
75 bool
76 select GENERIC_ALLOCATOR
77
e119bfff
RK
78config HAVE_PROC_CPU
79 bool
80
5ea81769
AV
81config NO_IOPORT
82 bool
5ea81769 83
1da177e4
LT
84config EISA
85 bool
86 ---help---
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
89
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
94
95 Say Y here if you are building a kernel for an EISA-based machine.
96
97 Otherwise, say N.
98
99config SBUS
100 bool
101
102config MCA
103 bool
104 help
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
109
f16fb1ec
RK
110config STACKTRACE_SUPPORT
111 bool
112 default y
113
f76e9154
NP
114config HAVE_LATENCYTOP_SUPPORT
115 bool
116 depends on !SMP
117 default y
118
f16fb1ec
RK
119config LOCKDEP_SUPPORT
120 bool
121 default y
122
7ad1bcb2
RK
123config TRACE_IRQFLAGS_SUPPORT
124 bool
125 default y
126
4a2581a0
TG
127config HARDIRQS_SW_RESEND
128 bool
129 default y
130
131config GENERIC_IRQ_PROBE
132 bool
133 default y
134
95c354fe
NP
135config GENERIC_LOCKBREAK
136 bool
137 default y
138 depends on SMP && PREEMPT
139
1da177e4
LT
140config RWSEM_GENERIC_SPINLOCK
141 bool
142 default y
143
144config RWSEM_XCHGADD_ALGORITHM
145 bool
146
f0d1b0b3
DH
147config ARCH_HAS_ILOG2_U32
148 bool
f0d1b0b3
DH
149
150config ARCH_HAS_ILOG2_U64
151 bool
f0d1b0b3 152
89c52ed4
BD
153config ARCH_HAS_CPUFREQ
154 bool
155 help
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
158 it.
159
c7b0aff4
KH
160config ARCH_HAS_CPU_IDLE_WAIT
161 def_bool y
162
b89c3b16
AM
163config GENERIC_HWEIGHT
164 bool
165 default y
166
1da177e4
LT
167config GENERIC_CALIBRATE_DELAY
168 bool
169 default y
170
a08b6b79
Z
171config ARCH_MAY_HAVE_PC_FDC
172 bool
173
5ac6da66
CL
174config ZONE_DMA
175 bool
5ac6da66 176
ccd7ab7f
FT
177config NEED_DMA_MAP_STATE
178 def_bool y
179
1da177e4
LT
180config GENERIC_ISA_DMA
181 bool
182
1da177e4
LT
183config FIQ
184 bool
185
034d2f5a
AV
186config ARCH_MTD_XIP
187 bool
188
c760fc19
HC
189config VECTORS_BASE
190 hex
6afd6fae 191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
c760fc19
HC
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 default 0x00000000
194 help
195 The base address of exception vectors.
196
dc21af99 197config ARM_PATCH_PHYS_VIRT
c1becedc
RK
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
199 default y
b511d75d 200 depends on !XIP_KERNEL && MMU
dc21af99
RK
201 depends on !ARCH_REALVIEW || !SPARSEMEM
202 help
111e9a5c
RK
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
dc21af99 206
111e9a5c 207 This can only be used with non-XIP MMU kernels where the base
daece596 208 of physical memory is at a 16MB boundary.
dc21af99 209
c1becedc
RK
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
213
cada3c08 214
1da177e4
LT
215source "init/Kconfig"
216
dc52ddc0
MH
217source "kernel/Kconfig.freezer"
218
1da177e4
LT
219menu "System Type"
220
3c427975
HC
221config MMU
222 bool "MMU-based Paged Memory Management Support"
223 default y
224 help
225 Select if you want MMU-based virtualised addressing space
226 support by paged memory management. If unsure, say 'Y'.
227
ccf50e23
RK
228#
229# The "ARM system type" choice list is ordered alphabetically by option
230# text. Please add new entries in the option alphabetic order.
231#
1da177e4
LT
232choice
233 prompt "ARM system type"
6a0e2430 234 default ARCH_VERSATILE
1da177e4 235
4af6fee1
DS
236config ARCH_INTEGRATOR
237 bool "ARM Ltd. Integrator family"
238 select ARM_AMBA
89c52ed4 239 select ARCH_HAS_CPUFREQ
6d803ba7 240 select CLKDEV_LOOKUP
aa3831cf 241 select HAVE_MACH_CLKDEV
c5a0adb5 242 select ICST
13edd86d 243 select GENERIC_CLOCKEVENTS
f4b8b319 244 select PLAT_VERSATILE
c41b16f8 245 select PLAT_VERSATILE_FPGA_IRQ
4af6fee1
DS
246 help
247 Support for ARM's Integrator platform.
248
249config ARCH_REALVIEW
250 bool "ARM Ltd. RealView family"
251 select ARM_AMBA
6d803ba7 252 select CLKDEV_LOOKUP
aa3831cf 253 select HAVE_MACH_CLKDEV
c5a0adb5 254 select ICST
ae30ceac 255 select GENERIC_CLOCKEVENTS
eb7fffa3 256 select ARCH_WANT_OPTIONAL_GPIOLIB
f4b8b319 257 select PLAT_VERSATILE
3cb5ee49 258 select PLAT_VERSATILE_CLCD
e3887714 259 select ARM_TIMER_SP804
b56ba8aa 260 select GPIO_PL061 if GPIOLIB
4af6fee1
DS
261 help
262 This enables support for ARM Ltd RealView boards.
263
264config ARCH_VERSATILE
265 bool "ARM Ltd. Versatile family"
266 select ARM_AMBA
267 select ARM_VIC
6d803ba7 268 select CLKDEV_LOOKUP
aa3831cf 269 select HAVE_MACH_CLKDEV
c5a0adb5 270 select ICST
89df1272 271 select GENERIC_CLOCKEVENTS
bbeddc43 272 select ARCH_WANT_OPTIONAL_GPIOLIB
f4b8b319 273 select PLAT_VERSATILE
3414ba8c 274 select PLAT_VERSATILE_CLCD
c41b16f8 275 select PLAT_VERSATILE_FPGA_IRQ
e3887714 276 select ARM_TIMER_SP804
4af6fee1
DS
277 help
278 This enables support for ARM Ltd Versatile board.
279
ceade897
RK
280config ARCH_VEXPRESS
281 bool "ARM Ltd. Versatile Express family"
282 select ARCH_WANT_OPTIONAL_GPIOLIB
283 select ARM_AMBA
284 select ARM_TIMER_SP804
6d803ba7 285 select CLKDEV_LOOKUP
aa3831cf 286 select HAVE_MACH_CLKDEV
ceade897 287 select GENERIC_CLOCKEVENTS
ceade897 288 select HAVE_CLK
95c34f83 289 select HAVE_PATA_PLATFORM
ceade897
RK
290 select ICST
291 select PLAT_VERSATILE
0fb44b91 292 select PLAT_VERSATILE_CLCD
ceade897
RK
293 help
294 This enables support for the ARM Ltd Versatile Express boards.
295
8fc5ffa0
AV
296config ARCH_AT91
297 bool "Atmel AT91"
f373e8c0 298 select ARCH_REQUIRE_GPIOLIB
93686ae8 299 select HAVE_CLK
bd602995 300 select CLKDEV_LOOKUP
4af6fee1 301 help
2b3b3516
AV
302 This enables support for systems based on the Atmel AT91RM9200,
303 AT91SAM9 and AT91CAP9 processors.
4af6fee1 304
ccf50e23
RK
305config ARCH_BCMRING
306 bool "Broadcom BCMRING"
307 depends on MMU
308 select CPU_V6
309 select ARM_AMBA
82d63734 310 select ARM_TIMER_SP804
6d803ba7 311 select CLKDEV_LOOKUP
ccf50e23
RK
312 select GENERIC_CLOCKEVENTS
313 select ARCH_WANT_OPTIONAL_GPIOLIB
314 help
315 Support for Broadcom's BCMRing platform.
316
1da177e4 317config ARCH_CLPS711X
4af6fee1 318 bool "Cirrus Logic CLPS711x/EP721x-based"
c750815e 319 select CPU_ARM720T
5cfc8ee0 320 select ARCH_USES_GETTIMEOFFSET
f999b8bd
MM
321 help
322 Support for Cirrus Logic 711x/721x based boards.
1da177e4 323
d94f944e
AV
324config ARCH_CNS3XXX
325 bool "Cavium Networks CNS3XXX family"
00d2711d 326 select CPU_V6K
d94f944e
AV
327 select GENERIC_CLOCKEVENTS
328 select ARM_GIC
0b05da72 329 select MIGHT_HAVE_PCI
5f32f7a0 330 select PCI_DOMAINS if PCI
d94f944e
AV
331 help
332 Support for Cavium Networks CNS3XXX platform.
333
788c9700
RK
334config ARCH_GEMINI
335 bool "Cortina Systems Gemini"
336 select CPU_FA526
788c9700 337 select ARCH_REQUIRE_GPIOLIB
5cfc8ee0 338 select ARCH_USES_GETTIMEOFFSET
788c9700
RK
339 help
340 Support for the Cortina Systems Gemini family SoCs
341
3a6cb8ce
AB
342config ARCH_PRIMA2
343 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
344 select CPU_V7
345 select GENERIC_TIME
346 select NO_IOPORT
347 select GENERIC_CLOCKEVENTS
348 select CLKDEV_LOOKUP
349 select GENERIC_IRQ_CHIP
350 select USE_OF
351 select ZONE_DMA
352 help
353 Support for CSR SiRFSoC ARM Cortex A9 Platform
354
1da177e4
LT
355config ARCH_EBSA110
356 bool "EBSA-110"
c750815e 357 select CPU_SA110
f7e68bbf 358 select ISA
c5eb2a2b 359 select NO_IOPORT
5cfc8ee0 360 select ARCH_USES_GETTIMEOFFSET
1da177e4
LT
361 help
362 This is an evaluation board for the StrongARM processor available
f6c8965a 363 from Digital. It has limited hardware on-board, including an
1da177e4
LT
364 Ethernet interface, two PCMCIA sockets, two serial ports and a
365 parallel port.
366
e7736d47
LB
367config ARCH_EP93XX
368 bool "EP93xx-based"
c750815e 369 select CPU_ARM920T
e7736d47
LB
370 select ARM_AMBA
371 select ARM_VIC
6d803ba7 372 select CLKDEV_LOOKUP
7444a72e 373 select ARCH_REQUIRE_GPIOLIB
eb33575c 374 select ARCH_HAS_HOLES_MEMORYMODEL
5cfc8ee0 375 select ARCH_USES_GETTIMEOFFSET
e7736d47
LB
376 help
377 This enables support for the Cirrus EP93xx series of CPUs.
378
1da177e4
LT
379config ARCH_FOOTBRIDGE
380 bool "FootBridge"
c750815e 381 select CPU_SA110
1da177e4 382 select FOOTBRIDGE
4e8d7637 383 select GENERIC_CLOCKEVENTS
f999b8bd
MM
384 help
385 Support for systems based on the DC21285 companion chip
386 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
1da177e4 387
788c9700
RK
388config ARCH_MXC
389 bool "Freescale MXC/iMX-based"
788c9700 390 select GENERIC_CLOCKEVENTS
788c9700 391 select ARCH_REQUIRE_GPIOLIB
6d803ba7 392 select CLKDEV_LOOKUP
234b6ced 393 select CLKSRC_MMIO
8b6c44f1 394 select GENERIC_IRQ_CHIP
c124befc 395 select HAVE_SCHED_CLOCK
788c9700
RK
396 help
397 Support for Freescale MXC/iMX-based family of processors
398
1d3f33d5
SG
399config ARCH_MXS
400 bool "Freescale MXS-based"
401 select GENERIC_CLOCKEVENTS
402 select ARCH_REQUIRE_GPIOLIB
b9214b97 403 select CLKDEV_LOOKUP
5c61ddcf 404 select CLKSRC_MMIO
1d3f33d5
SG
405 help
406 Support for Freescale MXS-based family of processors
407
4af6fee1
DS
408config ARCH_NETX
409 bool "Hilscher NetX based"
234b6ced 410 select CLKSRC_MMIO
c750815e 411 select CPU_ARM926T
4af6fee1 412 select ARM_VIC
2fcfe6b8 413 select GENERIC_CLOCKEVENTS
f999b8bd 414 help
4af6fee1
DS
415 This enables support for systems based on the Hilscher NetX Soc
416
417config ARCH_H720X
418 bool "Hynix HMS720x-based"
c750815e 419 select CPU_ARM720T
4af6fee1 420 select ISA_DMA_API
5cfc8ee0 421 select ARCH_USES_GETTIMEOFFSET
4af6fee1
DS
422 help
423 This enables support for systems based on the Hynix HMS720x
424
3b938be6
RK
425config ARCH_IOP13XX
426 bool "IOP13xx-based"
427 depends on MMU
c750815e 428 select CPU_XSC3
3b938be6
RK
429 select PLAT_IOP
430 select PCI
431 select ARCH_SUPPORTS_MSI
8d5796d2 432 select VMSPLIT_1G
3b938be6
RK
433 help
434 Support for Intel's IOP13XX (XScale) family of processors.
435
3f7e5815
LB
436config ARCH_IOP32X
437 bool "IOP32x-based"
a4f7e763 438 depends on MMU
c750815e 439 select CPU_XSCALE
7ae1f7ec 440 select PLAT_IOP
f7e68bbf 441 select PCI
bb2b180c 442 select ARCH_REQUIRE_GPIOLIB
f999b8bd 443 help
3f7e5815
LB
444 Support for Intel's 80219 and IOP32X (XScale) family of
445 processors.
446
447config ARCH_IOP33X
448 bool "IOP33x-based"
449 depends on MMU
c750815e 450 select CPU_XSCALE
7ae1f7ec 451 select PLAT_IOP
3f7e5815 452 select PCI
bb2b180c 453 select ARCH_REQUIRE_GPIOLIB
3f7e5815
LB
454 help
455 Support for Intel's IOP33X (XScale) family of processors.
1da177e4 456
3b938be6
RK
457config ARCH_IXP23XX
458 bool "IXP23XX-based"
a4f7e763 459 depends on MMU
c750815e 460 select CPU_XSC3
3b938be6 461 select PCI
5cfc8ee0 462 select ARCH_USES_GETTIMEOFFSET
f999b8bd 463 help
3b938be6 464 Support for Intel's IXP23xx (XScale) family of processors.
1da177e4
LT
465
466config ARCH_IXP2000
467 bool "IXP2400/2800-based"
a4f7e763 468 depends on MMU
c750815e 469 select CPU_XSCALE
f7e68bbf 470 select PCI
5cfc8ee0 471 select ARCH_USES_GETTIMEOFFSET
f999b8bd
MM
472 help
473 Support for Intel's IXP2400/2800 (XScale) family of processors.
1da177e4 474
3b938be6
RK
475config ARCH_IXP4XX
476 bool "IXP4xx-based"
a4f7e763 477 depends on MMU
234b6ced 478 select CLKSRC_MMIO
c750815e 479 select CPU_XSCALE
8858e9af 480 select GENERIC_GPIO
3b938be6 481 select GENERIC_CLOCKEVENTS
5b0d495c 482 select HAVE_SCHED_CLOCK
0b05da72 483 select MIGHT_HAVE_PCI
485bdde7 484 select DMABOUNCE if PCI
c4713074 485 help
3b938be6 486 Support for Intel's IXP4XX (XScale) family of processors.
c4713074 487
edabd38e
SB
488config ARCH_DOVE
489 bool "Marvell Dove"
7b769bb3 490 select CPU_V7
edabd38e 491 select PCI
edabd38e 492 select ARCH_REQUIRE_GPIOLIB
edabd38e
SB
493 select GENERIC_CLOCKEVENTS
494 select PLAT_ORION
495 help
496 Support for the Marvell Dove SoC 88AP510
497
651c74c7
SB
498config ARCH_KIRKWOOD
499 bool "Marvell Kirkwood"
c750815e 500 select CPU_FEROCEON
651c74c7 501 select PCI
a8865655 502 select ARCH_REQUIRE_GPIOLIB
651c74c7
SB
503 select GENERIC_CLOCKEVENTS
504 select PLAT_ORION
505 help
506 Support for the following Marvell Kirkwood series SoCs:
507 88F6180, 88F6192 and 88F6281.
508
40805949
KW
509config ARCH_LPC32XX
510 bool "NXP LPC32XX"
234b6ced 511 select CLKSRC_MMIO
40805949
KW
512 select CPU_ARM926T
513 select ARCH_REQUIRE_GPIOLIB
514 select HAVE_IDE
515 select ARM_AMBA
516 select USB_ARCH_HAS_OHCI
6d803ba7 517 select CLKDEV_LOOKUP
40805949
KW
518 select GENERIC_TIME
519 select GENERIC_CLOCKEVENTS
520 help
521 Support for the NXP LPC32XX family of processors
522
794d15b2
SS
523config ARCH_MV78XX0
524 bool "Marvell MV78xx0"
c750815e 525 select CPU_FEROCEON
794d15b2 526 select PCI
a8865655 527 select ARCH_REQUIRE_GPIOLIB
794d15b2
SS
528 select GENERIC_CLOCKEVENTS
529 select PLAT_ORION
530 help
531 Support for the following Marvell MV78xx0 series SoCs:
532 MV781x0, MV782x0.
533
9dd0b194 534config ARCH_ORION5X
585cf175
TP
535 bool "Marvell Orion"
536 depends on MMU
c750815e 537 select CPU_FEROCEON
038ee083 538 select PCI
a8865655 539 select ARCH_REQUIRE_GPIOLIB
51cbff1d 540 select GENERIC_CLOCKEVENTS
69b02f6a 541 select PLAT_ORION
585cf175 542 help
9dd0b194 543 Support for the following Marvell Orion 5x series SoCs:
d2b2a6bb 544 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
d323ade1 545 Orion-2 (5281), Orion-1-90 (6183).
585cf175 546
788c9700 547config ARCH_MMP
2f7e8fae 548 bool "Marvell PXA168/910/MMP2"
788c9700 549 depends on MMU
788c9700 550 select ARCH_REQUIRE_GPIOLIB
6d803ba7 551 select CLKDEV_LOOKUP
788c9700 552 select GENERIC_CLOCKEVENTS
28bb7bc6 553 select HAVE_SCHED_CLOCK
788c9700
RK
554 select TICK_ONESHOT
555 select PLAT_PXA
0bd86961 556 select SPARSE_IRQ
788c9700 557 help
2f7e8fae 558 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
788c9700
RK
559
560config ARCH_KS8695
561 bool "Micrel/Kendin KS8695"
562 select CPU_ARM922T
98830bc9 563 select ARCH_REQUIRE_GPIOLIB
5cfc8ee0 564 select ARCH_USES_GETTIMEOFFSET
788c9700
RK
565 help
566 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
567 System-on-Chip devices.
568
788c9700
RK
569config ARCH_W90X900
570 bool "Nuvoton W90X900 CPU"
571 select CPU_ARM926T
c52d3d68 572 select ARCH_REQUIRE_GPIOLIB
6d803ba7 573 select CLKDEV_LOOKUP
6fa5d5f7 574 select CLKSRC_MMIO
58b5369e 575 select GENERIC_CLOCKEVENTS
788c9700 576 help
a8bc4ead 577 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
578 At present, the w90x900 has been renamed nuc900, regarding
579 the ARM series product line, you can login the following
580 link address to know more.
581
582 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
583 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
788c9700 584
a62e9030 585config ARCH_NUC93X
586 bool "Nuvoton NUC93X CPU"
587 select CPU_ARM926T
6d803ba7 588 select CLKDEV_LOOKUP
a62e9030 589 help
590 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
591 low-power and high performance MPEG-4/JPEG multimedia controller chip.
592
c5f80065
EG
593config ARCH_TEGRA
594 bool "NVIDIA Tegra"
4073723a 595 select CLKDEV_LOOKUP
234b6ced 596 select CLKSRC_MMIO
c5f80065
EG
597 select GENERIC_TIME
598 select GENERIC_CLOCKEVENTS
599 select GENERIC_GPIO
600 select HAVE_CLK
e3f4c0ab 601 select HAVE_SCHED_CLOCK
7056d423 602 select ARCH_HAS_CPUFREQ
c5f80065
EG
603 help
604 This enables support for NVIDIA Tegra based systems (Tegra APX,
605 Tegra 6xx and Tegra 2 series).
606
4af6fee1
DS
607config ARCH_PNX4008
608 bool "Philips Nexperia PNX4008 Mobile"
c750815e 609 select CPU_ARM926T
6d803ba7 610 select CLKDEV_LOOKUP
5cfc8ee0 611 select ARCH_USES_GETTIMEOFFSET
4af6fee1
DS
612 help
613 This enables support for Philips PNX4008 mobile platform.
614
1da177e4 615config ARCH_PXA
2c8086a5 616 bool "PXA2xx/PXA3xx-based"
a4f7e763 617 depends on MMU
034d2f5a 618 select ARCH_MTD_XIP
89c52ed4 619 select ARCH_HAS_CPUFREQ
6d803ba7 620 select CLKDEV_LOOKUP
234b6ced 621 select CLKSRC_MMIO
7444a72e 622 select ARCH_REQUIRE_GPIOLIB
981d0f39 623 select GENERIC_CLOCKEVENTS
7ce83018 624 select HAVE_SCHED_CLOCK
a88264c2 625 select TICK_ONESHOT
bd5ce433 626 select PLAT_PXA
6ac6b817 627 select SPARSE_IRQ
4e234cc0 628 select AUTO_ZRELADDR
8a97ae2f 629 select MULTI_IRQ_HANDLER
f999b8bd 630 help
2c8086a5 631 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
1da177e4 632
788c9700
RK
633config ARCH_MSM
634 bool "Qualcomm MSM"
4b536b8d 635 select HAVE_CLK
49cbe786 636 select GENERIC_CLOCKEVENTS
923a081c 637 select ARCH_REQUIRE_GPIOLIB
bd32344a 638 select CLKDEV_LOOKUP
49cbe786 639 help
4b53eb4f
DW
640 Support for Qualcomm MSM/QSD based systems. This runs on the
641 apps processor of the MSM/QSD and depends on a shared memory
642 interface to the modem processor which runs the baseband
643 stack and controls some vital subsystems
644 (clock and power control, etc).
49cbe786 645
c793c1b0 646config ARCH_SHMOBILE
6d72ad35
PM
647 bool "Renesas SH-Mobile / R-Mobile"
648 select HAVE_CLK
5e93c6b4 649 select CLKDEV_LOOKUP
aa3831cf 650 select HAVE_MACH_CLKDEV
6d72ad35
PM
651 select GENERIC_CLOCKEVENTS
652 select NO_IOPORT
653 select SPARSE_IRQ
60f1435c 654 select MULTI_IRQ_HANDLER
e3e01091 655 select PM_GENERIC_DOMAINS if PM
c793c1b0 656 help
6d72ad35 657 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
c793c1b0 658
1da177e4
LT
659config ARCH_RPC
660 bool "RiscPC"
661 select ARCH_ACORN
662 select FIQ
663 select TIMER_ACORN
a08b6b79 664 select ARCH_MAY_HAVE_PC_FDC
341eb781 665 select HAVE_PATA_PLATFORM
065909b9 666 select ISA_DMA_API
5ea81769 667 select NO_IOPORT
07f841b7 668 select ARCH_SPARSEMEM_ENABLE
5cfc8ee0 669 select ARCH_USES_GETTIMEOFFSET
1da177e4
LT
670 help
671 On the Acorn Risc-PC, Linux can support the internal IDE disk and
672 CD-ROM interface, serial and parallel port, and the floppy drive.
673
674config ARCH_SA1100
675 bool "SA1100-based"
234b6ced 676 select CLKSRC_MMIO
c750815e 677 select CPU_SA1100
f7e68bbf 678 select ISA
05944d74 679 select ARCH_SPARSEMEM_ENABLE
034d2f5a 680 select ARCH_MTD_XIP
89c52ed4 681 select ARCH_HAS_CPUFREQ
1937f5b9 682 select CPU_FREQ
3e238be2 683 select GENERIC_CLOCKEVENTS
9483a578 684 select HAVE_CLK
5094b92f 685 select HAVE_SCHED_CLOCK
3e238be2 686 select TICK_ONESHOT
7444a72e 687 select ARCH_REQUIRE_GPIOLIB
f999b8bd
MM
688 help
689 Support for StrongARM 11x0 based boards.
1da177e4
LT
690
691config ARCH_S3C2410
63b1f51b 692 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
0a938b97 693 select GENERIC_GPIO
9d56c02a 694 select ARCH_HAS_CPUFREQ
9483a578 695 select HAVE_CLK
e83626f2 696 select CLKDEV_LOOKUP
5cfc8ee0 697 select ARCH_USES_GETTIMEOFFSET
20676c15 698 select HAVE_S3C2410_I2C if I2C
1da177e4
LT
699 help
700 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
701 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
f6c8965a 702 the Samsung SMDK2410 development board (and derivatives).
1da177e4 703
63b1f51b 704 Note, the S3C2416 and the S3C2450 are so close that they even share
25985edc 705 the same SoC ID code. This means that there is no separate machine
63b1f51b
BD
706 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
707
a08ab637
BD
708config ARCH_S3C64XX
709 bool "Samsung S3C64XX"
89f1fa08 710 select PLAT_SAMSUNG
89f0ce72 711 select CPU_V6
89f0ce72 712 select ARM_VIC
a08ab637 713 select HAVE_CLK
226e85f4 714 select CLKDEV_LOOKUP
89f0ce72 715 select NO_IOPORT
5cfc8ee0 716 select ARCH_USES_GETTIMEOFFSET
89c52ed4 717 select ARCH_HAS_CPUFREQ
89f0ce72
BD
718 select ARCH_REQUIRE_GPIOLIB
719 select SAMSUNG_CLKSRC
720 select SAMSUNG_IRQ_VIC_TIMER
721 select SAMSUNG_IRQ_UART
722 select S3C_GPIO_TRACK
723 select S3C_GPIO_PULL_UPDOWN
724 select S3C_GPIO_CFG_S3C24XX
725 select S3C_GPIO_CFG_S3C64XX
726 select S3C_DEV_NAND
727 select USB_ARCH_HAS_OHCI
728 select SAMSUNG_GPIOLIB_4BIT
20676c15 729 select HAVE_S3C2410_I2C if I2C
c39d8d55 730 select HAVE_S3C2410_WATCHDOG if WATCHDOG
a08ab637
BD
731 help
732 Samsung S3C64XX series based systems
733
49b7a491
KK
734config ARCH_S5P64X0
735 bool "Samsung S5P6440 S5P6450"
c4ffccdd
KK
736 select CPU_V6
737 select GENERIC_GPIO
738 select HAVE_CLK
d8b22d25 739 select CLKDEV_LOOKUP
0665ccc4 740 select CLKSRC_MMIO
c39d8d55 741 select HAVE_S3C2410_WATCHDOG if WATCHDOG
9e65bbf2
SK
742 select GENERIC_CLOCKEVENTS
743 select HAVE_SCHED_CLOCK
20676c15 744 select HAVE_S3C2410_I2C if I2C
754961a8 745 select HAVE_S3C_RTC if RTC_CLASS
c4ffccdd 746 help
49b7a491
KK
747 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
748 SMDK6450.
c4ffccdd 749
acc84707
MS
750config ARCH_S5PC100
751 bool "Samsung S5PC100"
5a7652f2
BM
752 select GENERIC_GPIO
753 select HAVE_CLK
29e8eb0f 754 select CLKDEV_LOOKUP
5a7652f2 755 select CPU_V7
d6d502fa 756 select ARM_L1_CACHE_SHIFT_6
925c68cd 757 select ARCH_USES_GETTIMEOFFSET
20676c15 758 select HAVE_S3C2410_I2C if I2C
754961a8 759 select HAVE_S3C_RTC if RTC_CLASS
c39d8d55 760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
5a7652f2 761 help
acc84707 762 Samsung S5PC100 series based systems
5a7652f2 763
170f4e42
KK
764config ARCH_S5PV210
765 bool "Samsung S5PV210/S5PC110"
766 select CPU_V7
eecb6a84 767 select ARCH_SPARSEMEM_ENABLE
0f75a96b 768 select ARCH_HAS_HOLES_MEMORYMODEL
170f4e42
KK
769 select GENERIC_GPIO
770 select HAVE_CLK
b2a9dd46 771 select CLKDEV_LOOKUP
0665ccc4 772 select CLKSRC_MMIO
170f4e42 773 select ARM_L1_CACHE_SHIFT_6
d8144aea 774 select ARCH_HAS_CPUFREQ
9e65bbf2
SK
775 select GENERIC_CLOCKEVENTS
776 select HAVE_SCHED_CLOCK
20676c15 777 select HAVE_S3C2410_I2C if I2C
754961a8 778 select HAVE_S3C_RTC if RTC_CLASS
c39d8d55 779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
170f4e42
KK
780 help
781 Samsung S5PV210/S5PC110 series based systems
782
10606aad
KK
783config ARCH_EXYNOS4
784 bool "Samsung EXYNOS4"
cc0e72b8 785 select CPU_V7
f567fa6f 786 select ARCH_SPARSEMEM_ENABLE
0f75a96b 787 select ARCH_HAS_HOLES_MEMORYMODEL
cc0e72b8
CY
788 select GENERIC_GPIO
789 select HAVE_CLK
badc4f2d 790 select CLKDEV_LOOKUP
b333fb16 791 select ARCH_HAS_CPUFREQ
cc0e72b8 792 select GENERIC_CLOCKEVENTS
754961a8 793 select HAVE_S3C_RTC if RTC_CLASS
20676c15 794 select HAVE_S3C2410_I2C if I2C
c39d8d55 795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
cc0e72b8 796 help
10606aad 797 Samsung EXYNOS4 series based systems
cc0e72b8 798
1da177e4
LT
799config ARCH_SHARK
800 bool "Shark"
c750815e 801 select CPU_SA110
f7e68bbf
RK
802 select ISA
803 select ISA_DMA
3bca103a 804 select ZONE_DMA
f7e68bbf 805 select PCI
5cfc8ee0 806 select ARCH_USES_GETTIMEOFFSET
f999b8bd
MM
807 help
808 Support for the StrongARM based Digital DNARD machine, also known
809 as "Shark" (<http://www.shark-linux.de/shark.html>).
1da177e4 810
83ef3338
HK
811config ARCH_TCC_926
812 bool "Telechips TCC ARM926-based systems"
234b6ced 813 select CLKSRC_MMIO
83ef3338
HK
814 select CPU_ARM926T
815 select HAVE_CLK
6d803ba7 816 select CLKDEV_LOOKUP
83ef3338
HK
817 select GENERIC_CLOCKEVENTS
818 help
819 Support for Telechips TCC ARM926-based systems.
820
d98aac75
LW
821config ARCH_U300
822 bool "ST-Ericsson U300 Series"
823 depends on MMU
234b6ced 824 select CLKSRC_MMIO
d98aac75 825 select CPU_ARM926T
5c21b7ca 826 select HAVE_SCHED_CLOCK
bc581770 827 select HAVE_TCM
d98aac75
LW
828 select ARM_AMBA
829 select ARM_VIC
d98aac75 830 select GENERIC_CLOCKEVENTS
6d803ba7 831 select CLKDEV_LOOKUP
aa3831cf 832 select HAVE_MACH_CLKDEV
d98aac75
LW
833 select GENERIC_GPIO
834 help
835 Support for ST-Ericsson U300 series mobile platforms.
836
ccf50e23
RK
837config ARCH_U8500
838 bool "ST-Ericsson U8500 Series"
839 select CPU_V7
840 select ARM_AMBA
ccf50e23 841 select GENERIC_CLOCKEVENTS
6d803ba7 842 select CLKDEV_LOOKUP
94bdc0e2 843 select ARCH_REQUIRE_GPIOLIB
7c1a70e9 844 select ARCH_HAS_CPUFREQ
ccf50e23
RK
845 help
846 Support for ST-Ericsson's Ux500 architecture
847
848config ARCH_NOMADIK
849 bool "STMicroelectronics Nomadik"
850 select ARM_AMBA
851 select ARM_VIC
852 select CPU_ARM926T
6d803ba7 853 select CLKDEV_LOOKUP
ccf50e23 854 select GENERIC_CLOCKEVENTS
ccf50e23
RK
855 select ARCH_REQUIRE_GPIOLIB
856 help
857 Support for the Nomadik platform by ST-Ericsson
858
7c6337e2
KH
859config ARCH_DAVINCI
860 bool "TI DaVinci"
7c6337e2 861 select GENERIC_CLOCKEVENTS
dce1115b 862 select ARCH_REQUIRE_GPIOLIB
3bca103a 863 select ZONE_DMA
9232fcc9 864 select HAVE_IDE
6d803ba7 865 select CLKDEV_LOOKUP
20e9969b 866 select GENERIC_ALLOCATOR
dc7ad3b3 867 select GENERIC_IRQ_CHIP
ae88e05a 868 select ARCH_HAS_HOLES_MEMORYMODEL
7c6337e2
KH
869 help
870 Support for TI's DaVinci platform.
871
3b938be6
RK
872config ARCH_OMAP
873 bool "TI OMAP"
9483a578 874 select HAVE_CLK
7444a72e 875 select ARCH_REQUIRE_GPIOLIB
89c52ed4 876 select ARCH_HAS_CPUFREQ
354a183f 877 select CLKSRC_MMIO
06cad098 878 select GENERIC_CLOCKEVENTS
dc548fbb 879 select HAVE_SCHED_CLOCK
9af915da 880 select ARCH_HAS_HOLES_MEMORYMODEL
3b938be6 881 help
6e457bb0 882 Support for TI's OMAP platform (OMAP1/2/3/4).
3b938be6 883
cee37e50 884config PLAT_SPEAR
885 bool "ST SPEAr"
886 select ARM_AMBA
887 select ARCH_REQUIRE_GPIOLIB
6d803ba7 888 select CLKDEV_LOOKUP
d6e15d78 889 select CLKSRC_MMIO
cee37e50 890 select GENERIC_CLOCKEVENTS
cee37e50 891 select HAVE_CLK
892 help
893 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
894
21f47fbc
AC
895config ARCH_VT8500
896 bool "VIA/WonderMedia 85xx"
897 select CPU_ARM926T
898 select GENERIC_GPIO
899 select ARCH_HAS_CPUFREQ
900 select GENERIC_CLOCKEVENTS
901 select ARCH_REQUIRE_GPIOLIB
902 select HAVE_PWM
903 help
904 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
02c981c0 905
b85a3ef4
JL
906config ARCH_ZYNQ
907 bool "Xilinx Zynq ARM Cortex A9 Platform"
02c981c0
BD
908 select CPU_V7
909 select GENERIC_TIME
02c981c0
BD
910 select GENERIC_CLOCKEVENTS
911 select CLKDEV_LOOKUP
b85a3ef4
JL
912 select ARM_GIC
913 select ARM_AMBA
914 select ICST
02c981c0 915 select USE_OF
02c981c0 916 help
b85a3ef4 917 Support for Xilinx Zynq ARM Cortex A9 Platform
1da177e4
LT
918endchoice
919
ccf50e23
RK
920#
921# This is sorted alphabetically by mach-* pathname. However, plat-*
922# Kconfigs may be included either alphabetically (according to the
923# plat- suffix) or along side the corresponding mach-* source.
924#
95b8f20f
RK
925source "arch/arm/mach-at91/Kconfig"
926
927source "arch/arm/mach-bcmring/Kconfig"
928
1da177e4
LT
929source "arch/arm/mach-clps711x/Kconfig"
930
d94f944e
AV
931source "arch/arm/mach-cns3xxx/Kconfig"
932
95b8f20f
RK
933source "arch/arm/mach-davinci/Kconfig"
934
935source "arch/arm/mach-dove/Kconfig"
936
e7736d47
LB
937source "arch/arm/mach-ep93xx/Kconfig"
938
1da177e4
LT
939source "arch/arm/mach-footbridge/Kconfig"
940
59d3a193
PZ
941source "arch/arm/mach-gemini/Kconfig"
942
95b8f20f
RK
943source "arch/arm/mach-h720x/Kconfig"
944
1da177e4
LT
945source "arch/arm/mach-integrator/Kconfig"
946
3f7e5815
LB
947source "arch/arm/mach-iop32x/Kconfig"
948
949source "arch/arm/mach-iop33x/Kconfig"
1da177e4 950
285f5fa7
DW
951source "arch/arm/mach-iop13xx/Kconfig"
952
1da177e4
LT
953source "arch/arm/mach-ixp4xx/Kconfig"
954
955source "arch/arm/mach-ixp2000/Kconfig"
956
c4713074
LB
957source "arch/arm/mach-ixp23xx/Kconfig"
958
95b8f20f
RK
959source "arch/arm/mach-kirkwood/Kconfig"
960
961source "arch/arm/mach-ks8695/Kconfig"
962
40805949
KW
963source "arch/arm/mach-lpc32xx/Kconfig"
964
95b8f20f
RK
965source "arch/arm/mach-msm/Kconfig"
966
794d15b2
SS
967source "arch/arm/mach-mv78xx0/Kconfig"
968
95b8f20f 969source "arch/arm/plat-mxc/Kconfig"
1da177e4 970
1d3f33d5
SG
971source "arch/arm/mach-mxs/Kconfig"
972
95b8f20f 973source "arch/arm/mach-netx/Kconfig"
49cbe786 974
95b8f20f
RK
975source "arch/arm/mach-nomadik/Kconfig"
976source "arch/arm/plat-nomadik/Kconfig"
977
186f93ea 978source "arch/arm/mach-nuc93x/Kconfig"
1da177e4 979
d48af15e
TL
980source "arch/arm/plat-omap/Kconfig"
981
982source "arch/arm/mach-omap1/Kconfig"
1da177e4 983
1dbae815
TL
984source "arch/arm/mach-omap2/Kconfig"
985
9dd0b194 986source "arch/arm/mach-orion5x/Kconfig"
585cf175 987
95b8f20f
RK
988source "arch/arm/mach-pxa/Kconfig"
989source "arch/arm/plat-pxa/Kconfig"
585cf175 990
95b8f20f
RK
991source "arch/arm/mach-mmp/Kconfig"
992
993source "arch/arm/mach-realview/Kconfig"
994
995source "arch/arm/mach-sa1100/Kconfig"
edabd38e 996
cf383678 997source "arch/arm/plat-samsung/Kconfig"
a21765a7 998source "arch/arm/plat-s3c24xx/Kconfig"
c4ffccdd 999source "arch/arm/plat-s5p/Kconfig"
a21765a7 1000
cee37e50 1001source "arch/arm/plat-spear/Kconfig"
a21765a7 1002
83ef3338
HK
1003source "arch/arm/plat-tcc/Kconfig"
1004
a21765a7 1005if ARCH_S3C2410
1da177e4 1006source "arch/arm/mach-s3c2410/Kconfig"
a21765a7 1007source "arch/arm/mach-s3c2412/Kconfig"
f1290a49 1008source "arch/arm/mach-s3c2416/Kconfig"
a21765a7 1009source "arch/arm/mach-s3c2440/Kconfig"
e4d06e39 1010source "arch/arm/mach-s3c2443/Kconfig"
a21765a7 1011endif
1da177e4 1012
a08ab637 1013if ARCH_S3C64XX
431107ea 1014source "arch/arm/mach-s3c64xx/Kconfig"
a08ab637
BD
1015endif
1016
49b7a491 1017source "arch/arm/mach-s5p64x0/Kconfig"
c4ffccdd 1018
5a7652f2 1019source "arch/arm/mach-s5pc100/Kconfig"
5a7652f2 1020
170f4e42
KK
1021source "arch/arm/mach-s5pv210/Kconfig"
1022
10606aad 1023source "arch/arm/mach-exynos4/Kconfig"
cc0e72b8 1024
882d01f9 1025source "arch/arm/mach-shmobile/Kconfig"
52c543f9 1026
c5f80065
EG
1027source "arch/arm/mach-tegra/Kconfig"
1028
95b8f20f 1029source "arch/arm/mach-u300/Kconfig"
1da177e4 1030
95b8f20f 1031source "arch/arm/mach-ux500/Kconfig"
1da177e4
LT
1032
1033source "arch/arm/mach-versatile/Kconfig"
1034
ceade897 1035source "arch/arm/mach-vexpress/Kconfig"
420c34e4 1036source "arch/arm/plat-versatile/Kconfig"
ceade897 1037
21f47fbc
AC
1038source "arch/arm/mach-vt8500/Kconfig"
1039
7ec80ddf 1040source "arch/arm/mach-w90x900/Kconfig"
1041
1da177e4
LT
1042# Definitions to make life easier
1043config ARCH_ACORN
1044 bool
1045
7ae1f7ec
LB
1046config PLAT_IOP
1047 bool
469d3044 1048 select GENERIC_CLOCKEVENTS
08f26b1e 1049 select HAVE_SCHED_CLOCK
7ae1f7ec 1050
69b02f6a
LB
1051config PLAT_ORION
1052 bool
bfe45e0b 1053 select CLKSRC_MMIO
dc7ad3b3 1054 select GENERIC_IRQ_CHIP
f06a1624 1055 select HAVE_SCHED_CLOCK
69b02f6a 1056
bd5ce433
EM
1057config PLAT_PXA
1058 bool
1059
f4b8b319
RK
1060config PLAT_VERSATILE
1061 bool
1062
e3887714
RK
1063config ARM_TIMER_SP804
1064 bool
bfe45e0b 1065 select CLKSRC_MMIO
e3887714 1066
1da177e4
LT
1067source arch/arm/mm/Kconfig
1068
afe4b25e
LB
1069config IWMMXT
1070 bool "Enable iWMMXt support"
ef6c8445
HZ
1071 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1072 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
afe4b25e
LB
1073 help
1074 Enable support for iWMMXt context switching at run time if
1075 running on a CPU that supports it.
1076
1da177e4
LT
1077# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1078config XSCALE_PMU
1079 bool
1080 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1081 default y
1082
0f4f0672 1083config CPU_HAS_PMU
e399b1a4 1084 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
8954bb0d 1085 (!ARCH_OMAP3 || OMAP3_EMU)
0f4f0672
JI
1086 default y
1087 bool
1088
52108641 1089config MULTI_IRQ_HANDLER
1090 bool
1091 help
1092 Allow each machine to specify it's own IRQ handler at run time.
1093
3b93e7b0
HC
1094if !MMU
1095source "arch/arm/Kconfig-nommu"
1096endif
1097
9cba3ccc
CM
1098config ARM_ERRATA_411920
1099 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
e399b1a4 1100 depends on CPU_V6 || CPU_V6K
9cba3ccc
CM
1101 help
1102 Invalidation of the Instruction Cache operation can
1103 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1104 It does not affect the MPCore. This option enables the ARM Ltd.
1105 recommended workaround.
1106
7ce236fc
CM
1107config ARM_ERRATA_430973
1108 bool "ARM errata: Stale prediction on replaced interworking branch"
1109 depends on CPU_V7
1110 help
1111 This option enables the workaround for the 430973 Cortex-A8
1112 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1113 interworking branch is replaced with another code sequence at the
1114 same virtual address, whether due to self-modifying code or virtual
1115 to physical address re-mapping, Cortex-A8 does not recover from the
1116 stale interworking branch prediction. This results in Cortex-A8
1117 executing the new code sequence in the incorrect ARM or Thumb state.
1118 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1119 and also flushes the branch target cache at every context switch.
1120 Note that setting specific bits in the ACTLR register may not be
1121 available in non-secure mode.
1122
855c551f
CM
1123config ARM_ERRATA_458693
1124 bool "ARM errata: Processor deadlock when a false hazard is created"
1125 depends on CPU_V7
1126 help
1127 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1128 erratum. For very specific sequences of memory operations, it is
1129 possible for a hazard condition intended for a cache line to instead
1130 be incorrectly associated with a different cache line. This false
1131 hazard might then cause a processor deadlock. The workaround enables
1132 the L1 caching of the NEON accesses and disables the PLD instruction
1133 in the ACTLR register. Note that setting specific bits in the ACTLR
1134 register may not be available in non-secure mode.
1135
0516e464
CM
1136config ARM_ERRATA_460075
1137 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1138 depends on CPU_V7
1139 help
1140 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1141 erratum. Any asynchronous access to the L2 cache may encounter a
1142 situation in which recent store transactions to the L2 cache are lost
1143 and overwritten with stale memory contents from external memory. The
1144 workaround disables the write-allocate mode for the L2 cache via the
1145 ACTLR register. Note that setting specific bits in the ACTLR register
1146 may not be available in non-secure mode.
1147
9f05027c
WD
1148config ARM_ERRATA_742230
1149 bool "ARM errata: DMB operation may be faulty"
1150 depends on CPU_V7 && SMP
1151 help
1152 This option enables the workaround for the 742230 Cortex-A9
1153 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1154 between two write operations may not ensure the correct visibility
1155 ordering of the two writes. This workaround sets a specific bit in
1156 the diagnostic register of the Cortex-A9 which causes the DMB
1157 instruction to behave as a DSB, ensuring the correct behaviour of
1158 the two writes.
1159
a672e99b
WD
1160config ARM_ERRATA_742231
1161 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1162 depends on CPU_V7 && SMP
1163 help
1164 This option enables the workaround for the 742231 Cortex-A9
1165 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1166 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1167 accessing some data located in the same cache line, may get corrupted
1168 data due to bad handling of the address hazard when the line gets
1169 replaced from one of the CPUs at the same time as another CPU is
1170 accessing it. This workaround sets specific bits in the diagnostic
1171 register of the Cortex-A9 which reduces the linefill issuing
1172 capabilities of the processor.
1173
9e65582a
SS
1174config PL310_ERRATA_588369
1175 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
2839e06c 1176 depends on CACHE_L2X0
9e65582a
SS
1177 help
1178 The PL310 L2 cache controller implements three types of Clean &
1179 Invalidate maintenance operations: by Physical Address
1180 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1181 They are architecturally defined to behave as the execution of a
1182 clean operation followed immediately by an invalidate operation,
1183 both performing to the same memory location. This functionality
1184 is not correctly implemented in PL310 as clean lines are not
2839e06c 1185 invalidated as a result of these operations.
cdf357f1
WD
1186
1187config ARM_ERRATA_720789
1188 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1189 depends on CPU_V7 && SMP
1190 help
1191 This option enables the workaround for the 720789 Cortex-A9 (prior to
1192 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1193 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1194 As a consequence of this erratum, some TLB entries which should be
1195 invalidated are not, resulting in an incoherency in the system page
1196 tables. The workaround changes the TLB flushing routines to invalidate
1197 entries regardless of the ASID.
475d92fc 1198
1f0090a1
RK
1199config PL310_ERRATA_727915
1200 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1201 depends on CACHE_L2X0
1202 help
1203 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1204 operation (offset 0x7FC). This operation runs in background so that
1205 PL310 can handle normal accesses while it is in progress. Under very
1206 rare circumstances, due to this erratum, write data can be lost when
1207 PL310 treats a cacheable write transaction during a Clean &
1208 Invalidate by Way operation.
1209
475d92fc
WD
1210config ARM_ERRATA_743622
1211 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1212 depends on CPU_V7
1213 help
1214 This option enables the workaround for the 743622 Cortex-A9
1215 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1216 optimisation in the Cortex-A9 Store Buffer may lead to data
1217 corruption. This workaround sets a specific bit in the diagnostic
1218 register of the Cortex-A9 which disables the Store Buffer
1219 optimisation, preventing the defect from occurring. This has no
1220 visible impact on the overall performance or power consumption of the
1221 processor.
1222
9a27c27c
WD
1223config ARM_ERRATA_751472
1224 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1225 depends on CPU_V7 && SMP
1226 help
1227 This option enables the workaround for the 751472 Cortex-A9 (prior
1228 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1229 completion of a following broadcasted operation if the second
1230 operation is received by a CPU before the ICIALLUIS has completed,
1231 potentially leading to corrupted entries in the cache or TLB.
1232
885028e4
SK
1233config ARM_ERRATA_753970
1234 bool "ARM errata: cache sync operation may be faulty"
1235 depends on CACHE_PL310
1236 help
1237 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1238
1239 Under some condition the effect of cache sync operation on
1240 the store buffer still remains when the operation completes.
1241 This means that the store buffer is always asked to drain and
1242 this prevents it from merging any further writes. The workaround
1243 is to replace the normal offset of cache sync operation (0x730)
1244 by another offset targeting an unmapped PL310 register 0x740.
1245 This has the same effect as the cache sync operation: store buffer
1246 drain and waiting for all buffers empty.
1247
fcbdc5fe
WD
1248config ARM_ERRATA_754322
1249 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1250 depends on CPU_V7
1251 help
1252 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1253 r3p*) erratum. A speculative memory access may cause a page table walk
1254 which starts prior to an ASID switch but completes afterwards. This
1255 can populate the micro-TLB with a stale entry which may be hit with
1256 the new ASID. This workaround places two dsb instructions in the mm
1257 switching code so that no page table walks can cross the ASID switch.
1258
5dab26af
WD
1259config ARM_ERRATA_754327
1260 bool "ARM errata: no automatic Store Buffer drain"
1261 depends on CPU_V7 && SMP
1262 help
1263 This option enables the workaround for the 754327 Cortex-A9 (prior to
1264 r2p0) erratum. The Store Buffer does not have any automatic draining
1265 mechanism and therefore a livelock may occur if an external agent
1266 continuously polls a memory location waiting to observe an update.
1267 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1268 written polling loops from denying visibility of updates to memory.
1269
1da177e4
LT
1270endmenu
1271
1272source "arch/arm/common/Kconfig"
1273
1da177e4
LT
1274menu "Bus support"
1275
1276config ARM_AMBA
1277 bool
1278
1279config ISA
1280 bool
1da177e4
LT
1281 help
1282 Find out whether you have ISA slots on your motherboard. ISA is the
1283 name of a bus system, i.e. the way the CPU talks to the other stuff
1284 inside your box. Other bus systems are PCI, EISA, MicroChannel
1285 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1286 newer boards don't support it. If you have ISA, say Y, otherwise N.
1287
065909b9 1288# Select ISA DMA controller support
1da177e4
LT
1289config ISA_DMA
1290 bool
065909b9 1291 select ISA_DMA_API
1da177e4 1292
065909b9 1293# Select ISA DMA interface
5cae841b
AV
1294config ISA_DMA_API
1295 bool
5cae841b 1296
1da177e4 1297config PCI
0b05da72 1298 bool "PCI support" if MIGHT_HAVE_PCI
1da177e4
LT
1299 help
1300 Find out whether you have a PCI motherboard. PCI is the name of a
1301 bus system, i.e. the way the CPU talks to the other stuff inside
1302 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1303 VESA. If you have PCI, say Y, otherwise N.
1304
52882173
AV
1305config PCI_DOMAINS
1306 bool
1307 depends on PCI
1308
b080ac8a
MRJ
1309config PCI_NANOENGINE
1310 bool "BSE nanoEngine PCI support"
1311 depends on SA1100_NANOENGINE
1312 help
1313 Enable PCI on the BSE nanoEngine board.
1314
36e23590
MW
1315config PCI_SYSCALL
1316 def_bool PCI
1317
1da177e4
LT
1318# Select the host bridge type
1319config PCI_HOST_VIA82C505
1320 bool
1321 depends on PCI && ARCH_SHARK
1322 default y
1323
a0113a99
MR
1324config PCI_HOST_ITE8152
1325 bool
1326 depends on PCI && MACH_ARMCORE
1327 default y
1328 select DMABOUNCE
1329
1da177e4
LT
1330source "drivers/pci/Kconfig"
1331
1332source "drivers/pcmcia/Kconfig"
1333
1334endmenu
1335
1336menu "Kernel Features"
1337
0567a0c0
KH
1338source "kernel/time/Kconfig"
1339
1da177e4 1340config SMP
bb2d8130 1341 bool "Symmetric Multi-Processing"
fbb4ddac 1342 depends on CPU_V6K || CPU_V7
bc28248e 1343 depends on GENERIC_CLOCKEVENTS
971acb9b 1344 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
89c3dedf 1345 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
10606aad 1346 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
e9d728f5 1347 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
f6dd9fa5 1348 select USE_GENERIC_SMP_HELPERS
89c3dedf 1349 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1da177e4
LT
1350 help
1351 This enables support for systems with more than one CPU. If you have
1352 a system with only one CPU, like most personal computers, say N. If
1353 you have a system with more than one CPU, say Y.
1354
1355 If you say N here, the kernel will run on single and multiprocessor
1356 machines, but will use only one CPU of a multiprocessor machine. If
1357 you say Y here, the kernel will run on many, but not all, single
1358 processor machines. On a single processor machine, the kernel will
1359 run faster if you say N here.
1360
03502faa 1361 See also <file:Documentation/i386/IO-APIC.txt>,
1da177e4 1362 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
50a23e6e 1363 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1da177e4
LT
1364
1365 If you don't know what to do here, say N.
1366
f00ec48f
RK
1367config SMP_ON_UP
1368 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1369 depends on EXPERIMENTAL
4d2692a7 1370 depends on SMP && !XIP_KERNEL
f00ec48f
RK
1371 default y
1372 help
1373 SMP kernels contain instructions which fail on non-SMP processors.
1374 Enabling this option allows the kernel to modify itself to make
1375 these instructions safe. Disabling it allows about 1K of space
1376 savings.
1377
1378 If you don't know what to do here, say Y.
1379
a8cbcd92
RK
1380config HAVE_ARM_SCU
1381 bool
a8cbcd92
RK
1382 help
1383 This option enables support for the ARM system coherency unit
1384
f32f4ce2
RK
1385config HAVE_ARM_TWD
1386 bool
1387 depends on SMP
15095bb0 1388 select TICK_ONESHOT
f32f4ce2
RK
1389 help
1390 This options enables support for the ARM timer and watchdog unit
1391
8d5796d2
LB
1392choice
1393 prompt "Memory split"
1394 default VMSPLIT_3G
1395 help
1396 Select the desired split between kernel and user memory.
1397
1398 If you are not absolutely sure what you are doing, leave this
1399 option alone!
1400
1401 config VMSPLIT_3G
1402 bool "3G/1G user/kernel split"
1403 config VMSPLIT_2G
1404 bool "2G/2G user/kernel split"
1405 config VMSPLIT_1G
1406 bool "1G/3G user/kernel split"
1407endchoice
1408
1409config PAGE_OFFSET
1410 hex
1411 default 0x40000000 if VMSPLIT_1G
1412 default 0x80000000 if VMSPLIT_2G
1413 default 0xC0000000
1414
1da177e4
LT
1415config NR_CPUS
1416 int "Maximum number of CPUs (2-32)"
1417 range 2 32
1418 depends on SMP
1419 default "4"
1420
a054a811
RK
1421config HOTPLUG_CPU
1422 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1423 depends on SMP && HOTPLUG && EXPERIMENTAL
1424 help
1425 Say Y here to experiment with turning CPUs off and on. CPUs
1426 can be controlled through /sys/devices/system/cpu.
1427
37ee16ae
RK
1428config LOCAL_TIMERS
1429 bool "Use local timer interrupts"
971acb9b 1430 depends on SMP
37ee16ae 1431 default y
30d8bead 1432 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
37ee16ae
RK
1433 help
1434 Enable support for local timers on SMP platforms, rather then the
1435 legacy IPI broadcast method. Local timers allows the system
1436 accounting to be spread across the timer interval, preventing a
1437 "thundering herd" at every timer tick.
1438
d45a398f 1439source kernel/Kconfig.preempt
1da177e4 1440
f8065813
RK
1441config HZ
1442 int
49b7a491 1443 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
a73ddc61 1444 ARCH_S5PV210 || ARCH_EXYNOS4
bfe65704 1445 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
5248c657 1446 default AT91_TIMER_HZ if ARCH_AT91
5da3e714 1447 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
f8065813
RK
1448 default 100
1449
16c79651 1450config THUMB2_KERNEL
4a50bfe3 1451 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
e399b1a4 1452 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
16c79651
CM
1453 select AEABI
1454 select ARM_ASM_UNIFIED
1455 help
1456 By enabling this option, the kernel will be compiled in
1457 Thumb-2 mode. A compiler/assembler that understand the unified
1458 ARM-Thumb syntax is needed.
1459
1460 If unsure, say N.
1461
6f685c5c
DM
1462config THUMB2_AVOID_R_ARM_THM_JUMP11
1463 bool "Work around buggy Thumb-2 short branch relocations in gas"
1464 depends on THUMB2_KERNEL && MODULES
1465 default y
1466 help
1467 Various binutils versions can resolve Thumb-2 branches to
1468 locally-defined, preemptible global symbols as short-range "b.n"
1469 branch instructions.
1470
1471 This is a problem, because there's no guarantee the final
1472 destination of the symbol, or any candidate locations for a
1473 trampoline, are within range of the branch. For this reason, the
1474 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1475 relocation in modules at all, and it makes little sense to add
1476 support.
1477
1478 The symptom is that the kernel fails with an "unsupported
1479 relocation" error when loading some modules.
1480
1481 Until fixed tools are available, passing
1482 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1483 code which hits this problem, at the cost of a bit of extra runtime
1484 stack usage in some cases.
1485
1486 The problem is described in more detail at:
1487 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1488
1489 Only Thumb-2 kernels are affected.
1490
1491 Unless you are sure your tools don't have this problem, say Y.
1492
0becb088
CM
1493config ARM_ASM_UNIFIED
1494 bool
1495
704bdda0
NP
1496config AEABI
1497 bool "Use the ARM EABI to compile the kernel"
1498 help
1499 This option allows for the kernel to be compiled using the latest
1500 ARM ABI (aka EABI). This is only useful if you are using a user
1501 space environment that is also compiled with EABI.
1502
1503 Since there are major incompatibilities between the legacy ABI and
1504 EABI, especially with regard to structure member alignment, this
1505 option also changes the kernel syscall calling convention to
1506 disambiguate both ABIs and allow for backward compatibility support
1507 (selected with CONFIG_OABI_COMPAT).
1508
1509 To use this you need GCC version 4.0.0 or later.
1510
6c90c872 1511config OABI_COMPAT
a73a3ff1 1512 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
9bc433a1 1513 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
6c90c872
NP
1514 default y
1515 help
1516 This option preserves the old syscall interface along with the
1517 new (ARM EABI) one. It also provides a compatibility layer to
1518 intercept syscalls that have structure arguments which layout
1519 in memory differs between the legacy ABI and the new ARM EABI
1520 (only for non "thumb" binaries). This option adds a tiny
1521 overhead to all syscalls and produces a slightly larger kernel.
1522 If you know you'll be using only pure EABI user space then you
1523 can say N here. If this option is not selected and you attempt
1524 to execute a legacy ABI binary then the result will be
1525 UNPREDICTABLE (in fact it can be predicted that it won't work
1526 at all). If in doubt say Y.
1527
eb33575c 1528config ARCH_HAS_HOLES_MEMORYMODEL
e80d6a24 1529 bool
e80d6a24 1530
05944d74
RK
1531config ARCH_SPARSEMEM_ENABLE
1532 bool
1533
07a2f737
RK
1534config ARCH_SPARSEMEM_DEFAULT
1535 def_bool ARCH_SPARSEMEM_ENABLE
1536
05944d74 1537config ARCH_SELECT_MEMORY_MODEL
be370302 1538 def_bool ARCH_SPARSEMEM_ENABLE
c80d79d7 1539
7b7bf499
WD
1540config HAVE_ARCH_PFN_VALID
1541 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1542
053a96ca 1543config HIGHMEM
e8db89a2
RK
1544 bool "High Memory Support"
1545 depends on MMU
053a96ca
NP
1546 help
1547 The address space of ARM processors is only 4 Gigabytes large
1548 and it has to accommodate user address space, kernel address
1549 space as well as some memory mapped IO. That means that, if you
1550 have a large amount of physical memory and/or IO, not all of the
1551 memory can be "permanently mapped" by the kernel. The physical
1552 memory that is not permanently mapped is called "high memory".
1553
1554 Depending on the selected kernel/user memory split, minimum
1555 vmalloc space and actual amount of RAM, you may not need this
1556 option which should result in a slightly faster kernel.
1557
1558 If unsure, say n.
1559
65cec8e3
RK
1560config HIGHPTE
1561 bool "Allocate 2nd-level pagetables from highmem"
1562 depends on HIGHMEM
65cec8e3 1563
1b8873a0
JI
1564config HW_PERF_EVENTS
1565 bool "Enable hardware performance counter support for perf events"
fe166148 1566 depends on PERF_EVENTS && CPU_HAS_PMU
1b8873a0
JI
1567 default y
1568 help
1569 Enable hardware performance counter support for perf events. If
1570 disabled, perf events will use software events only.
1571
3f22ab27
DH
1572source "mm/Kconfig"
1573
c1b2d970
MD
1574config FORCE_MAX_ZONEORDER
1575 int "Maximum zone order" if ARCH_SHMOBILE
1576 range 11 64 if ARCH_SHMOBILE
1577 default "9" if SA1111
1578 default "11"
1579 help
1580 The kernel memory allocator divides physically contiguous memory
1581 blocks into "zones", where each zone is a power of two number of
1582 pages. This option selects the largest power of two that the kernel
1583 keeps in the memory allocator. If you need to allocate very large
1584 blocks of physically contiguous memory, then you may need to
1585 increase this value.
1586
1587 This config option is actually maximum order plus one. For example,
1588 a value of 11 means that the largest free memory block is 2^10 pages.
1589
1da177e4
LT
1590config LEDS
1591 bool "Timer and CPU usage LEDs"
e055d5bf 1592 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
8c8fdbc9 1593 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1da177e4
LT
1594 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1595 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
73a59c1c 1596 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
25329671 1597 ARCH_AT91 || ARCH_DAVINCI || \
ff3042fb 1598 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1da177e4
LT
1599 help
1600 If you say Y here, the LEDs on your machine will be used
1601 to provide useful information about your current system status.
1602
1603 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1604 be able to select which LEDs are active using the options below. If
1605 you are compiling a kernel for the EBSA-110 or the LART however, the
1606 red LED will simply flash regularly to indicate that the system is
1607 still functional. It is safe to say Y here if you have a CATS
1608 system, but the driver will do nothing.
1609
1610config LEDS_TIMER
1611 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
eebdf7d7
DB
1612 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1613 || MACH_OMAP_PERSEUS2
1da177e4 1614 depends on LEDS
0567a0c0 1615 depends on !GENERIC_CLOCKEVENTS
1da177e4
LT
1616 default y if ARCH_EBSA110
1617 help
1618 If you say Y here, one of the system LEDs (the green one on the
1619 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1620 will flash regularly to indicate that the system is still
1621 operational. This is mainly useful to kernel hackers who are
1622 debugging unstable kernels.
1623
1624 The LART uses the same LED for both Timer LED and CPU usage LED
1625 functions. You may choose to use both, but the Timer LED function
1626 will overrule the CPU usage LED.
1627
1628config LEDS_CPU
1629 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
eebdf7d7
DB
1630 !ARCH_OMAP) \
1631 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1632 || MACH_OMAP_PERSEUS2
1da177e4
LT
1633 depends on LEDS
1634 help
1635 If you say Y here, the red LED will be used to give a good real
1636 time indication of CPU usage, by lighting whenever the idle task
1637 is not currently executing.
1638
1639 The LART uses the same LED for both Timer LED and CPU usage LED
1640 functions. You may choose to use both, but the Timer LED function
1641 will overrule the CPU usage LED.
1642
1643config ALIGNMENT_TRAP
1644 bool
f12d0d7c 1645 depends on CPU_CP15_MMU
1da177e4 1646 default y if !ARCH_EBSA110
e119bfff 1647 select HAVE_PROC_CPU if PROC_FS
1da177e4 1648 help
84eb8d06 1649 ARM processors cannot fetch/store information which is not
1da177e4
LT
1650 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1651 address divisible by 4. On 32-bit ARM processors, these non-aligned
1652 fetch/store instructions will be emulated in software if you say
1653 here, which has a severe performance impact. This is necessary for
1654 correct operation of some network protocols. With an IP-only
1655 configuration it is safe to say N, otherwise say Y.
1656
39ec58f3
LB
1657config UACCESS_WITH_MEMCPY
1658 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1659 depends on MMU && EXPERIMENTAL
1660 default y if CPU_FEROCEON
1661 help
1662 Implement faster copy_to_user and clear_user methods for CPU
1663 cores where a 8-word STM instruction give significantly higher
1664 memory write throughput than a sequence of individual 32bit stores.
1665
1666 A possible side effect is a slight increase in scheduling latency
1667 between threads sharing the same address space if they invoke
1668 such copy operations with large buffers.
1669
1670 However, if the CPU data cache is using a write-allocate mode,
1671 this option is unlikely to provide any performance gain.
1672
70c70d97
NP
1673config SECCOMP
1674 bool
1675 prompt "Enable seccomp to safely compute untrusted bytecode"
1676 ---help---
1677 This kernel feature is useful for number crunching applications
1678 that may need to compute untrusted bytecode during their
1679 execution. By using pipes or other transports made available to
1680 the process as file descriptors supporting the read/write
1681 syscalls, it's possible to isolate those applications in
1682 their own address space using seccomp. Once seccomp is
1683 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1684 and the task is only allowed to execute a few safe syscalls
1685 defined by each seccomp mode.
1686
c743f380
NP
1687config CC_STACKPROTECTOR
1688 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
4a50bfe3 1689 depends on EXPERIMENTAL
c743f380
NP
1690 help
1691 This option turns on the -fstack-protector GCC feature. This
1692 feature puts, at the beginning of functions, a canary value on
1693 the stack just before the return address, and validates
1694 the value just before actually returning. Stack based buffer
1695 overflows (that need to overwrite this return address) now also
1696 overwrite the canary, which gets detected and the attack is then
1697 neutralized via a kernel panic.
1698 This feature requires gcc version 4.2 or above.
1699
73a65b3f
UKK
1700config DEPRECATED_PARAM_STRUCT
1701 bool "Provide old way to pass kernel parameters"
1702 help
1703 This was deprecated in 2001 and announced to live on for 5 years.
1704 Some old boot loaders still use this way.
1705
1da177e4
LT
1706endmenu
1707
1708menu "Boot options"
1709
9eb8f674
GL
1710config USE_OF
1711 bool "Flattened Device Tree support"
1712 select OF
1713 select OF_EARLY_FLATTREE
08a543ad 1714 select IRQ_DOMAIN
9eb8f674
GL
1715 help
1716 Include support for flattened device tree machine descriptions.
1717
1da177e4
LT
1718# Compressed boot loader in ROM. Yes, we really want to ask about
1719# TEXT and BSS so we preserve their values in the config files.
1720config ZBOOT_ROM_TEXT
1721 hex "Compressed ROM boot loader base address"
1722 default "0"
1723 help
1724 The physical address at which the ROM-able zImage is to be
1725 placed in the target. Platforms which normally make use of
1726 ROM-able zImage formats normally set this to a suitable
1727 value in their defconfig file.
1728
1729 If ZBOOT_ROM is not enabled, this has no effect.
1730
1731config ZBOOT_ROM_BSS
1732 hex "Compressed ROM boot loader BSS address"
1733 default "0"
1734 help
f8c440b2
DF
1735 The base address of an area of read/write memory in the target
1736 for the ROM-able zImage which must be available while the
1737 decompressor is running. It must be large enough to hold the
1738 entire decompressed kernel plus an additional 128 KiB.
1739 Platforms which normally make use of ROM-able zImage formats
1740 normally set this to a suitable value in their defconfig file.
1da177e4
LT
1741
1742 If ZBOOT_ROM is not enabled, this has no effect.
1743
1744config ZBOOT_ROM
1745 bool "Compressed boot loader in ROM/flash"
1746 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1747 help
1748 Say Y here if you intend to execute your compressed kernel image
1749 (zImage) directly from ROM or flash. If unsure, say N.
1750
090ab3ff
SH
1751choice
1752 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1753 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1754 default ZBOOT_ROM_NONE
1755 help
1756 Include experimental SD/MMC loading code in the ROM-able zImage.
1757 With this enabled it is possible to write the the ROM-able zImage
1758 kernel image to an MMC or SD card and boot the kernel straight
1759 from the reset vector. At reset the processor Mask ROM will load
1760 the first part of the the ROM-able zImage which in turn loads the
1761 rest the kernel image to RAM.
1762
1763config ZBOOT_ROM_NONE
1764 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1765 help
1766 Do not load image from SD or MMC
1767
f45b1149
SH
1768config ZBOOT_ROM_MMCIF
1769 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
f45b1149 1770 help
090ab3ff
SH
1771 Load image from MMCIF hardware block.
1772
1773config ZBOOT_ROM_SH_MOBILE_SDHI
1774 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1775 help
1776 Load image from SDHI hardware block
1777
1778endchoice
f45b1149 1779
1da177e4
LT
1780config CMDLINE
1781 string "Default kernel command string"
1782 default ""
1783 help
1784 On some architectures (EBSA110 and CATS), there is currently no way
1785 for the boot loader to pass arguments to the kernel. For these
1786 architectures, you should supply some command-line options at build
1787 time by entering them here. As a minimum, you should specify the
1788 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1789
4394c124
VB
1790choice
1791 prompt "Kernel command line type" if CMDLINE != ""
1792 default CMDLINE_FROM_BOOTLOADER
1793
1794config CMDLINE_FROM_BOOTLOADER
1795 bool "Use bootloader kernel arguments if available"
1796 help
1797 Uses the command-line options passed by the boot loader. If
1798 the boot loader doesn't provide any, the default kernel command
1799 string provided in CMDLINE will be used.
1800
1801config CMDLINE_EXTEND
1802 bool "Extend bootloader kernel arguments"
1803 help
1804 The command-line arguments provided by the boot loader will be
1805 appended to the default kernel command string.
1806
92d2040d
AH
1807config CMDLINE_FORCE
1808 bool "Always use the default kernel command string"
92d2040d
AH
1809 help
1810 Always use the default kernel command string, even if the boot
1811 loader passes other arguments to the kernel.
1812 This is useful if you cannot or don't want to change the
1813 command-line options your boot loader passes to the kernel.
4394c124 1814endchoice
92d2040d 1815
1da177e4
LT
1816config XIP_KERNEL
1817 bool "Kernel Execute-In-Place from ROM"
1818 depends on !ZBOOT_ROM
1819 help
1820 Execute-In-Place allows the kernel to run from non-volatile storage
1821 directly addressable by the CPU, such as NOR flash. This saves RAM
1822 space since the text section of the kernel is not loaded from flash
1823 to RAM. Read-write sections, such as the data section and stack,
1824 are still copied to RAM. The XIP kernel is not compressed since
1825 it has to run directly from flash, so it will take more space to
1826 store it. The flash address used to link the kernel object files,
1827 and for storing it, is configuration dependent. Therefore, if you
1828 say Y here, you must know the proper physical address where to
1829 store the kernel image depending on your own flash memory usage.
1830
1831 Also note that the make target becomes "make xipImage" rather than
1832 "make zImage" or "make Image". The final kernel binary to put in
1833 ROM memory will be arch/arm/boot/xipImage.
1834
1835 If unsure, say N.
1836
1837config XIP_PHYS_ADDR
1838 hex "XIP Kernel Physical Location"
1839 depends on XIP_KERNEL
1840 default "0x00080000"
1841 help
1842 This is the physical address in your flash memory the kernel will
1843 be linked for and stored to. This address is dependent on your
1844 own flash usage.
1845
c587e4a6
RP
1846config KEXEC
1847 bool "Kexec system call (EXPERIMENTAL)"
1848 depends on EXPERIMENTAL
1849 help
1850 kexec is a system call that implements the ability to shutdown your
1851 current kernel, and to start another kernel. It is like a reboot
01dd2fbf 1852 but it is independent of the system firmware. And like a reboot
c587e4a6
RP
1853 you can start any kernel with it, not just Linux.
1854
1855 It is an ongoing process to be certain the hardware in a machine
1856 is properly shutdown, so do not be surprised if this code does not
1857 initially work for you. It may help to enable device hotplugging
1858 support.
1859
4cd9d6f7
RP
1860config ATAGS_PROC
1861 bool "Export atags in procfs"
b98d7291
UL
1862 depends on KEXEC
1863 default y
4cd9d6f7
RP
1864 help
1865 Should the atags used to boot the kernel be exported in an "atags"
1866 file in procfs. Useful with kexec.
1867
cb5d39b3
MW
1868config CRASH_DUMP
1869 bool "Build kdump crash kernel (EXPERIMENTAL)"
1870 depends on EXPERIMENTAL
1871 help
1872 Generate crash dump after being started by kexec. This should
1873 be normally only set in special crash dump kernels which are
1874 loaded in the main kernel with kexec-tools into a specially
1875 reserved region and then later executed after a crash by
1876 kdump/kexec. The crash dump kernel must be compiled to a
1877 memory address not used by the main kernel
1878
1879 For more details see Documentation/kdump/kdump.txt
1880
e69edc79
EM
1881config AUTO_ZRELADDR
1882 bool "Auto calculation of the decompressed kernel image address"
1883 depends on !ZBOOT_ROM && !ARCH_U300
1884 help
1885 ZRELADDR is the physical address where the decompressed kernel
1886 image will be placed. If AUTO_ZRELADDR is selected, the address
1887 will be determined at run-time by masking the current IP with
1888 0xf8000000. This assumes the zImage being placed in the first 128MB
1889 from start of memory.
1890
1da177e4
LT
1891endmenu
1892
ac9d7efc 1893menu "CPU Power Management"
1da177e4 1894
89c52ed4 1895if ARCH_HAS_CPUFREQ
1da177e4
LT
1896
1897source "drivers/cpufreq/Kconfig"
1898
64f102b6
YS
1899config CPU_FREQ_IMX
1900 tristate "CPUfreq driver for i.MX CPUs"
1901 depends on ARCH_MXC && CPU_FREQ
1902 help
1903 This enables the CPUfreq driver for i.MX CPUs.
1904
1da177e4
LT
1905config CPU_FREQ_SA1100
1906 bool
1da177e4
LT
1907
1908config CPU_FREQ_SA1110
1909 bool
1da177e4
LT
1910
1911config CPU_FREQ_INTEGRATOR
1912 tristate "CPUfreq driver for ARM Integrator CPUs"
1913 depends on ARCH_INTEGRATOR && CPU_FREQ
1914 default y
1915 help
1916 This enables the CPUfreq driver for ARM Integrator CPUs.
1917
1918 For details, take a look at <file:Documentation/cpu-freq>.
1919
1920 If in doubt, say Y.
1921
9e2697ff
RK
1922config CPU_FREQ_PXA
1923 bool
1924 depends on CPU_FREQ && ARCH_PXA && PXA25x
1925 default y
1926 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1927
9d56c02a
BD
1928config CPU_FREQ_S3C
1929 bool
1930 help
1931 Internal configuration node for common cpufreq on Samsung SoC
1932
1933config CPU_FREQ_S3C24XX
4a50bfe3 1934 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
9d56c02a
BD
1935 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1936 select CPU_FREQ_S3C
1937 help
1938 This enables the CPUfreq driver for the Samsung S3C24XX family
1939 of CPUs.
1940
1941 For details, take a look at <file:Documentation/cpu-freq>.
1942
1943 If in doubt, say N.
1944
1945config CPU_FREQ_S3C24XX_PLL
4a50bfe3 1946 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
9d56c02a
BD
1947 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1948 help
1949 Compile in support for changing the PLL frequency from the
1950 S3C24XX series CPUfreq driver. The PLL takes time to settle
1951 after a frequency change, so by default it is not enabled.
1952
1953 This also means that the PLL tables for the selected CPU(s) will
1954 be built which may increase the size of the kernel image.
1955
1956config CPU_FREQ_S3C24XX_DEBUG
1957 bool "Debug CPUfreq Samsung driver core"
1958 depends on CPU_FREQ_S3C24XX
1959 help
1960 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1961
1962config CPU_FREQ_S3C24XX_IODEBUG
1963 bool "Debug CPUfreq Samsung driver IO timing"
1964 depends on CPU_FREQ_S3C24XX
1965 help
1966 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1967
e6d197a6
BD
1968config CPU_FREQ_S3C24XX_DEBUGFS
1969 bool "Export debugfs for CPUFreq"
1970 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1971 help
1972 Export status information via debugfs.
1973
1da177e4
LT
1974endif
1975
ac9d7efc
RK
1976source "drivers/cpuidle/Kconfig"
1977
1978endmenu
1979
1da177e4
LT
1980menu "Floating point emulation"
1981
1982comment "At least one emulation must be selected"
1983
1984config FPE_NWFPE
1985 bool "NWFPE math emulation"
593c252a 1986 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1da177e4
LT
1987 ---help---
1988 Say Y to include the NWFPE floating point emulator in the kernel.
1989 This is necessary to run most binaries. Linux does not currently
1990 support floating point hardware so you need to say Y here even if
1991 your machine has an FPA or floating point co-processor podule.
1992
1993 You may say N here if you are going to load the Acorn FPEmulator
1994 early in the bootup.
1995
1996config FPE_NWFPE_XP
1997 bool "Support extended precision"
bedf142b 1998 depends on FPE_NWFPE
1da177e4
LT
1999 help
2000 Say Y to include 80-bit support in the kernel floating-point
2001 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2002 Note that gcc does not generate 80-bit operations by default,
2003 so in most cases this option only enlarges the size of the
2004 floating point emulator without any good reason.
2005
2006 You almost surely want to say N here.
2007
2008config FPE_FASTFPE
2009 bool "FastFPE math emulation (EXPERIMENTAL)"
8993a44c 2010 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1da177e4
LT
2011 ---help---
2012 Say Y here to include the FAST floating point emulator in the kernel.
2013 This is an experimental much faster emulator which now also has full
2014 precision for the mantissa. It does not support any exceptions.
2015 It is very simple, and approximately 3-6 times faster than NWFPE.
2016
2017 It should be sufficient for most programs. It may be not suitable
2018 for scientific calculations, but you have to check this for yourself.
2019 If you do not feel you need a faster FP emulation you should better
2020 choose NWFPE.
2021
2022config VFP
2023 bool "VFP-format floating point maths"
e399b1a4 2024 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1da177e4
LT
2025 help
2026 Say Y to include VFP support code in the kernel. This is needed
2027 if your hardware includes a VFP unit.
2028
2029 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2030 release notes and additional status information.
2031
2032 Say N if your target does not have VFP hardware.
2033
25ebee02
CM
2034config VFPv3
2035 bool
2036 depends on VFP
2037 default y if CPU_V7
2038
b5872db4
CM
2039config NEON
2040 bool "Advanced SIMD (NEON) Extension support"
2041 depends on VFPv3 && CPU_V7
2042 help
2043 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2044 Extension.
2045
1da177e4
LT
2046endmenu
2047
2048menu "Userspace binary formats"
2049
2050source "fs/Kconfig.binfmt"
2051
2052config ARTHUR
2053 tristate "RISC OS personality"
704bdda0 2054 depends on !AEABI
1da177e4
LT
2055 help
2056 Say Y here to include the kernel code necessary if you want to run
2057 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2058 experimental; if this sounds frightening, say N and sleep in peace.
2059 You can also say M here to compile this support as a module (which
2060 will be called arthur).
2061
2062endmenu
2063
2064menu "Power management options"
2065
eceab4ac 2066source "kernel/power/Kconfig"
1da177e4 2067
f4cb5700 2068config ARCH_SUSPEND_POSSIBLE
586893eb 2069 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
6a786182
RK
2070 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2071 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
f4cb5700
JB
2072 def_bool y
2073
1da177e4
LT
2074endmenu
2075
d5950b43
SR
2076source "net/Kconfig"
2077
ac25150f 2078source "drivers/Kconfig"
1da177e4
LT
2079
2080source "fs/Kconfig"
2081
1da177e4
LT
2082source "arch/arm/Kconfig.debug"
2083
2084source "security/Kconfig"
2085
2086source "crypto/Kconfig"
2087
2088source "lib/Kconfig"
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