Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
7563bbf8 | 4 | select ARCH_HAVE_CUSTOM_GPIO_H |
e17c6d56 | 5 | select HAVE_AOUT |
24056f52 | 6 | select HAVE_DMA_API_DEBUG |
d0ee9f40 | 7 | select HAVE_IDE if PCI || ISA || PCMCIA |
2dc6a016 | 8 | select HAVE_DMA_ATTRS |
c7909509 | 9 | select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7) |
2778f620 | 10 | select HAVE_MEMBLOCK |
12b824fb | 11 | select RTC_LIB |
75e7153a | 12 | select SYS_SUPPORTS_APM_EMULATION |
a41297a0 | 13 | select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) |
fe166148 | 14 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
09f05d85 | 15 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL |
5cbad0eb | 16 | select HAVE_ARCH_KGDB |
0693bf68 | 17 | select HAVE_ARCH_TRACEHOOK |
856bc356 | 18 | select HAVE_KPROBES if !XIP_KERNEL |
9edddaa2 | 19 | select HAVE_KRETPROBES if (HAVE_KPROBES) |
606576ce | 20 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
80be7a7f RV |
21 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
22 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) | |
0e341af8 | 23 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
e39f5602 | 24 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE |
1fe53268 | 25 | select HAVE_GENERIC_DMA_COHERENT |
e7db7b42 AT |
26 | select HAVE_KERNEL_GZIP |
27 | select HAVE_KERNEL_LZO | |
6e8699f7 | 28 | select HAVE_KERNEL_LZMA |
a7f464f3 | 29 | select HAVE_KERNEL_XZ |
e360adbe | 30 | select HAVE_IRQ_WORK |
7ada189f JI |
31 | select HAVE_PERF_EVENTS |
32 | select PERF_USE_VMALLOC | |
e513f8bf | 33 | select HAVE_REGS_AND_STACK_ACCESS_API |
e399b1a4 | 34 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
ed60453f | 35 | select HAVE_C_RECORDMCOUNT |
e2a93ecc | 36 | select HAVE_GENERIC_HARDIRQS |
37e74beb SB |
37 | select HARDIRQS_SW_RESEND |
38 | select GENERIC_IRQ_PROBE | |
25a5662a | 39 | select GENERIC_IRQ_SHOW |
d4aa8b15 TG |
40 | select GENERIC_IRQ_PROBE |
41 | select HARDIRQS_SW_RESEND | |
1fb90263 | 42 | select CPU_PM if (SUSPEND || CPU_IDLE) |
e5bfb72c | 43 | select GENERIC_PCI_IOMAP |
e47b65b0 | 44 | select HAVE_BPF_JIT |
84ec6d57 | 45 | select GENERIC_SMP_IDLE_THREAD |
3d92a71a AMG |
46 | select KTIME_SCALAR |
47 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP | |
1da177e4 LT |
48 | help |
49 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 50 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 51 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 52 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
53 | Europe. There is an ARM Linux project with a web page at |
54 | <http://www.arm.linux.org.uk/>. | |
55 | ||
74facffe RK |
56 | config ARM_HAS_SG_CHAIN |
57 | bool | |
58 | ||
4ce63fcd MS |
59 | config NEED_SG_DMA_LENGTH |
60 | bool | |
61 | ||
62 | config ARM_DMA_USE_IOMMU | |
63 | select NEED_SG_DMA_LENGTH | |
64 | select ARM_HAS_SG_CHAIN | |
65 | bool | |
66 | ||
1a189b97 RK |
67 | config HAVE_PWM |
68 | bool | |
69 | ||
0b05da72 HUK |
70 | config MIGHT_HAVE_PCI |
71 | bool | |
72 | ||
75e7153a RB |
73 | config SYS_SUPPORTS_APM_EMULATION |
74 | bool | |
75 | ||
0a938b97 DB |
76 | config GENERIC_GPIO |
77 | bool | |
0a938b97 | 78 | |
bc581770 LW |
79 | config HAVE_TCM |
80 | bool | |
81 | select GENERIC_ALLOCATOR | |
82 | ||
e119bfff RK |
83 | config HAVE_PROC_CPU |
84 | bool | |
85 | ||
5ea81769 AV |
86 | config NO_IOPORT |
87 | bool | |
5ea81769 | 88 | |
1da177e4 LT |
89 | config EISA |
90 | bool | |
91 | ---help--- | |
92 | The Extended Industry Standard Architecture (EISA) bus was | |
93 | developed as an open alternative to the IBM MicroChannel bus. | |
94 | ||
95 | The EISA bus provided some of the features of the IBM MicroChannel | |
96 | bus while maintaining backward compatibility with cards made for | |
97 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
98 | 1995 when it was made obsolete by the PCI bus. | |
99 | ||
100 | Say Y here if you are building a kernel for an EISA-based machine. | |
101 | ||
102 | Otherwise, say N. | |
103 | ||
104 | config SBUS | |
105 | bool | |
106 | ||
f16fb1ec RK |
107 | config STACKTRACE_SUPPORT |
108 | bool | |
109 | default y | |
110 | ||
f76e9154 NP |
111 | config HAVE_LATENCYTOP_SUPPORT |
112 | bool | |
113 | depends on !SMP | |
114 | default y | |
115 | ||
f16fb1ec RK |
116 | config LOCKDEP_SUPPORT |
117 | bool | |
118 | default y | |
119 | ||
7ad1bcb2 RK |
120 | config TRACE_IRQFLAGS_SUPPORT |
121 | bool | |
122 | default y | |
123 | ||
95c354fe NP |
124 | config GENERIC_LOCKBREAK |
125 | bool | |
126 | default y | |
127 | depends on SMP && PREEMPT | |
128 | ||
1da177e4 LT |
129 | config RWSEM_GENERIC_SPINLOCK |
130 | bool | |
131 | default y | |
132 | ||
133 | config RWSEM_XCHGADD_ALGORITHM | |
134 | bool | |
135 | ||
f0d1b0b3 DH |
136 | config ARCH_HAS_ILOG2_U32 |
137 | bool | |
f0d1b0b3 DH |
138 | |
139 | config ARCH_HAS_ILOG2_U64 | |
140 | bool | |
f0d1b0b3 | 141 | |
89c52ed4 BD |
142 | config ARCH_HAS_CPUFREQ |
143 | bool | |
144 | help | |
145 | Internal node to signify that the ARCH has CPUFREQ support | |
146 | and that the relevant menu configurations are displayed for | |
147 | it. | |
148 | ||
b89c3b16 AM |
149 | config GENERIC_HWEIGHT |
150 | bool | |
151 | default y | |
152 | ||
1da177e4 LT |
153 | config GENERIC_CALIBRATE_DELAY |
154 | bool | |
155 | default y | |
156 | ||
a08b6b79 Z |
157 | config ARCH_MAY_HAVE_PC_FDC |
158 | bool | |
159 | ||
5ac6da66 CL |
160 | config ZONE_DMA |
161 | bool | |
5ac6da66 | 162 | |
ccd7ab7f FT |
163 | config NEED_DMA_MAP_STATE |
164 | def_bool y | |
165 | ||
58af4a24 RH |
166 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
167 | bool | |
168 | ||
1da177e4 LT |
169 | config GENERIC_ISA_DMA |
170 | bool | |
171 | ||
1da177e4 LT |
172 | config FIQ |
173 | bool | |
174 | ||
13a5045d RH |
175 | config NEED_RET_TO_USER |
176 | bool | |
177 | ||
034d2f5a AV |
178 | config ARCH_MTD_XIP |
179 | bool | |
180 | ||
c760fc19 HC |
181 | config VECTORS_BASE |
182 | hex | |
6afd6fae | 183 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
184 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
185 | default 0x00000000 | |
186 | help | |
187 | The base address of exception vectors. | |
188 | ||
dc21af99 | 189 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
190 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
191 | default y | |
b511d75d | 192 | depends on !XIP_KERNEL && MMU |
dc21af99 RK |
193 | depends on !ARCH_REALVIEW || !SPARSEMEM |
194 | help | |
111e9a5c RK |
195 | Patch phys-to-virt and virt-to-phys translation functions at |
196 | boot and module load time according to the position of the | |
197 | kernel in system memory. | |
dc21af99 | 198 | |
111e9a5c | 199 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 200 | of physical memory is at a 16MB boundary. |
dc21af99 | 201 | |
c1becedc RK |
202 | Only disable this option if you know that you do not require |
203 | this feature (eg, building a kernel for a single machine) and | |
204 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 205 | |
c334bc15 RH |
206 | config NEED_MACH_IO_H |
207 | bool | |
208 | help | |
209 | Select this when mach/io.h is required to provide special | |
210 | definitions for this platform. The need for mach/io.h should | |
211 | be avoided when possible. | |
212 | ||
0cdc8b92 | 213 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
214 | bool |
215 | help | |
0cdc8b92 NP |
216 | Select this when mach/memory.h is required to provide special |
217 | definitions for this platform. The need for mach/memory.h should | |
218 | be avoided when possible. | |
dc21af99 | 219 | |
1b9f95f8 | 220 | config PHYS_OFFSET |
974c0724 | 221 | hex "Physical address of main memory" if MMU |
0cdc8b92 | 222 | depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H |
974c0724 | 223 | default DRAM_BASE if !MMU |
111e9a5c | 224 | help |
1b9f95f8 NP |
225 | Please provide the physical address corresponding to the |
226 | location of main memory in your system. | |
cada3c08 | 227 | |
87e040b6 SG |
228 | config GENERIC_BUG |
229 | def_bool y | |
230 | depends on BUG | |
231 | ||
1da177e4 LT |
232 | source "init/Kconfig" |
233 | ||
dc52ddc0 MH |
234 | source "kernel/Kconfig.freezer" |
235 | ||
1da177e4 LT |
236 | menu "System Type" |
237 | ||
3c427975 HC |
238 | config MMU |
239 | bool "MMU-based Paged Memory Management Support" | |
240 | default y | |
241 | help | |
242 | Select if you want MMU-based virtualised addressing space | |
243 | support by paged memory management. If unsure, say 'Y'. | |
244 | ||
ccf50e23 RK |
245 | # |
246 | # The "ARM system type" choice list is ordered alphabetically by option | |
247 | # text. Please add new entries in the option alphabetic order. | |
248 | # | |
1da177e4 LT |
249 | choice |
250 | prompt "ARM system type" | |
6a0e2430 | 251 | default ARCH_VERSATILE |
1da177e4 | 252 | |
4af6fee1 DS |
253 | config ARCH_INTEGRATOR |
254 | bool "ARM Ltd. Integrator family" | |
255 | select ARM_AMBA | |
89c52ed4 | 256 | select ARCH_HAS_CPUFREQ |
6d803ba7 | 257 | select CLKDEV_LOOKUP |
aa3831cf | 258 | select HAVE_MACH_CLKDEV |
9904f793 | 259 | select HAVE_TCM |
c5a0adb5 | 260 | select ICST |
13edd86d | 261 | select GENERIC_CLOCKEVENTS |
f4b8b319 | 262 | select PLAT_VERSATILE |
c41b16f8 | 263 | select PLAT_VERSATILE_FPGA_IRQ |
c334bc15 | 264 | select NEED_MACH_IO_H |
0cdc8b92 | 265 | select NEED_MACH_MEMORY_H |
695436e3 | 266 | select SPARSE_IRQ |
3108e6ab | 267 | select MULTI_IRQ_HANDLER |
4af6fee1 DS |
268 | help |
269 | Support for ARM's Integrator platform. | |
270 | ||
271 | config ARCH_REALVIEW | |
272 | bool "ARM Ltd. RealView family" | |
273 | select ARM_AMBA | |
6d803ba7 | 274 | select CLKDEV_LOOKUP |
aa3831cf | 275 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 276 | select ICST |
ae30ceac | 277 | select GENERIC_CLOCKEVENTS |
eb7fffa3 | 278 | select ARCH_WANT_OPTIONAL_GPIOLIB |
f4b8b319 | 279 | select PLAT_VERSATILE |
3cb5ee49 | 280 | select PLAT_VERSATILE_CLCD |
e3887714 | 281 | select ARM_TIMER_SP804 |
b56ba8aa | 282 | select GPIO_PL061 if GPIOLIB |
0cdc8b92 | 283 | select NEED_MACH_MEMORY_H |
4af6fee1 DS |
284 | help |
285 | This enables support for ARM Ltd RealView boards. | |
286 | ||
287 | config ARCH_VERSATILE | |
288 | bool "ARM Ltd. Versatile family" | |
289 | select ARM_AMBA | |
290 | select ARM_VIC | |
6d803ba7 | 291 | select CLKDEV_LOOKUP |
aa3831cf | 292 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 293 | select ICST |
89df1272 | 294 | select GENERIC_CLOCKEVENTS |
bbeddc43 | 295 | select ARCH_WANT_OPTIONAL_GPIOLIB |
9b0f7e39 | 296 | select NEED_MACH_IO_H if PCI |
f4b8b319 | 297 | select PLAT_VERSATILE |
3414ba8c | 298 | select PLAT_VERSATILE_CLCD |
c41b16f8 | 299 | select PLAT_VERSATILE_FPGA_IRQ |
e3887714 | 300 | select ARM_TIMER_SP804 |
4af6fee1 DS |
301 | help |
302 | This enables support for ARM Ltd Versatile board. | |
303 | ||
ceade897 RK |
304 | config ARCH_VEXPRESS |
305 | bool "ARM Ltd. Versatile Express family" | |
306 | select ARCH_WANT_OPTIONAL_GPIOLIB | |
307 | select ARM_AMBA | |
308 | select ARM_TIMER_SP804 | |
6d803ba7 | 309 | select CLKDEV_LOOKUP |
aa3831cf | 310 | select HAVE_MACH_CLKDEV |
ceade897 | 311 | select GENERIC_CLOCKEVENTS |
ceade897 | 312 | select HAVE_CLK |
95c34f83 | 313 | select HAVE_PATA_PLATFORM |
ceade897 | 314 | select ICST |
ba81f502 | 315 | select NO_IOPORT |
ceade897 | 316 | select PLAT_VERSATILE |
0fb44b91 | 317 | select PLAT_VERSATILE_CLCD |
ceade897 RK |
318 | help |
319 | This enables support for the ARM Ltd Versatile Express boards. | |
320 | ||
8fc5ffa0 AV |
321 | config ARCH_AT91 |
322 | bool "Atmel AT91" | |
f373e8c0 | 323 | select ARCH_REQUIRE_GPIOLIB |
93686ae8 | 324 | select HAVE_CLK |
bd602995 | 325 | select CLKDEV_LOOKUP |
e261501d | 326 | select IRQ_DOMAIN |
1ac02d79 | 327 | select NEED_MACH_IO_H if PCCARD |
4af6fee1 | 328 | help |
929e994f NF |
329 | This enables support for systems based on Atmel |
330 | AT91RM9200 and AT91SAM9* processors. | |
4af6fee1 | 331 | |
ccf50e23 RK |
332 | config ARCH_BCMRING |
333 | bool "Broadcom BCMRING" | |
334 | depends on MMU | |
335 | select CPU_V6 | |
336 | select ARM_AMBA | |
82d63734 | 337 | select ARM_TIMER_SP804 |
6d803ba7 | 338 | select CLKDEV_LOOKUP |
ccf50e23 RK |
339 | select GENERIC_CLOCKEVENTS |
340 | select ARCH_WANT_OPTIONAL_GPIOLIB | |
341 | help | |
342 | Support for Broadcom's BCMRing platform. | |
343 | ||
220e6cf7 RH |
344 | config ARCH_HIGHBANK |
345 | bool "Calxeda Highbank-based" | |
346 | select ARCH_WANT_OPTIONAL_GPIOLIB | |
347 | select ARM_AMBA | |
348 | select ARM_GIC | |
349 | select ARM_TIMER_SP804 | |
22d80379 | 350 | select CACHE_L2X0 |
220e6cf7 RH |
351 | select CLKDEV_LOOKUP |
352 | select CPU_V7 | |
353 | select GENERIC_CLOCKEVENTS | |
354 | select HAVE_ARM_SCU | |
3b55658a | 355 | select HAVE_SMP |
fdfa64a4 | 356 | select SPARSE_IRQ |
220e6cf7 RH |
357 | select USE_OF |
358 | help | |
359 | Support for the Calxeda Highbank SoC based boards. | |
360 | ||
1da177e4 | 361 | config ARCH_CLPS711X |
0e2fce59 | 362 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" |
c750815e | 363 | select CPU_ARM720T |
5cfc8ee0 | 364 | select ARCH_USES_GETTIMEOFFSET |
0cdc8b92 | 365 | select NEED_MACH_MEMORY_H |
f999b8bd | 366 | help |
0e2fce59 | 367 | Support for Cirrus Logic 711x/721x/731x based boards. |
1da177e4 | 368 | |
d94f944e AV |
369 | config ARCH_CNS3XXX |
370 | bool "Cavium Networks CNS3XXX family" | |
00d2711d | 371 | select CPU_V6K |
d94f944e AV |
372 | select GENERIC_CLOCKEVENTS |
373 | select ARM_GIC | |
ce5ea9f3 | 374 | select MIGHT_HAVE_CACHE_L2X0 |
0b05da72 | 375 | select MIGHT_HAVE_PCI |
5f32f7a0 | 376 | select PCI_DOMAINS if PCI |
d94f944e AV |
377 | help |
378 | Support for Cavium Networks CNS3XXX platform. | |
379 | ||
788c9700 RK |
380 | config ARCH_GEMINI |
381 | bool "Cortina Systems Gemini" | |
382 | select CPU_FA526 | |
788c9700 | 383 | select ARCH_REQUIRE_GPIOLIB |
5cfc8ee0 | 384 | select ARCH_USES_GETTIMEOFFSET |
788c9700 RK |
385 | help |
386 | Support for the Cortina Systems Gemini family SoCs | |
387 | ||
3a6cb8ce AB |
388 | config ARCH_PRIMA2 |
389 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" | |
390 | select CPU_V7 | |
3a6cb8ce AB |
391 | select NO_IOPORT |
392 | select GENERIC_CLOCKEVENTS | |
393 | select CLKDEV_LOOKUP | |
394 | select GENERIC_IRQ_CHIP | |
ce5ea9f3 | 395 | select MIGHT_HAVE_CACHE_L2X0 |
cbd8d842 BS |
396 | select PINCTRL |
397 | select PINCTRL_SIRF | |
3a6cb8ce AB |
398 | select USE_OF |
399 | select ZONE_DMA | |
400 | help | |
401 | Support for CSR SiRFSoC ARM Cortex A9 Platform | |
402 | ||
1da177e4 LT |
403 | config ARCH_EBSA110 |
404 | bool "EBSA-110" | |
c750815e | 405 | select CPU_SA110 |
f7e68bbf | 406 | select ISA |
c5eb2a2b | 407 | select NO_IOPORT |
5cfc8ee0 | 408 | select ARCH_USES_GETTIMEOFFSET |
c334bc15 | 409 | select NEED_MACH_IO_H |
0cdc8b92 | 410 | select NEED_MACH_MEMORY_H |
1da177e4 LT |
411 | help |
412 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 413 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
414 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
415 | parallel port. | |
416 | ||
e7736d47 LB |
417 | config ARCH_EP93XX |
418 | bool "EP93xx-based" | |
c750815e | 419 | select CPU_ARM920T |
e7736d47 LB |
420 | select ARM_AMBA |
421 | select ARM_VIC | |
6d803ba7 | 422 | select CLKDEV_LOOKUP |
7444a72e | 423 | select ARCH_REQUIRE_GPIOLIB |
eb33575c | 424 | select ARCH_HAS_HOLES_MEMORYMODEL |
5cfc8ee0 | 425 | select ARCH_USES_GETTIMEOFFSET |
5725aeae | 426 | select NEED_MACH_MEMORY_H |
e7736d47 LB |
427 | help |
428 | This enables support for the Cirrus EP93xx series of CPUs. | |
429 | ||
1da177e4 LT |
430 | config ARCH_FOOTBRIDGE |
431 | bool "FootBridge" | |
c750815e | 432 | select CPU_SA110 |
1da177e4 | 433 | select FOOTBRIDGE |
4e8d7637 | 434 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 435 | select HAVE_IDE |
c334bc15 | 436 | select NEED_MACH_IO_H |
0cdc8b92 | 437 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
438 | help |
439 | Support for systems based on the DC21285 companion chip | |
440 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 441 | |
788c9700 RK |
442 | config ARCH_MXC |
443 | bool "Freescale MXC/iMX-based" | |
788c9700 | 444 | select GENERIC_CLOCKEVENTS |
788c9700 | 445 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 446 | select CLKDEV_LOOKUP |
234b6ced | 447 | select CLKSRC_MMIO |
8b6c44f1 | 448 | select GENERIC_IRQ_CHIP |
ffa2ea3f | 449 | select MULTI_IRQ_HANDLER |
788c9700 RK |
450 | help |
451 | Support for Freescale MXC/iMX-based family of processors | |
452 | ||
1d3f33d5 SG |
453 | config ARCH_MXS |
454 | bool "Freescale MXS-based" | |
455 | select GENERIC_CLOCKEVENTS | |
456 | select ARCH_REQUIRE_GPIOLIB | |
b9214b97 | 457 | select CLKDEV_LOOKUP |
5c61ddcf | 458 | select CLKSRC_MMIO |
2664681f | 459 | select COMMON_CLK |
6abda3e1 | 460 | select HAVE_CLK_PREPARE |
a0f5e363 | 461 | select PINCTRL |
6c4d4efb | 462 | select USE_OF |
1d3f33d5 SG |
463 | help |
464 | Support for Freescale MXS-based family of processors | |
465 | ||
4af6fee1 DS |
466 | config ARCH_NETX |
467 | bool "Hilscher NetX based" | |
234b6ced | 468 | select CLKSRC_MMIO |
c750815e | 469 | select CPU_ARM926T |
4af6fee1 | 470 | select ARM_VIC |
2fcfe6b8 | 471 | select GENERIC_CLOCKEVENTS |
f999b8bd | 472 | help |
4af6fee1 DS |
473 | This enables support for systems based on the Hilscher NetX Soc |
474 | ||
475 | config ARCH_H720X | |
476 | bool "Hynix HMS720x-based" | |
c750815e | 477 | select CPU_ARM720T |
4af6fee1 | 478 | select ISA_DMA_API |
5cfc8ee0 | 479 | select ARCH_USES_GETTIMEOFFSET |
4af6fee1 DS |
480 | help |
481 | This enables support for systems based on the Hynix HMS720x | |
482 | ||
3b938be6 RK |
483 | config ARCH_IOP13XX |
484 | bool "IOP13xx-based" | |
485 | depends on MMU | |
c750815e | 486 | select CPU_XSC3 |
3b938be6 RK |
487 | select PLAT_IOP |
488 | select PCI | |
489 | select ARCH_SUPPORTS_MSI | |
8d5796d2 | 490 | select VMSPLIT_1G |
c334bc15 | 491 | select NEED_MACH_IO_H |
0cdc8b92 | 492 | select NEED_MACH_MEMORY_H |
13a5045d | 493 | select NEED_RET_TO_USER |
3b938be6 RK |
494 | help |
495 | Support for Intel's IOP13XX (XScale) family of processors. | |
496 | ||
3f7e5815 LB |
497 | config ARCH_IOP32X |
498 | bool "IOP32x-based" | |
a4f7e763 | 499 | depends on MMU |
c750815e | 500 | select CPU_XSCALE |
c334bc15 | 501 | select NEED_MACH_IO_H |
13a5045d | 502 | select NEED_RET_TO_USER |
7ae1f7ec | 503 | select PLAT_IOP |
f7e68bbf | 504 | select PCI |
bb2b180c | 505 | select ARCH_REQUIRE_GPIOLIB |
f999b8bd | 506 | help |
3f7e5815 LB |
507 | Support for Intel's 80219 and IOP32X (XScale) family of |
508 | processors. | |
509 | ||
510 | config ARCH_IOP33X | |
511 | bool "IOP33x-based" | |
512 | depends on MMU | |
c750815e | 513 | select CPU_XSCALE |
c334bc15 | 514 | select NEED_MACH_IO_H |
13a5045d | 515 | select NEED_RET_TO_USER |
7ae1f7ec | 516 | select PLAT_IOP |
3f7e5815 | 517 | select PCI |
bb2b180c | 518 | select ARCH_REQUIRE_GPIOLIB |
3f7e5815 LB |
519 | help |
520 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 521 | |
3b938be6 RK |
522 | config ARCH_IXP4XX |
523 | bool "IXP4xx-based" | |
a4f7e763 | 524 | depends on MMU |
58af4a24 | 525 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
234b6ced | 526 | select CLKSRC_MMIO |
c750815e | 527 | select CPU_XSCALE |
9dde0ae3 | 528 | select ARCH_REQUIRE_GPIOLIB |
3b938be6 | 529 | select GENERIC_CLOCKEVENTS |
0b05da72 | 530 | select MIGHT_HAVE_PCI |
c334bc15 | 531 | select NEED_MACH_IO_H |
485bdde7 | 532 | select DMABOUNCE if PCI |
c4713074 | 533 | help |
3b938be6 | 534 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 535 | |
edabd38e SB |
536 | config ARCH_DOVE |
537 | bool "Marvell Dove" | |
7b769bb3 | 538 | select CPU_V7 |
edabd38e | 539 | select PCI |
edabd38e | 540 | select ARCH_REQUIRE_GPIOLIB |
edabd38e | 541 | select GENERIC_CLOCKEVENTS |
c334bc15 | 542 | select NEED_MACH_IO_H |
edabd38e SB |
543 | select PLAT_ORION |
544 | help | |
545 | Support for the Marvell Dove SoC 88AP510 | |
546 | ||
651c74c7 SB |
547 | config ARCH_KIRKWOOD |
548 | bool "Marvell Kirkwood" | |
c750815e | 549 | select CPU_FEROCEON |
651c74c7 | 550 | select PCI |
a8865655 | 551 | select ARCH_REQUIRE_GPIOLIB |
651c74c7 | 552 | select GENERIC_CLOCKEVENTS |
c334bc15 | 553 | select NEED_MACH_IO_H |
651c74c7 SB |
554 | select PLAT_ORION |
555 | help | |
556 | Support for the following Marvell Kirkwood series SoCs: | |
557 | 88F6180, 88F6192 and 88F6281. | |
558 | ||
40805949 KW |
559 | config ARCH_LPC32XX |
560 | bool "NXP LPC32XX" | |
234b6ced | 561 | select CLKSRC_MMIO |
40805949 KW |
562 | select CPU_ARM926T |
563 | select ARCH_REQUIRE_GPIOLIB | |
564 | select HAVE_IDE | |
565 | select ARM_AMBA | |
566 | select USB_ARCH_HAS_OHCI | |
6d803ba7 | 567 | select CLKDEV_LOOKUP |
40805949 | 568 | select GENERIC_CLOCKEVENTS |
f5c42271 | 569 | select USE_OF |
40805949 KW |
570 | help |
571 | Support for the NXP LPC32XX family of processors | |
572 | ||
794d15b2 SS |
573 | config ARCH_MV78XX0 |
574 | bool "Marvell MV78xx0" | |
c750815e | 575 | select CPU_FEROCEON |
794d15b2 | 576 | select PCI |
a8865655 | 577 | select ARCH_REQUIRE_GPIOLIB |
794d15b2 | 578 | select GENERIC_CLOCKEVENTS |
c334bc15 | 579 | select NEED_MACH_IO_H |
794d15b2 SS |
580 | select PLAT_ORION |
581 | help | |
582 | Support for the following Marvell MV78xx0 series SoCs: | |
583 | MV781x0, MV782x0. | |
584 | ||
9dd0b194 | 585 | config ARCH_ORION5X |
585cf175 TP |
586 | bool "Marvell Orion" |
587 | depends on MMU | |
c750815e | 588 | select CPU_FEROCEON |
038ee083 | 589 | select PCI |
a8865655 | 590 | select ARCH_REQUIRE_GPIOLIB |
51cbff1d | 591 | select GENERIC_CLOCKEVENTS |
b5e12229 | 592 | select NEED_MACH_IO_H |
69b02f6a | 593 | select PLAT_ORION |
585cf175 | 594 | help |
9dd0b194 | 595 | Support for the following Marvell Orion 5x series SoCs: |
d2b2a6bb | 596 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
d323ade1 | 597 | Orion-2 (5281), Orion-1-90 (6183). |
585cf175 | 598 | |
788c9700 | 599 | config ARCH_MMP |
2f7e8fae | 600 | bool "Marvell PXA168/910/MMP2" |
788c9700 | 601 | depends on MMU |
788c9700 | 602 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 603 | select CLKDEV_LOOKUP |
788c9700 | 604 | select GENERIC_CLOCKEVENTS |
157d2644 | 605 | select GPIO_PXA |
c24b3114 | 606 | select IRQ_DOMAIN |
788c9700 | 607 | select PLAT_PXA |
0bd86961 | 608 | select SPARSE_IRQ |
3c7241bd | 609 | select GENERIC_ALLOCATOR |
788c9700 | 610 | help |
2f7e8fae | 611 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. |
788c9700 RK |
612 | |
613 | config ARCH_KS8695 | |
614 | bool "Micrel/Kendin KS8695" | |
615 | select CPU_ARM922T | |
98830bc9 | 616 | select ARCH_REQUIRE_GPIOLIB |
5cfc8ee0 | 617 | select ARCH_USES_GETTIMEOFFSET |
0cdc8b92 | 618 | select NEED_MACH_MEMORY_H |
788c9700 RK |
619 | help |
620 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
621 | System-on-Chip devices. | |
622 | ||
788c9700 RK |
623 | config ARCH_W90X900 |
624 | bool "Nuvoton W90X900 CPU" | |
625 | select CPU_ARM926T | |
c52d3d68 | 626 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 627 | select CLKDEV_LOOKUP |
6fa5d5f7 | 628 | select CLKSRC_MMIO |
58b5369e | 629 | select GENERIC_CLOCKEVENTS |
788c9700 | 630 | help |
a8bc4ead | 631 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
632 | At present, the w90x900 has been renamed nuc900, regarding | |
633 | the ARM series product line, you can login the following | |
634 | link address to know more. | |
635 | ||
636 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
637 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 638 | |
c5f80065 EG |
639 | config ARCH_TEGRA |
640 | bool "NVIDIA Tegra" | |
4073723a | 641 | select CLKDEV_LOOKUP |
234b6ced | 642 | select CLKSRC_MMIO |
c5f80065 EG |
643 | select GENERIC_CLOCKEVENTS |
644 | select GENERIC_GPIO | |
645 | select HAVE_CLK | |
3b55658a | 646 | select HAVE_SMP |
ce5ea9f3 | 647 | select MIGHT_HAVE_CACHE_L2X0 |
c334bc15 | 648 | select NEED_MACH_IO_H if PCI |
7056d423 | 649 | select ARCH_HAS_CPUFREQ |
c5f80065 EG |
650 | help |
651 | This enables support for NVIDIA Tegra based systems (Tegra APX, | |
652 | Tegra 6xx and Tegra 2 series). | |
653 | ||
af75655c JI |
654 | config ARCH_PICOXCELL |
655 | bool "Picochip picoXcell" | |
656 | select ARCH_REQUIRE_GPIOLIB | |
657 | select ARM_PATCH_PHYS_VIRT | |
658 | select ARM_VIC | |
659 | select CPU_V6K | |
660 | select DW_APB_TIMER | |
661 | select GENERIC_CLOCKEVENTS | |
662 | select GENERIC_GPIO | |
af75655c JI |
663 | select HAVE_TCM |
664 | select NO_IOPORT | |
98e27a5c | 665 | select SPARSE_IRQ |
af75655c JI |
666 | select USE_OF |
667 | help | |
668 | This enables support for systems based on the Picochip picoXcell | |
669 | family of Femtocell devices. The picoxcell support requires device tree | |
670 | for all boards. | |
671 | ||
4af6fee1 DS |
672 | config ARCH_PNX4008 |
673 | bool "Philips Nexperia PNX4008 Mobile" | |
c750815e | 674 | select CPU_ARM926T |
6d803ba7 | 675 | select CLKDEV_LOOKUP |
5cfc8ee0 | 676 | select ARCH_USES_GETTIMEOFFSET |
4af6fee1 DS |
677 | help |
678 | This enables support for Philips PNX4008 mobile platform. | |
679 | ||
1da177e4 | 680 | config ARCH_PXA |
2c8086a5 | 681 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 682 | depends on MMU |
034d2f5a | 683 | select ARCH_MTD_XIP |
89c52ed4 | 684 | select ARCH_HAS_CPUFREQ |
6d803ba7 | 685 | select CLKDEV_LOOKUP |
234b6ced | 686 | select CLKSRC_MMIO |
7444a72e | 687 | select ARCH_REQUIRE_GPIOLIB |
981d0f39 | 688 | select GENERIC_CLOCKEVENTS |
157d2644 | 689 | select GPIO_PXA |
bd5ce433 | 690 | select PLAT_PXA |
6ac6b817 | 691 | select SPARSE_IRQ |
4e234cc0 | 692 | select AUTO_ZRELADDR |
8a97ae2f | 693 | select MULTI_IRQ_HANDLER |
15e0d9e3 | 694 | select ARM_CPU_SUSPEND if PM |
d0ee9f40 | 695 | select HAVE_IDE |
f999b8bd | 696 | help |
2c8086a5 | 697 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 | 698 | |
788c9700 RK |
699 | config ARCH_MSM |
700 | bool "Qualcomm MSM" | |
4b536b8d | 701 | select HAVE_CLK |
49cbe786 | 702 | select GENERIC_CLOCKEVENTS |
923a081c | 703 | select ARCH_REQUIRE_GPIOLIB |
bd32344a | 704 | select CLKDEV_LOOKUP |
49cbe786 | 705 | help |
4b53eb4f DW |
706 | Support for Qualcomm MSM/QSD based systems. This runs on the |
707 | apps processor of the MSM/QSD and depends on a shared memory | |
708 | interface to the modem processor which runs the baseband | |
709 | stack and controls some vital subsystems | |
710 | (clock and power control, etc). | |
49cbe786 | 711 | |
c793c1b0 | 712 | config ARCH_SHMOBILE |
6d72ad35 PM |
713 | bool "Renesas SH-Mobile / R-Mobile" |
714 | select HAVE_CLK | |
5e93c6b4 | 715 | select CLKDEV_LOOKUP |
aa3831cf | 716 | select HAVE_MACH_CLKDEV |
3b55658a | 717 | select HAVE_SMP |
6d72ad35 | 718 | select GENERIC_CLOCKEVENTS |
ce5ea9f3 | 719 | select MIGHT_HAVE_CACHE_L2X0 |
6d72ad35 PM |
720 | select NO_IOPORT |
721 | select SPARSE_IRQ | |
60f1435c | 722 | select MULTI_IRQ_HANDLER |
e3e01091 | 723 | select PM_GENERIC_DOMAINS if PM |
0cdc8b92 | 724 | select NEED_MACH_MEMORY_H |
c793c1b0 | 725 | help |
6d72ad35 | 726 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms. |
c793c1b0 | 727 | |
1da177e4 LT |
728 | config ARCH_RPC |
729 | bool "RiscPC" | |
730 | select ARCH_ACORN | |
731 | select FIQ | |
a08b6b79 | 732 | select ARCH_MAY_HAVE_PC_FDC |
341eb781 | 733 | select HAVE_PATA_PLATFORM |
065909b9 | 734 | select ISA_DMA_API |
5ea81769 | 735 | select NO_IOPORT |
07f841b7 | 736 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 737 | select ARCH_USES_GETTIMEOFFSET |
d0ee9f40 | 738 | select HAVE_IDE |
c334bc15 | 739 | select NEED_MACH_IO_H |
0cdc8b92 | 740 | select NEED_MACH_MEMORY_H |
1da177e4 LT |
741 | help |
742 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
743 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
744 | ||
745 | config ARCH_SA1100 | |
746 | bool "SA1100-based" | |
234b6ced | 747 | select CLKSRC_MMIO |
c750815e | 748 | select CPU_SA1100 |
f7e68bbf | 749 | select ISA |
05944d74 | 750 | select ARCH_SPARSEMEM_ENABLE |
034d2f5a | 751 | select ARCH_MTD_XIP |
89c52ed4 | 752 | select ARCH_HAS_CPUFREQ |
1937f5b9 | 753 | select CPU_FREQ |
3e238be2 | 754 | select GENERIC_CLOCKEVENTS |
4a8f8340 | 755 | select CLKDEV_LOOKUP |
7444a72e | 756 | select ARCH_REQUIRE_GPIOLIB |
d0ee9f40 | 757 | select HAVE_IDE |
0cdc8b92 | 758 | select NEED_MACH_MEMORY_H |
375dec92 | 759 | select SPARSE_IRQ |
f999b8bd MM |
760 | help |
761 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 762 | |
b130d5c2 KK |
763 | config ARCH_S3C24XX |
764 | bool "Samsung S3C24XX SoCs" | |
0a938b97 | 765 | select GENERIC_GPIO |
9d56c02a | 766 | select ARCH_HAS_CPUFREQ |
9483a578 | 767 | select HAVE_CLK |
e83626f2 | 768 | select CLKDEV_LOOKUP |
5cfc8ee0 | 769 | select ARCH_USES_GETTIMEOFFSET |
20676c15 | 770 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 KK |
771 | select HAVE_S3C_RTC if RTC_CLASS |
772 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
c334bc15 | 773 | select NEED_MACH_IO_H |
1da177e4 | 774 | help |
b130d5c2 KK |
775 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
776 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
777 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
778 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 779 | |
a08ab637 BD |
780 | config ARCH_S3C64XX |
781 | bool "Samsung S3C64XX" | |
89f1fa08 | 782 | select PLAT_SAMSUNG |
89f0ce72 | 783 | select CPU_V6 |
89f0ce72 | 784 | select ARM_VIC |
a08ab637 | 785 | select HAVE_CLK |
6700397a | 786 | select HAVE_TCM |
226e85f4 | 787 | select CLKDEV_LOOKUP |
89f0ce72 | 788 | select NO_IOPORT |
5cfc8ee0 | 789 | select ARCH_USES_GETTIMEOFFSET |
89c52ed4 | 790 | select ARCH_HAS_CPUFREQ |
89f0ce72 BD |
791 | select ARCH_REQUIRE_GPIOLIB |
792 | select SAMSUNG_CLKSRC | |
793 | select SAMSUNG_IRQ_VIC_TIMER | |
89f0ce72 | 794 | select S3C_GPIO_TRACK |
89f0ce72 BD |
795 | select S3C_DEV_NAND |
796 | select USB_ARCH_HAS_OHCI | |
797 | select SAMSUNG_GPIOLIB_4BIT | |
20676c15 | 798 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 799 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
a08ab637 BD |
800 | help |
801 | Samsung S3C64XX series based systems | |
802 | ||
49b7a491 KK |
803 | config ARCH_S5P64X0 |
804 | bool "Samsung S5P6440 S5P6450" | |
c4ffccdd KK |
805 | select CPU_V6 |
806 | select GENERIC_GPIO | |
807 | select HAVE_CLK | |
d8b22d25 | 808 | select CLKDEV_LOOKUP |
0665ccc4 | 809 | select CLKSRC_MMIO |
c39d8d55 | 810 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
9e65bbf2 | 811 | select GENERIC_CLOCKEVENTS |
20676c15 | 812 | select HAVE_S3C2410_I2C if I2C |
754961a8 | 813 | select HAVE_S3C_RTC if RTC_CLASS |
c4ffccdd | 814 | help |
49b7a491 KK |
815 | Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, |
816 | SMDK6450. | |
c4ffccdd | 817 | |
acc84707 MS |
818 | config ARCH_S5PC100 |
819 | bool "Samsung S5PC100" | |
5a7652f2 BM |
820 | select GENERIC_GPIO |
821 | select HAVE_CLK | |
29e8eb0f | 822 | select CLKDEV_LOOKUP |
5a7652f2 | 823 | select CPU_V7 |
925c68cd | 824 | select ARCH_USES_GETTIMEOFFSET |
20676c15 | 825 | select HAVE_S3C2410_I2C if I2C |
754961a8 | 826 | select HAVE_S3C_RTC if RTC_CLASS |
c39d8d55 | 827 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
5a7652f2 | 828 | help |
acc84707 | 829 | Samsung S5PC100 series based systems |
5a7652f2 | 830 | |
170f4e42 KK |
831 | config ARCH_S5PV210 |
832 | bool "Samsung S5PV210/S5PC110" | |
833 | select CPU_V7 | |
eecb6a84 | 834 | select ARCH_SPARSEMEM_ENABLE |
0f75a96b | 835 | select ARCH_HAS_HOLES_MEMORYMODEL |
170f4e42 KK |
836 | select GENERIC_GPIO |
837 | select HAVE_CLK | |
b2a9dd46 | 838 | select CLKDEV_LOOKUP |
0665ccc4 | 839 | select CLKSRC_MMIO |
d8144aea | 840 | select ARCH_HAS_CPUFREQ |
9e65bbf2 | 841 | select GENERIC_CLOCKEVENTS |
20676c15 | 842 | select HAVE_S3C2410_I2C if I2C |
754961a8 | 843 | select HAVE_S3C_RTC if RTC_CLASS |
c39d8d55 | 844 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
0cdc8b92 | 845 | select NEED_MACH_MEMORY_H |
170f4e42 KK |
846 | help |
847 | Samsung S5PV210/S5PC110 series based systems | |
848 | ||
83014579 KK |
849 | config ARCH_EXYNOS |
850 | bool "SAMSUNG EXYNOS" | |
cc0e72b8 | 851 | select CPU_V7 |
f567fa6f | 852 | select ARCH_SPARSEMEM_ENABLE |
0f75a96b | 853 | select ARCH_HAS_HOLES_MEMORYMODEL |
cc0e72b8 CY |
854 | select GENERIC_GPIO |
855 | select HAVE_CLK | |
badc4f2d | 856 | select CLKDEV_LOOKUP |
b333fb16 | 857 | select ARCH_HAS_CPUFREQ |
cc0e72b8 | 858 | select GENERIC_CLOCKEVENTS |
754961a8 | 859 | select HAVE_S3C_RTC if RTC_CLASS |
20676c15 | 860 | select HAVE_S3C2410_I2C if I2C |
c39d8d55 | 861 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
0cdc8b92 | 862 | select NEED_MACH_MEMORY_H |
cc0e72b8 | 863 | help |
83014579 | 864 | Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) |
cc0e72b8 | 865 | |
1da177e4 LT |
866 | config ARCH_SHARK |
867 | bool "Shark" | |
c750815e | 868 | select CPU_SA110 |
f7e68bbf RK |
869 | select ISA |
870 | select ISA_DMA | |
3bca103a | 871 | select ZONE_DMA |
f7e68bbf | 872 | select PCI |
5cfc8ee0 | 873 | select ARCH_USES_GETTIMEOFFSET |
0cdc8b92 | 874 | select NEED_MACH_MEMORY_H |
c334bc15 | 875 | select NEED_MACH_IO_H |
f999b8bd MM |
876 | help |
877 | Support for the StrongARM based Digital DNARD machine, also known | |
878 | as "Shark" (<http://www.shark-linux.de/shark.html>). | |
1da177e4 | 879 | |
d98aac75 LW |
880 | config ARCH_U300 |
881 | bool "ST-Ericsson U300 Series" | |
882 | depends on MMU | |
234b6ced | 883 | select CLKSRC_MMIO |
d98aac75 | 884 | select CPU_ARM926T |
bc581770 | 885 | select HAVE_TCM |
d98aac75 | 886 | select ARM_AMBA |
5485c1e0 | 887 | select ARM_PATCH_PHYS_VIRT |
d98aac75 | 888 | select ARM_VIC |
d98aac75 | 889 | select GENERIC_CLOCKEVENTS |
6d803ba7 | 890 | select CLKDEV_LOOKUP |
50667d63 | 891 | select COMMON_CLK |
d98aac75 | 892 | select GENERIC_GPIO |
cc890cd7 | 893 | select ARCH_REQUIRE_GPIOLIB |
d98aac75 LW |
894 | help |
895 | Support for ST-Ericsson U300 series mobile platforms. | |
896 | ||
ccf50e23 RK |
897 | config ARCH_U8500 |
898 | bool "ST-Ericsson U8500 Series" | |
67ae14fc | 899 | depends on MMU |
ccf50e23 RK |
900 | select CPU_V7 |
901 | select ARM_AMBA | |
ccf50e23 | 902 | select GENERIC_CLOCKEVENTS |
6d803ba7 | 903 | select CLKDEV_LOOKUP |
94bdc0e2 | 904 | select ARCH_REQUIRE_GPIOLIB |
7c1a70e9 | 905 | select ARCH_HAS_CPUFREQ |
3b55658a | 906 | select HAVE_SMP |
ce5ea9f3 | 907 | select MIGHT_HAVE_CACHE_L2X0 |
ccf50e23 RK |
908 | help |
909 | Support for ST-Ericsson's Ux500 architecture | |
910 | ||
911 | config ARCH_NOMADIK | |
912 | bool "STMicroelectronics Nomadik" | |
913 | select ARM_AMBA | |
914 | select ARM_VIC | |
915 | select CPU_ARM926T | |
6d803ba7 | 916 | select CLKDEV_LOOKUP |
ccf50e23 | 917 | select GENERIC_CLOCKEVENTS |
0fa7be40 | 918 | select PINCTRL |
ce5ea9f3 | 919 | select MIGHT_HAVE_CACHE_L2X0 |
ccf50e23 RK |
920 | select ARCH_REQUIRE_GPIOLIB |
921 | help | |
922 | Support for the Nomadik platform by ST-Ericsson | |
923 | ||
7c6337e2 KH |
924 | config ARCH_DAVINCI |
925 | bool "TI DaVinci" | |
7c6337e2 | 926 | select GENERIC_CLOCKEVENTS |
dce1115b | 927 | select ARCH_REQUIRE_GPIOLIB |
3bca103a | 928 | select ZONE_DMA |
9232fcc9 | 929 | select HAVE_IDE |
6d803ba7 | 930 | select CLKDEV_LOOKUP |
20e9969b | 931 | select GENERIC_ALLOCATOR |
dc7ad3b3 | 932 | select GENERIC_IRQ_CHIP |
ae88e05a | 933 | select ARCH_HAS_HOLES_MEMORYMODEL |
7c6337e2 KH |
934 | help |
935 | Support for TI's DaVinci platform. | |
936 | ||
3b938be6 RK |
937 | config ARCH_OMAP |
938 | bool "TI OMAP" | |
9483a578 | 939 | select HAVE_CLK |
7444a72e | 940 | select ARCH_REQUIRE_GPIOLIB |
89c52ed4 | 941 | select ARCH_HAS_CPUFREQ |
354a183f | 942 | select CLKSRC_MMIO |
06cad098 | 943 | select GENERIC_CLOCKEVENTS |
9af915da | 944 | select ARCH_HAS_HOLES_MEMORYMODEL |
3b938be6 | 945 | help |
6e457bb0 | 946 | Support for TI's OMAP platform (OMAP1/2/3/4). |
3b938be6 | 947 | |
cee37e50 | 948 | config PLAT_SPEAR |
949 | bool "ST SPEAr" | |
950 | select ARM_AMBA | |
951 | select ARCH_REQUIRE_GPIOLIB | |
6d803ba7 | 952 | select CLKDEV_LOOKUP |
5df33a62 | 953 | select COMMON_CLK |
d6e15d78 | 954 | select CLKSRC_MMIO |
cee37e50 | 955 | select GENERIC_CLOCKEVENTS |
cee37e50 | 956 | select HAVE_CLK |
957 | help | |
958 | Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). | |
959 | ||
21f47fbc AC |
960 | config ARCH_VT8500 |
961 | bool "VIA/WonderMedia 85xx" | |
962 | select CPU_ARM926T | |
963 | select GENERIC_GPIO | |
964 | select ARCH_HAS_CPUFREQ | |
965 | select GENERIC_CLOCKEVENTS | |
966 | select ARCH_REQUIRE_GPIOLIB | |
967 | select HAVE_PWM | |
968 | help | |
969 | Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. | |
02c981c0 | 970 | |
b85a3ef4 JL |
971 | config ARCH_ZYNQ |
972 | bool "Xilinx Zynq ARM Cortex A9 Platform" | |
02c981c0 | 973 | select CPU_V7 |
02c981c0 BD |
974 | select GENERIC_CLOCKEVENTS |
975 | select CLKDEV_LOOKUP | |
b85a3ef4 JL |
976 | select ARM_GIC |
977 | select ARM_AMBA | |
978 | select ICST | |
ce5ea9f3 | 979 | select MIGHT_HAVE_CACHE_L2X0 |
02c981c0 | 980 | select USE_OF |
02c981c0 | 981 | help |
b85a3ef4 | 982 | Support for Xilinx Zynq ARM Cortex A9 Platform |
1da177e4 LT |
983 | endchoice |
984 | ||
ccf50e23 RK |
985 | # |
986 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
987 | # Kconfigs may be included either alphabetically (according to the | |
988 | # plat- suffix) or along side the corresponding mach-* source. | |
989 | # | |
95b8f20f RK |
990 | source "arch/arm/mach-at91/Kconfig" |
991 | ||
992 | source "arch/arm/mach-bcmring/Kconfig" | |
993 | ||
1da177e4 LT |
994 | source "arch/arm/mach-clps711x/Kconfig" |
995 | ||
d94f944e AV |
996 | source "arch/arm/mach-cns3xxx/Kconfig" |
997 | ||
95b8f20f RK |
998 | source "arch/arm/mach-davinci/Kconfig" |
999 | ||
1000 | source "arch/arm/mach-dove/Kconfig" | |
1001 | ||
e7736d47 LB |
1002 | source "arch/arm/mach-ep93xx/Kconfig" |
1003 | ||
1da177e4 LT |
1004 | source "arch/arm/mach-footbridge/Kconfig" |
1005 | ||
59d3a193 PZ |
1006 | source "arch/arm/mach-gemini/Kconfig" |
1007 | ||
95b8f20f RK |
1008 | source "arch/arm/mach-h720x/Kconfig" |
1009 | ||
1da177e4 LT |
1010 | source "arch/arm/mach-integrator/Kconfig" |
1011 | ||
3f7e5815 LB |
1012 | source "arch/arm/mach-iop32x/Kconfig" |
1013 | ||
1014 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 1015 | |
285f5fa7 DW |
1016 | source "arch/arm/mach-iop13xx/Kconfig" |
1017 | ||
1da177e4 LT |
1018 | source "arch/arm/mach-ixp4xx/Kconfig" |
1019 | ||
95b8f20f RK |
1020 | source "arch/arm/mach-kirkwood/Kconfig" |
1021 | ||
1022 | source "arch/arm/mach-ks8695/Kconfig" | |
1023 | ||
40805949 KW |
1024 | source "arch/arm/mach-lpc32xx/Kconfig" |
1025 | ||
95b8f20f RK |
1026 | source "arch/arm/mach-msm/Kconfig" |
1027 | ||
794d15b2 SS |
1028 | source "arch/arm/mach-mv78xx0/Kconfig" |
1029 | ||
95b8f20f | 1030 | source "arch/arm/plat-mxc/Kconfig" |
1da177e4 | 1031 | |
1d3f33d5 SG |
1032 | source "arch/arm/mach-mxs/Kconfig" |
1033 | ||
95b8f20f | 1034 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 1035 | |
95b8f20f RK |
1036 | source "arch/arm/mach-nomadik/Kconfig" |
1037 | source "arch/arm/plat-nomadik/Kconfig" | |
1038 | ||
d48af15e TL |
1039 | source "arch/arm/plat-omap/Kconfig" |
1040 | ||
1041 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 1042 | |
1dbae815 TL |
1043 | source "arch/arm/mach-omap2/Kconfig" |
1044 | ||
9dd0b194 | 1045 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 1046 | |
95b8f20f RK |
1047 | source "arch/arm/mach-pxa/Kconfig" |
1048 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 1049 | |
95b8f20f RK |
1050 | source "arch/arm/mach-mmp/Kconfig" |
1051 | ||
1052 | source "arch/arm/mach-realview/Kconfig" | |
1053 | ||
1054 | source "arch/arm/mach-sa1100/Kconfig" | |
edabd38e | 1055 | |
cf383678 | 1056 | source "arch/arm/plat-samsung/Kconfig" |
a21765a7 BD |
1057 | source "arch/arm/plat-s3c24xx/Kconfig" |
1058 | ||
cee37e50 | 1059 | source "arch/arm/plat-spear/Kconfig" |
a21765a7 | 1060 | |
85fd6d63 | 1061 | source "arch/arm/mach-s3c24xx/Kconfig" |
b130d5c2 | 1062 | if ARCH_S3C24XX |
a21765a7 BD |
1063 | source "arch/arm/mach-s3c2412/Kconfig" |
1064 | source "arch/arm/mach-s3c2440/Kconfig" | |
a21765a7 | 1065 | endif |
1da177e4 | 1066 | |
a08ab637 | 1067 | if ARCH_S3C64XX |
431107ea | 1068 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 BD |
1069 | endif |
1070 | ||
49b7a491 | 1071 | source "arch/arm/mach-s5p64x0/Kconfig" |
c4ffccdd | 1072 | |
5a7652f2 | 1073 | source "arch/arm/mach-s5pc100/Kconfig" |
5a7652f2 | 1074 | |
170f4e42 KK |
1075 | source "arch/arm/mach-s5pv210/Kconfig" |
1076 | ||
83014579 | 1077 | source "arch/arm/mach-exynos/Kconfig" |
cc0e72b8 | 1078 | |
882d01f9 | 1079 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 1080 | |
c5f80065 EG |
1081 | source "arch/arm/mach-tegra/Kconfig" |
1082 | ||
95b8f20f | 1083 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 1084 | |
95b8f20f | 1085 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
1086 | |
1087 | source "arch/arm/mach-versatile/Kconfig" | |
1088 | ||
ceade897 | 1089 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 1090 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 1091 | |
21f47fbc AC |
1092 | source "arch/arm/mach-vt8500/Kconfig" |
1093 | ||
7ec80ddf | 1094 | source "arch/arm/mach-w90x900/Kconfig" |
1095 | ||
1da177e4 LT |
1096 | # Definitions to make life easier |
1097 | config ARCH_ACORN | |
1098 | bool | |
1099 | ||
7ae1f7ec LB |
1100 | config PLAT_IOP |
1101 | bool | |
469d3044 | 1102 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 1103 | |
69b02f6a LB |
1104 | config PLAT_ORION |
1105 | bool | |
bfe45e0b | 1106 | select CLKSRC_MMIO |
dc7ad3b3 | 1107 | select GENERIC_IRQ_CHIP |
2f129bf4 | 1108 | select COMMON_CLK |
69b02f6a | 1109 | |
bd5ce433 EM |
1110 | config PLAT_PXA |
1111 | bool | |
1112 | ||
f4b8b319 RK |
1113 | config PLAT_VERSATILE |
1114 | bool | |
1115 | ||
e3887714 RK |
1116 | config ARM_TIMER_SP804 |
1117 | bool | |
bfe45e0b | 1118 | select CLKSRC_MMIO |
a7bf6162 | 1119 | select HAVE_SCHED_CLOCK |
e3887714 | 1120 | |
1da177e4 LT |
1121 | source arch/arm/mm/Kconfig |
1122 | ||
958cab0f RK |
1123 | config ARM_NR_BANKS |
1124 | int | |
1125 | default 16 if ARCH_EP93XX | |
1126 | default 8 | |
1127 | ||
afe4b25e LB |
1128 | config IWMMXT |
1129 | bool "Enable iWMMXt support" | |
ef6c8445 HZ |
1130 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 |
1131 | default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP | |
afe4b25e LB |
1132 | help |
1133 | Enable support for iWMMXt context switching at run time if | |
1134 | running on a CPU that supports it. | |
1135 | ||
1da177e4 LT |
1136 | config XSCALE_PMU |
1137 | bool | |
bfc994b5 | 1138 | depends on CPU_XSCALE |
1da177e4 LT |
1139 | default y |
1140 | ||
0f4f0672 | 1141 | config CPU_HAS_PMU |
e399b1a4 | 1142 | depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ |
8954bb0d | 1143 | (!ARCH_OMAP3 || OMAP3_EMU) |
0f4f0672 JI |
1144 | default y |
1145 | bool | |
1146 | ||
52108641 | 1147 | config MULTI_IRQ_HANDLER |
1148 | bool | |
1149 | help | |
1150 | Allow each machine to specify it's own IRQ handler at run time. | |
1151 | ||
3b93e7b0 HC |
1152 | if !MMU |
1153 | source "arch/arm/Kconfig-nommu" | |
1154 | endif | |
1155 | ||
f0c4b8d6 WD |
1156 | config ARM_ERRATA_326103 |
1157 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
1158 | depends on CPU_V6 | |
1159 | help | |
1160 | Executing a SWP instruction to read-only memory does not set bit 11 | |
1161 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
1162 | treat the access as a read, preventing a COW from occurring and | |
1163 | causing the faulting task to livelock. | |
1164 | ||
9cba3ccc CM |
1165 | config ARM_ERRATA_411920 |
1166 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 1167 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
1168 | help |
1169 | Invalidation of the Instruction Cache operation can | |
1170 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1171 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1172 | recommended workaround. | |
1173 | ||
7ce236fc CM |
1174 | config ARM_ERRATA_430973 |
1175 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1176 | depends on CPU_V7 | |
1177 | help | |
1178 | This option enables the workaround for the 430973 Cortex-A8 | |
1179 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1180 | interworking branch is replaced with another code sequence at the | |
1181 | same virtual address, whether due to self-modifying code or virtual | |
1182 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1183 | stale interworking branch prediction. This results in Cortex-A8 | |
1184 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1185 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1186 | and also flushes the branch target cache at every context switch. | |
1187 | Note that setting specific bits in the ACTLR register may not be | |
1188 | available in non-secure mode. | |
1189 | ||
855c551f CM |
1190 | config ARM_ERRATA_458693 |
1191 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1192 | depends on CPU_V7 | |
1193 | help | |
1194 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1195 | erratum. For very specific sequences of memory operations, it is | |
1196 | possible for a hazard condition intended for a cache line to instead | |
1197 | be incorrectly associated with a different cache line. This false | |
1198 | hazard might then cause a processor deadlock. The workaround enables | |
1199 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1200 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1201 | register may not be available in non-secure mode. | |
1202 | ||
0516e464 CM |
1203 | config ARM_ERRATA_460075 |
1204 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1205 | depends on CPU_V7 | |
1206 | help | |
1207 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1208 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1209 | situation in which recent store transactions to the L2 cache are lost | |
1210 | and overwritten with stale memory contents from external memory. The | |
1211 | workaround disables the write-allocate mode for the L2 cache via the | |
1212 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1213 | may not be available in non-secure mode. | |
1214 | ||
9f05027c WD |
1215 | config ARM_ERRATA_742230 |
1216 | bool "ARM errata: DMB operation may be faulty" | |
1217 | depends on CPU_V7 && SMP | |
1218 | help | |
1219 | This option enables the workaround for the 742230 Cortex-A9 | |
1220 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1221 | between two write operations may not ensure the correct visibility | |
1222 | ordering of the two writes. This workaround sets a specific bit in | |
1223 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1224 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1225 | the two writes. | |
1226 | ||
a672e99b WD |
1227 | config ARM_ERRATA_742231 |
1228 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1229 | depends on CPU_V7 && SMP | |
1230 | help | |
1231 | This option enables the workaround for the 742231 Cortex-A9 | |
1232 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1233 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1234 | accessing some data located in the same cache line, may get corrupted | |
1235 | data due to bad handling of the address hazard when the line gets | |
1236 | replaced from one of the CPUs at the same time as another CPU is | |
1237 | accessing it. This workaround sets specific bits in the diagnostic | |
1238 | register of the Cortex-A9 which reduces the linefill issuing | |
1239 | capabilities of the processor. | |
1240 | ||
9e65582a | 1241 | config PL310_ERRATA_588369 |
fa0ce403 | 1242 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" |
2839e06c | 1243 | depends on CACHE_L2X0 |
9e65582a SS |
1244 | help |
1245 | The PL310 L2 cache controller implements three types of Clean & | |
1246 | Invalidate maintenance operations: by Physical Address | |
1247 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
1248 | They are architecturally defined to behave as the execution of a | |
1249 | clean operation followed immediately by an invalidate operation, | |
1250 | both performing to the same memory location. This functionality | |
1251 | is not correctly implemented in PL310 as clean lines are not | |
2839e06c | 1252 | invalidated as a result of these operations. |
cdf357f1 WD |
1253 | |
1254 | config ARM_ERRATA_720789 | |
1255 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1256 | depends on CPU_V7 |
cdf357f1 WD |
1257 | help |
1258 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1259 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1260 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1261 | As a consequence of this erratum, some TLB entries which should be | |
1262 | invalidated are not, resulting in an incoherency in the system page | |
1263 | tables. The workaround changes the TLB flushing routines to invalidate | |
1264 | entries regardless of the ASID. | |
475d92fc | 1265 | |
1f0090a1 | 1266 | config PL310_ERRATA_727915 |
fa0ce403 | 1267 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" |
1f0090a1 RK |
1268 | depends on CACHE_L2X0 |
1269 | help | |
1270 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
1271 | operation (offset 0x7FC). This operation runs in background so that | |
1272 | PL310 can handle normal accesses while it is in progress. Under very | |
1273 | rare circumstances, due to this erratum, write data can be lost when | |
1274 | PL310 treats a cacheable write transaction during a Clean & | |
1275 | Invalidate by Way operation. | |
1276 | ||
475d92fc WD |
1277 | config ARM_ERRATA_743622 |
1278 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1279 | depends on CPU_V7 | |
1280 | help | |
1281 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1282 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1283 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1284 | corruption. This workaround sets a specific bit in the diagnostic | |
1285 | register of the Cortex-A9 which disables the Store Buffer | |
1286 | optimisation, preventing the defect from occurring. This has no | |
1287 | visible impact on the overall performance or power consumption of the | |
1288 | processor. | |
1289 | ||
9a27c27c WD |
1290 | config ARM_ERRATA_751472 |
1291 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1292 | depends on CPU_V7 |
9a27c27c WD |
1293 | help |
1294 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1295 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1296 | completion of a following broadcasted operation if the second | |
1297 | operation is received by a CPU before the ICIALLUIS has completed, | |
1298 | potentially leading to corrupted entries in the cache or TLB. | |
1299 | ||
fa0ce403 WD |
1300 | config PL310_ERRATA_753970 |
1301 | bool "PL310 errata: cache sync operation may be faulty" | |
885028e4 SK |
1302 | depends on CACHE_PL310 |
1303 | help | |
1304 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
1305 | ||
1306 | Under some condition the effect of cache sync operation on | |
1307 | the store buffer still remains when the operation completes. | |
1308 | This means that the store buffer is always asked to drain and | |
1309 | this prevents it from merging any further writes. The workaround | |
1310 | is to replace the normal offset of cache sync operation (0x730) | |
1311 | by another offset targeting an unmapped PL310 register 0x740. | |
1312 | This has the same effect as the cache sync operation: store buffer | |
1313 | drain and waiting for all buffers empty. | |
1314 | ||
fcbdc5fe WD |
1315 | config ARM_ERRATA_754322 |
1316 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1317 | depends on CPU_V7 | |
1318 | help | |
1319 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1320 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1321 | which starts prior to an ASID switch but completes afterwards. This | |
1322 | can populate the micro-TLB with a stale entry which may be hit with | |
1323 | the new ASID. This workaround places two dsb instructions in the mm | |
1324 | switching code so that no page table walks can cross the ASID switch. | |
1325 | ||
5dab26af WD |
1326 | config ARM_ERRATA_754327 |
1327 | bool "ARM errata: no automatic Store Buffer drain" | |
1328 | depends on CPU_V7 && SMP | |
1329 | help | |
1330 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1331 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1332 | mechanism and therefore a livelock may occur if an external agent | |
1333 | continuously polls a memory location waiting to observe an update. | |
1334 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1335 | written polling loops from denying visibility of updates to memory. | |
1336 | ||
145e10e1 CM |
1337 | config ARM_ERRATA_364296 |
1338 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
1339 | depends on CPU_V6 && !SMP | |
1340 | help | |
1341 | This options enables the workaround for the 364296 ARM1136 | |
1342 | r0p2 erratum (possible cache data corruption with | |
1343 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1344 | the auxiliary control register and the FI bit in the control | |
1345 | register, thus disabling hit-under-miss without putting the | |
1346 | processor into full low interrupt latency mode. ARM11MPCore | |
1347 | is not affected. | |
1348 | ||
f630c1bd WD |
1349 | config ARM_ERRATA_764369 |
1350 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1351 | depends on CPU_V7 && SMP | |
1352 | help | |
1353 | This option enables the workaround for erratum 764369 | |
1354 | affecting Cortex-A9 MPCore with two or more processors (all | |
1355 | current revisions). Under certain timing circumstances, a data | |
1356 | cache line maintenance operation by MVA targeting an Inner | |
1357 | Shareable memory region may fail to proceed up to either the | |
1358 | Point of Coherency or to the Point of Unification of the | |
1359 | system. This workaround adds a DSB instruction before the | |
1360 | relevant cache maintenance functions and sets a specific bit | |
1361 | in the diagnostic control register of the SCU. | |
1362 | ||
11ed0ba1 WD |
1363 | config PL310_ERRATA_769419 |
1364 | bool "PL310 errata: no automatic Store Buffer drain" | |
1365 | depends on CACHE_L2X0 | |
1366 | help | |
1367 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
1368 | not automatically drain. This can cause normal, non-cacheable | |
1369 | writes to be retained when the memory system is idle, leading | |
1370 | to suboptimal I/O performance for drivers using coherent DMA. | |
1371 | This option adds a write barrier to the cpu_idle loop so that, | |
1372 | on systems with an outer cache, the store buffer is drained | |
1373 | explicitly. | |
1374 | ||
1da177e4 LT |
1375 | endmenu |
1376 | ||
1377 | source "arch/arm/common/Kconfig" | |
1378 | ||
1da177e4 LT |
1379 | menu "Bus support" |
1380 | ||
1381 | config ARM_AMBA | |
1382 | bool | |
1383 | ||
1384 | config ISA | |
1385 | bool | |
1da177e4 LT |
1386 | help |
1387 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1388 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1389 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1390 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1391 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1392 | ||
065909b9 | 1393 | # Select ISA DMA controller support |
1da177e4 LT |
1394 | config ISA_DMA |
1395 | bool | |
065909b9 | 1396 | select ISA_DMA_API |
1da177e4 | 1397 | |
065909b9 | 1398 | # Select ISA DMA interface |
5cae841b AV |
1399 | config ISA_DMA_API |
1400 | bool | |
5cae841b | 1401 | |
1da177e4 | 1402 | config PCI |
0b05da72 | 1403 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1404 | help |
1405 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1406 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1407 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1408 | VESA. If you have PCI, say Y, otherwise N. | |
1409 | ||
52882173 AV |
1410 | config PCI_DOMAINS |
1411 | bool | |
1412 | depends on PCI | |
1413 | ||
b080ac8a MRJ |
1414 | config PCI_NANOENGINE |
1415 | bool "BSE nanoEngine PCI support" | |
1416 | depends on SA1100_NANOENGINE | |
1417 | help | |
1418 | Enable PCI on the BSE nanoEngine board. | |
1419 | ||
36e23590 MW |
1420 | config PCI_SYSCALL |
1421 | def_bool PCI | |
1422 | ||
1da177e4 LT |
1423 | # Select the host bridge type |
1424 | config PCI_HOST_VIA82C505 | |
1425 | bool | |
1426 | depends on PCI && ARCH_SHARK | |
1427 | default y | |
1428 | ||
a0113a99 MR |
1429 | config PCI_HOST_ITE8152 |
1430 | bool | |
1431 | depends on PCI && MACH_ARMCORE | |
1432 | default y | |
1433 | select DMABOUNCE | |
1434 | ||
1da177e4 LT |
1435 | source "drivers/pci/Kconfig" |
1436 | ||
1437 | source "drivers/pcmcia/Kconfig" | |
1438 | ||
1439 | endmenu | |
1440 | ||
1441 | menu "Kernel Features" | |
1442 | ||
3b55658a DM |
1443 | config HAVE_SMP |
1444 | bool | |
1445 | help | |
1446 | This option should be selected by machines which have an SMP- | |
1447 | capable CPU. | |
1448 | ||
1449 | The only effect of this option is to make the SMP-related | |
1450 | options available to the user for configuration. | |
1451 | ||
1da177e4 | 1452 | config SMP |
bb2d8130 | 1453 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1454 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1455 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1456 | depends on HAVE_SMP |
9934ebb8 | 1457 | depends on MMU |
f6dd9fa5 | 1458 | select USE_GENERIC_SMP_HELPERS |
89c3dedf | 1459 | select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP |
1da177e4 LT |
1460 | help |
1461 | This enables support for systems with more than one CPU. If you have | |
1462 | a system with only one CPU, like most personal computers, say N. If | |
1463 | you have a system with more than one CPU, say Y. | |
1464 | ||
1465 | If you say N here, the kernel will run on single and multiprocessor | |
1466 | machines, but will use only one CPU of a multiprocessor machine. If | |
1467 | you say Y here, the kernel will run on many, but not all, single | |
1468 | processor machines. On a single processor machine, the kernel will | |
1469 | run faster if you say N here. | |
1470 | ||
395cf969 | 1471 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1472 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1473 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1474 | |
1475 | If you don't know what to do here, say N. | |
1476 | ||
f00ec48f RK |
1477 | config SMP_ON_UP |
1478 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
1479 | depends on EXPERIMENTAL | |
4d2692a7 | 1480 | depends on SMP && !XIP_KERNEL |
f00ec48f RK |
1481 | default y |
1482 | help | |
1483 | SMP kernels contain instructions which fail on non-SMP processors. | |
1484 | Enabling this option allows the kernel to modify itself to make | |
1485 | these instructions safe. Disabling it allows about 1K of space | |
1486 | savings. | |
1487 | ||
1488 | If you don't know what to do here, say Y. | |
1489 | ||
c9018aab VG |
1490 | config ARM_CPU_TOPOLOGY |
1491 | bool "Support cpu topology definition" | |
1492 | depends on SMP && CPU_V7 | |
1493 | default y | |
1494 | help | |
1495 | Support ARM cpu topology definition. The MPIDR register defines | |
1496 | affinity between processors which is then used to describe the cpu | |
1497 | topology of an ARM System. | |
1498 | ||
1499 | config SCHED_MC | |
1500 | bool "Multi-core scheduler support" | |
1501 | depends on ARM_CPU_TOPOLOGY | |
1502 | help | |
1503 | Multi-core scheduler support improves the CPU scheduler's decision | |
1504 | making when dealing with multi-core CPU chips at a cost of slightly | |
1505 | increased overhead in some places. If unsure say N here. | |
1506 | ||
1507 | config SCHED_SMT | |
1508 | bool "SMT scheduler support" | |
1509 | depends on ARM_CPU_TOPOLOGY | |
1510 | help | |
1511 | Improves the CPU scheduler's decision making when dealing with | |
1512 | MultiThreading at a cost of slightly increased overhead in some | |
1513 | places. If unsure say N here. | |
1514 | ||
a8cbcd92 RK |
1515 | config HAVE_ARM_SCU |
1516 | bool | |
a8cbcd92 RK |
1517 | help |
1518 | This option enables support for the ARM system coherency unit | |
1519 | ||
022c03a2 MZ |
1520 | config ARM_ARCH_TIMER |
1521 | bool "Architected timer support" | |
1522 | depends on CPU_V7 | |
1523 | help | |
1524 | This option enables support for the ARM architected timer | |
1525 | ||
f32f4ce2 RK |
1526 | config HAVE_ARM_TWD |
1527 | bool | |
1528 | depends on SMP | |
1529 | help | |
1530 | This options enables support for the ARM timer and watchdog unit | |
1531 | ||
8d5796d2 LB |
1532 | choice |
1533 | prompt "Memory split" | |
1534 | default VMSPLIT_3G | |
1535 | help | |
1536 | Select the desired split between kernel and user memory. | |
1537 | ||
1538 | If you are not absolutely sure what you are doing, leave this | |
1539 | option alone! | |
1540 | ||
1541 | config VMSPLIT_3G | |
1542 | bool "3G/1G user/kernel split" | |
1543 | config VMSPLIT_2G | |
1544 | bool "2G/2G user/kernel split" | |
1545 | config VMSPLIT_1G | |
1546 | bool "1G/3G user/kernel split" | |
1547 | endchoice | |
1548 | ||
1549 | config PAGE_OFFSET | |
1550 | hex | |
1551 | default 0x40000000 if VMSPLIT_1G | |
1552 | default 0x80000000 if VMSPLIT_2G | |
1553 | default 0xC0000000 | |
1554 | ||
1da177e4 LT |
1555 | config NR_CPUS |
1556 | int "Maximum number of CPUs (2-32)" | |
1557 | range 2 32 | |
1558 | depends on SMP | |
1559 | default "4" | |
1560 | ||
a054a811 RK |
1561 | config HOTPLUG_CPU |
1562 | bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" | |
1563 | depends on SMP && HOTPLUG && EXPERIMENTAL | |
1564 | help | |
1565 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1566 | can be controlled through /sys/devices/system/cpu. | |
1567 | ||
37ee16ae RK |
1568 | config LOCAL_TIMERS |
1569 | bool "Use local timer interrupts" | |
971acb9b | 1570 | depends on SMP |
37ee16ae | 1571 | default y |
30d8bead | 1572 | select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) |
37ee16ae RK |
1573 | help |
1574 | Enable support for local timers on SMP platforms, rather then the | |
1575 | legacy IPI broadcast method. Local timers allows the system | |
1576 | accounting to be spread across the timer interval, preventing a | |
1577 | "thundering herd" at every timer tick. | |
1578 | ||
44986ab0 PDSN |
1579 | config ARCH_NR_GPIO |
1580 | int | |
3dea19e8 | 1581 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
70227a45 | 1582 | default 355 if ARCH_U8500 |
9a01ec30 | 1583 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1584 | default 0 |
1585 | help | |
1586 | Maximum number of GPIOs in the system. | |
1587 | ||
1588 | If unsure, leave the default value. | |
1589 | ||
d45a398f | 1590 | source kernel/Kconfig.preempt |
1da177e4 | 1591 | |
f8065813 RK |
1592 | config HZ |
1593 | int | |
b130d5c2 | 1594 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ |
a73ddc61 | 1595 | ARCH_S5PV210 || ARCH_EXYNOS4 |
bfe65704 | 1596 | default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER |
5248c657 | 1597 | default AT91_TIMER_HZ if ARCH_AT91 |
5da3e714 | 1598 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE |
f8065813 RK |
1599 | default 100 |
1600 | ||
16c79651 | 1601 | config THUMB2_KERNEL |
4a50bfe3 | 1602 | bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" |
e399b1a4 | 1603 | depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL |
16c79651 CM |
1604 | select AEABI |
1605 | select ARM_ASM_UNIFIED | |
89bace65 | 1606 | select ARM_UNWIND |
16c79651 CM |
1607 | help |
1608 | By enabling this option, the kernel will be compiled in | |
1609 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1610 | ARM-Thumb syntax is needed. | |
1611 | ||
1612 | If unsure, say N. | |
1613 | ||
6f685c5c DM |
1614 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1615 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1616 | depends on THUMB2_KERNEL && MODULES | |
1617 | default y | |
1618 | help | |
1619 | Various binutils versions can resolve Thumb-2 branches to | |
1620 | locally-defined, preemptible global symbols as short-range "b.n" | |
1621 | branch instructions. | |
1622 | ||
1623 | This is a problem, because there's no guarantee the final | |
1624 | destination of the symbol, or any candidate locations for a | |
1625 | trampoline, are within range of the branch. For this reason, the | |
1626 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1627 | relocation in modules at all, and it makes little sense to add | |
1628 | support. | |
1629 | ||
1630 | The symptom is that the kernel fails with an "unsupported | |
1631 | relocation" error when loading some modules. | |
1632 | ||
1633 | Until fixed tools are available, passing | |
1634 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1635 | code which hits this problem, at the cost of a bit of extra runtime | |
1636 | stack usage in some cases. | |
1637 | ||
1638 | The problem is described in more detail at: | |
1639 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1640 | ||
1641 | Only Thumb-2 kernels are affected. | |
1642 | ||
1643 | Unless you are sure your tools don't have this problem, say Y. | |
1644 | ||
0becb088 CM |
1645 | config ARM_ASM_UNIFIED |
1646 | bool | |
1647 | ||
704bdda0 NP |
1648 | config AEABI |
1649 | bool "Use the ARM EABI to compile the kernel" | |
1650 | help | |
1651 | This option allows for the kernel to be compiled using the latest | |
1652 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1653 | space environment that is also compiled with EABI. | |
1654 | ||
1655 | Since there are major incompatibilities between the legacy ABI and | |
1656 | EABI, especially with regard to structure member alignment, this | |
1657 | option also changes the kernel syscall calling convention to | |
1658 | disambiguate both ABIs and allow for backward compatibility support | |
1659 | (selected with CONFIG_OABI_COMPAT). | |
1660 | ||
1661 | To use this you need GCC version 4.0.0 or later. | |
1662 | ||
6c90c872 | 1663 | config OABI_COMPAT |
a73a3ff1 | 1664 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
9bc433a1 | 1665 | depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL |
6c90c872 NP |
1666 | default y |
1667 | help | |
1668 | This option preserves the old syscall interface along with the | |
1669 | new (ARM EABI) one. It also provides a compatibility layer to | |
1670 | intercept syscalls that have structure arguments which layout | |
1671 | in memory differs between the legacy ABI and the new ARM EABI | |
1672 | (only for non "thumb" binaries). This option adds a tiny | |
1673 | overhead to all syscalls and produces a slightly larger kernel. | |
1674 | If you know you'll be using only pure EABI user space then you | |
1675 | can say N here. If this option is not selected and you attempt | |
1676 | to execute a legacy ABI binary then the result will be | |
1677 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
1678 | at all). If in doubt say Y. | |
1679 | ||
eb33575c | 1680 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1681 | bool |
e80d6a24 | 1682 | |
05944d74 RK |
1683 | config ARCH_SPARSEMEM_ENABLE |
1684 | bool | |
1685 | ||
07a2f737 RK |
1686 | config ARCH_SPARSEMEM_DEFAULT |
1687 | def_bool ARCH_SPARSEMEM_ENABLE | |
1688 | ||
05944d74 | 1689 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1690 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1691 | |
7b7bf499 WD |
1692 | config HAVE_ARCH_PFN_VALID |
1693 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1694 | ||
053a96ca | 1695 | config HIGHMEM |
e8db89a2 RK |
1696 | bool "High Memory Support" |
1697 | depends on MMU | |
053a96ca NP |
1698 | help |
1699 | The address space of ARM processors is only 4 Gigabytes large | |
1700 | and it has to accommodate user address space, kernel address | |
1701 | space as well as some memory mapped IO. That means that, if you | |
1702 | have a large amount of physical memory and/or IO, not all of the | |
1703 | memory can be "permanently mapped" by the kernel. The physical | |
1704 | memory that is not permanently mapped is called "high memory". | |
1705 | ||
1706 | Depending on the selected kernel/user memory split, minimum | |
1707 | vmalloc space and actual amount of RAM, you may not need this | |
1708 | option which should result in a slightly faster kernel. | |
1709 | ||
1710 | If unsure, say n. | |
1711 | ||
65cec8e3 RK |
1712 | config HIGHPTE |
1713 | bool "Allocate 2nd-level pagetables from highmem" | |
1714 | depends on HIGHMEM | |
65cec8e3 | 1715 | |
1b8873a0 JI |
1716 | config HW_PERF_EVENTS |
1717 | bool "Enable hardware performance counter support for perf events" | |
fe166148 | 1718 | depends on PERF_EVENTS && CPU_HAS_PMU |
1b8873a0 JI |
1719 | default y |
1720 | help | |
1721 | Enable hardware performance counter support for perf events. If | |
1722 | disabled, perf events will use software events only. | |
1723 | ||
3f22ab27 DH |
1724 | source "mm/Kconfig" |
1725 | ||
c1b2d970 MD |
1726 | config FORCE_MAX_ZONEORDER |
1727 | int "Maximum zone order" if ARCH_SHMOBILE | |
1728 | range 11 64 if ARCH_SHMOBILE | |
1729 | default "9" if SA1111 | |
1730 | default "11" | |
1731 | help | |
1732 | The kernel memory allocator divides physically contiguous memory | |
1733 | blocks into "zones", where each zone is a power of two number of | |
1734 | pages. This option selects the largest power of two that the kernel | |
1735 | keeps in the memory allocator. If you need to allocate very large | |
1736 | blocks of physically contiguous memory, then you may need to | |
1737 | increase this value. | |
1738 | ||
1739 | This config option is actually maximum order plus one. For example, | |
1740 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1741 | ||
1da177e4 LT |
1742 | config LEDS |
1743 | bool "Timer and CPU usage LEDs" | |
e055d5bf | 1744 | depends on ARCH_CDB89712 || ARCH_EBSA110 || \ |
8c8fdbc9 | 1745 | ARCH_EBSA285 || ARCH_INTEGRATOR || \ |
1da177e4 LT |
1746 | ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ |
1747 | ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ | |
73a59c1c | 1748 | ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ |
25329671 | 1749 | ARCH_AT91 || ARCH_DAVINCI || \ |
ff3042fb | 1750 | ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW |
1da177e4 LT |
1751 | help |
1752 | If you say Y here, the LEDs on your machine will be used | |
1753 | to provide useful information about your current system status. | |
1754 | ||
1755 | If you are compiling a kernel for a NetWinder or EBSA-285, you will | |
1756 | be able to select which LEDs are active using the options below. If | |
1757 | you are compiling a kernel for the EBSA-110 or the LART however, the | |
1758 | red LED will simply flash regularly to indicate that the system is | |
1759 | still functional. It is safe to say Y here if you have a CATS | |
1760 | system, but the driver will do nothing. | |
1761 | ||
1762 | config LEDS_TIMER | |
1763 | bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ | |
eebdf7d7 DB |
1764 | OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ |
1765 | || MACH_OMAP_PERSEUS2 | |
1da177e4 | 1766 | depends on LEDS |
0567a0c0 | 1767 | depends on !GENERIC_CLOCKEVENTS |
1da177e4 LT |
1768 | default y if ARCH_EBSA110 |
1769 | help | |
1770 | If you say Y here, one of the system LEDs (the green one on the | |
1771 | NetWinder, the amber one on the EBSA285, or the red one on the LART) | |
1772 | will flash regularly to indicate that the system is still | |
1773 | operational. This is mainly useful to kernel hackers who are | |
1774 | debugging unstable kernels. | |
1775 | ||
1776 | The LART uses the same LED for both Timer LED and CPU usage LED | |
1777 | functions. You may choose to use both, but the Timer LED function | |
1778 | will overrule the CPU usage LED. | |
1779 | ||
1780 | config LEDS_CPU | |
1781 | bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ | |
eebdf7d7 DB |
1782 | !ARCH_OMAP) \ |
1783 | || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ | |
1784 | || MACH_OMAP_PERSEUS2 | |
1da177e4 LT |
1785 | depends on LEDS |
1786 | help | |
1787 | If you say Y here, the red LED will be used to give a good real | |
1788 | time indication of CPU usage, by lighting whenever the idle task | |
1789 | is not currently executing. | |
1790 | ||
1791 | The LART uses the same LED for both Timer LED and CPU usage LED | |
1792 | functions. You may choose to use both, but the Timer LED function | |
1793 | will overrule the CPU usage LED. | |
1794 | ||
1795 | config ALIGNMENT_TRAP | |
1796 | bool | |
f12d0d7c | 1797 | depends on CPU_CP15_MMU |
1da177e4 | 1798 | default y if !ARCH_EBSA110 |
e119bfff | 1799 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1800 | help |
84eb8d06 | 1801 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1802 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1803 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1804 | fetch/store instructions will be emulated in software if you say | |
1805 | here, which has a severe performance impact. This is necessary for | |
1806 | correct operation of some network protocols. With an IP-only | |
1807 | configuration it is safe to say N, otherwise say Y. | |
1808 | ||
39ec58f3 LB |
1809 | config UACCESS_WITH_MEMCPY |
1810 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" | |
1811 | depends on MMU && EXPERIMENTAL | |
1812 | default y if CPU_FEROCEON | |
1813 | help | |
1814 | Implement faster copy_to_user and clear_user methods for CPU | |
1815 | cores where a 8-word STM instruction give significantly higher | |
1816 | memory write throughput than a sequence of individual 32bit stores. | |
1817 | ||
1818 | A possible side effect is a slight increase in scheduling latency | |
1819 | between threads sharing the same address space if they invoke | |
1820 | such copy operations with large buffers. | |
1821 | ||
1822 | However, if the CPU data cache is using a write-allocate mode, | |
1823 | this option is unlikely to provide any performance gain. | |
1824 | ||
70c70d97 NP |
1825 | config SECCOMP |
1826 | bool | |
1827 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1828 | ---help--- | |
1829 | This kernel feature is useful for number crunching applications | |
1830 | that may need to compute untrusted bytecode during their | |
1831 | execution. By using pipes or other transports made available to | |
1832 | the process as file descriptors supporting the read/write | |
1833 | syscalls, it's possible to isolate those applications in | |
1834 | their own address space using seccomp. Once seccomp is | |
1835 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1836 | and the task is only allowed to execute a few safe syscalls | |
1837 | defined by each seccomp mode. | |
1838 | ||
c743f380 NP |
1839 | config CC_STACKPROTECTOR |
1840 | bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" | |
4a50bfe3 | 1841 | depends on EXPERIMENTAL |
c743f380 NP |
1842 | help |
1843 | This option turns on the -fstack-protector GCC feature. This | |
1844 | feature puts, at the beginning of functions, a canary value on | |
1845 | the stack just before the return address, and validates | |
1846 | the value just before actually returning. Stack based buffer | |
1847 | overflows (that need to overwrite this return address) now also | |
1848 | overwrite the canary, which gets detected and the attack is then | |
1849 | neutralized via a kernel panic. | |
1850 | This feature requires gcc version 4.2 or above. | |
1851 | ||
73a65b3f UKK |
1852 | config DEPRECATED_PARAM_STRUCT |
1853 | bool "Provide old way to pass kernel parameters" | |
1854 | help | |
1855 | This was deprecated in 2001 and announced to live on for 5 years. | |
1856 | Some old boot loaders still use this way. | |
1857 | ||
1da177e4 LT |
1858 | endmenu |
1859 | ||
1860 | menu "Boot options" | |
1861 | ||
9eb8f674 GL |
1862 | config USE_OF |
1863 | bool "Flattened Device Tree support" | |
1864 | select OF | |
1865 | select OF_EARLY_FLATTREE | |
08a543ad | 1866 | select IRQ_DOMAIN |
9eb8f674 GL |
1867 | help |
1868 | Include support for flattened device tree machine descriptions. | |
1869 | ||
1da177e4 LT |
1870 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1871 | # TEXT and BSS so we preserve their values in the config files. | |
1872 | config ZBOOT_ROM_TEXT | |
1873 | hex "Compressed ROM boot loader base address" | |
1874 | default "0" | |
1875 | help | |
1876 | The physical address at which the ROM-able zImage is to be | |
1877 | placed in the target. Platforms which normally make use of | |
1878 | ROM-able zImage formats normally set this to a suitable | |
1879 | value in their defconfig file. | |
1880 | ||
1881 | If ZBOOT_ROM is not enabled, this has no effect. | |
1882 | ||
1883 | config ZBOOT_ROM_BSS | |
1884 | hex "Compressed ROM boot loader BSS address" | |
1885 | default "0" | |
1886 | help | |
f8c440b2 DF |
1887 | The base address of an area of read/write memory in the target |
1888 | for the ROM-able zImage which must be available while the | |
1889 | decompressor is running. It must be large enough to hold the | |
1890 | entire decompressed kernel plus an additional 128 KiB. | |
1891 | Platforms which normally make use of ROM-able zImage formats | |
1892 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1893 | |
1894 | If ZBOOT_ROM is not enabled, this has no effect. | |
1895 | ||
1896 | config ZBOOT_ROM | |
1897 | bool "Compressed boot loader in ROM/flash" | |
1898 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
1899 | help | |
1900 | Say Y here if you intend to execute your compressed kernel image | |
1901 | (zImage) directly from ROM or flash. If unsure, say N. | |
1902 | ||
090ab3ff SH |
1903 | choice |
1904 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
1905 | depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL | |
1906 | default ZBOOT_ROM_NONE | |
1907 | help | |
1908 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
59bf8964 | 1909 | With this enabled it is possible to write the ROM-able zImage |
090ab3ff SH |
1910 | kernel image to an MMC or SD card and boot the kernel straight |
1911 | from the reset vector. At reset the processor Mask ROM will load | |
59bf8964 | 1912 | the first part of the ROM-able zImage which in turn loads the |
090ab3ff SH |
1913 | rest the kernel image to RAM. |
1914 | ||
1915 | config ZBOOT_ROM_NONE | |
1916 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1917 | help | |
1918 | Do not load image from SD or MMC | |
1919 | ||
f45b1149 SH |
1920 | config ZBOOT_ROM_MMCIF |
1921 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
f45b1149 | 1922 | help |
090ab3ff SH |
1923 | Load image from MMCIF hardware block. |
1924 | ||
1925 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
1926 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
1927 | help | |
1928 | Load image from SDHI hardware block | |
1929 | ||
1930 | endchoice | |
f45b1149 | 1931 | |
e2a6a3aa JB |
1932 | config ARM_APPENDED_DTB |
1933 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
1934 | depends on OF && !ZBOOT_ROM && EXPERIMENTAL | |
1935 | help | |
1936 | With this option, the boot code will look for a device tree binary | |
1937 | (DTB) appended to zImage | |
1938 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1939 | ||
1940 | This is meant as a backward compatibility convenience for those | |
1941 | systems with a bootloader that can't be upgraded to accommodate | |
1942 | the documented boot protocol using a device tree. | |
1943 | ||
1944 | Beware that there is very little in terms of protection against | |
1945 | this option being confused by leftover garbage in memory that might | |
1946 | look like a DTB header after a reboot if no actual DTB is appended | |
1947 | to zImage. Do not leave this option active in a production kernel | |
1948 | if you don't intend to always append a DTB. Proper passing of the | |
1949 | location into r2 of a bootloader provided DTB is always preferable | |
1950 | to this option. | |
1951 | ||
b90b9a38 NP |
1952 | config ARM_ATAG_DTB_COMPAT |
1953 | bool "Supplement the appended DTB with traditional ATAG information" | |
1954 | depends on ARM_APPENDED_DTB | |
1955 | help | |
1956 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1957 | they provide ATAGs with memory configuration, the ramdisk address, | |
1958 | the kernel cmdline string, etc. Such information is dynamically | |
1959 | provided by the bootloader and can't always be stored in a static | |
1960 | DTB. To allow a device tree enabled kernel to be used with such | |
1961 | bootloaders, this option allows zImage to extract the information | |
1962 | from the ATAG list and store it at run time into the appended DTB. | |
1963 | ||
1da177e4 LT |
1964 | config CMDLINE |
1965 | string "Default kernel command string" | |
1966 | default "" | |
1967 | help | |
1968 | On some architectures (EBSA110 and CATS), there is currently no way | |
1969 | for the boot loader to pass arguments to the kernel. For these | |
1970 | architectures, you should supply some command-line options at build | |
1971 | time by entering them here. As a minimum, you should specify the | |
1972 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1973 | ||
4394c124 VB |
1974 | choice |
1975 | prompt "Kernel command line type" if CMDLINE != "" | |
1976 | default CMDLINE_FROM_BOOTLOADER | |
1977 | ||
1978 | config CMDLINE_FROM_BOOTLOADER | |
1979 | bool "Use bootloader kernel arguments if available" | |
1980 | help | |
1981 | Uses the command-line options passed by the boot loader. If | |
1982 | the boot loader doesn't provide any, the default kernel command | |
1983 | string provided in CMDLINE will be used. | |
1984 | ||
1985 | config CMDLINE_EXTEND | |
1986 | bool "Extend bootloader kernel arguments" | |
1987 | help | |
1988 | The command-line arguments provided by the boot loader will be | |
1989 | appended to the default kernel command string. | |
1990 | ||
92d2040d AH |
1991 | config CMDLINE_FORCE |
1992 | bool "Always use the default kernel command string" | |
92d2040d AH |
1993 | help |
1994 | Always use the default kernel command string, even if the boot | |
1995 | loader passes other arguments to the kernel. | |
1996 | This is useful if you cannot or don't want to change the | |
1997 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1998 | endchoice |
92d2040d | 1999 | |
1da177e4 LT |
2000 | config XIP_KERNEL |
2001 | bool "Kernel Execute-In-Place from ROM" | |
497b7e94 | 2002 | depends on !ZBOOT_ROM && !ARM_LPAE |
1da177e4 LT |
2003 | help |
2004 | Execute-In-Place allows the kernel to run from non-volatile storage | |
2005 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
2006 | space since the text section of the kernel is not loaded from flash | |
2007 | to RAM. Read-write sections, such as the data section and stack, | |
2008 | are still copied to RAM. The XIP kernel is not compressed since | |
2009 | it has to run directly from flash, so it will take more space to | |
2010 | store it. The flash address used to link the kernel object files, | |
2011 | and for storing it, is configuration dependent. Therefore, if you | |
2012 | say Y here, you must know the proper physical address where to | |
2013 | store the kernel image depending on your own flash memory usage. | |
2014 | ||
2015 | Also note that the make target becomes "make xipImage" rather than | |
2016 | "make zImage" or "make Image". The final kernel binary to put in | |
2017 | ROM memory will be arch/arm/boot/xipImage. | |
2018 | ||
2019 | If unsure, say N. | |
2020 | ||
2021 | config XIP_PHYS_ADDR | |
2022 | hex "XIP Kernel Physical Location" | |
2023 | depends on XIP_KERNEL | |
2024 | default "0x00080000" | |
2025 | help | |
2026 | This is the physical address in your flash memory the kernel will | |
2027 | be linked for and stored to. This address is dependent on your | |
2028 | own flash usage. | |
2029 | ||
c587e4a6 RP |
2030 | config KEXEC |
2031 | bool "Kexec system call (EXPERIMENTAL)" | |
02b73e2e | 2032 | depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU) |
c587e4a6 RP |
2033 | help |
2034 | kexec is a system call that implements the ability to shutdown your | |
2035 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 2036 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
2037 | you can start any kernel with it, not just Linux. |
2038 | ||
2039 | It is an ongoing process to be certain the hardware in a machine | |
2040 | is properly shutdown, so do not be surprised if this code does not | |
2041 | initially work for you. It may help to enable device hotplugging | |
2042 | support. | |
2043 | ||
4cd9d6f7 RP |
2044 | config ATAGS_PROC |
2045 | bool "Export atags in procfs" | |
b98d7291 UL |
2046 | depends on KEXEC |
2047 | default y | |
4cd9d6f7 RP |
2048 | help |
2049 | Should the atags used to boot the kernel be exported in an "atags" | |
2050 | file in procfs. Useful with kexec. | |
2051 | ||
cb5d39b3 MW |
2052 | config CRASH_DUMP |
2053 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
2054 | depends on EXPERIMENTAL | |
2055 | help | |
2056 | Generate crash dump after being started by kexec. This should | |
2057 | be normally only set in special crash dump kernels which are | |
2058 | loaded in the main kernel with kexec-tools into a specially | |
2059 | reserved region and then later executed after a crash by | |
2060 | kdump/kexec. The crash dump kernel must be compiled to a | |
2061 | memory address not used by the main kernel | |
2062 | ||
2063 | For more details see Documentation/kdump/kdump.txt | |
2064 | ||
e69edc79 EM |
2065 | config AUTO_ZRELADDR |
2066 | bool "Auto calculation of the decompressed kernel image address" | |
2067 | depends on !ZBOOT_ROM && !ARCH_U300 | |
2068 | help | |
2069 | ZRELADDR is the physical address where the decompressed kernel | |
2070 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2071 | will be determined at run-time by masking the current IP with | |
2072 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2073 | from start of memory. | |
2074 | ||
1da177e4 LT |
2075 | endmenu |
2076 | ||
ac9d7efc | 2077 | menu "CPU Power Management" |
1da177e4 | 2078 | |
89c52ed4 | 2079 | if ARCH_HAS_CPUFREQ |
1da177e4 LT |
2080 | |
2081 | source "drivers/cpufreq/Kconfig" | |
2082 | ||
64f102b6 YS |
2083 | config CPU_FREQ_IMX |
2084 | tristate "CPUfreq driver for i.MX CPUs" | |
2085 | depends on ARCH_MXC && CPU_FREQ | |
2086 | help | |
2087 | This enables the CPUfreq driver for i.MX CPUs. | |
2088 | ||
1da177e4 LT |
2089 | config CPU_FREQ_SA1100 |
2090 | bool | |
1da177e4 LT |
2091 | |
2092 | config CPU_FREQ_SA1110 | |
2093 | bool | |
1da177e4 LT |
2094 | |
2095 | config CPU_FREQ_INTEGRATOR | |
2096 | tristate "CPUfreq driver for ARM Integrator CPUs" | |
2097 | depends on ARCH_INTEGRATOR && CPU_FREQ | |
2098 | default y | |
2099 | help | |
2100 | This enables the CPUfreq driver for ARM Integrator CPUs. | |
2101 | ||
2102 | For details, take a look at <file:Documentation/cpu-freq>. | |
2103 | ||
2104 | If in doubt, say Y. | |
2105 | ||
9e2697ff RK |
2106 | config CPU_FREQ_PXA |
2107 | bool | |
2108 | depends on CPU_FREQ && ARCH_PXA && PXA25x | |
2109 | default y | |
ca7d156e | 2110 | select CPU_FREQ_TABLE |
9e2697ff RK |
2111 | select CPU_FREQ_DEFAULT_GOV_USERSPACE |
2112 | ||
9d56c02a BD |
2113 | config CPU_FREQ_S3C |
2114 | bool | |
2115 | help | |
2116 | Internal configuration node for common cpufreq on Samsung SoC | |
2117 | ||
2118 | config CPU_FREQ_S3C24XX | |
4a50bfe3 | 2119 | bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" |
b130d5c2 | 2120 | depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL |
9d56c02a BD |
2121 | select CPU_FREQ_S3C |
2122 | help | |
2123 | This enables the CPUfreq driver for the Samsung S3C24XX family | |
2124 | of CPUs. | |
2125 | ||
2126 | For details, take a look at <file:Documentation/cpu-freq>. | |
2127 | ||
2128 | If in doubt, say N. | |
2129 | ||
2130 | config CPU_FREQ_S3C24XX_PLL | |
4a50bfe3 | 2131 | bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" |
9d56c02a BD |
2132 | depends on CPU_FREQ_S3C24XX && EXPERIMENTAL |
2133 | help | |
2134 | Compile in support for changing the PLL frequency from the | |
2135 | S3C24XX series CPUfreq driver. The PLL takes time to settle | |
2136 | after a frequency change, so by default it is not enabled. | |
2137 | ||
2138 | This also means that the PLL tables for the selected CPU(s) will | |
2139 | be built which may increase the size of the kernel image. | |
2140 | ||
2141 | config CPU_FREQ_S3C24XX_DEBUG | |
2142 | bool "Debug CPUfreq Samsung driver core" | |
2143 | depends on CPU_FREQ_S3C24XX | |
2144 | help | |
2145 | Enable s3c_freq_dbg for the Samsung S3C CPUfreq core | |
2146 | ||
2147 | config CPU_FREQ_S3C24XX_IODEBUG | |
2148 | bool "Debug CPUfreq Samsung driver IO timing" | |
2149 | depends on CPU_FREQ_S3C24XX | |
2150 | help | |
2151 | Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core | |
2152 | ||
e6d197a6 BD |
2153 | config CPU_FREQ_S3C24XX_DEBUGFS |
2154 | bool "Export debugfs for CPUFreq" | |
2155 | depends on CPU_FREQ_S3C24XX && DEBUG_FS | |
2156 | help | |
2157 | Export status information via debugfs. | |
2158 | ||
1da177e4 LT |
2159 | endif |
2160 | ||
ac9d7efc RK |
2161 | source "drivers/cpuidle/Kconfig" |
2162 | ||
2163 | endmenu | |
2164 | ||
1da177e4 LT |
2165 | menu "Floating point emulation" |
2166 | ||
2167 | comment "At least one emulation must be selected" | |
2168 | ||
2169 | config FPE_NWFPE | |
2170 | bool "NWFPE math emulation" | |
593c252a | 2171 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2172 | ---help--- |
2173 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2174 | This is necessary to run most binaries. Linux does not currently | |
2175 | support floating point hardware so you need to say Y here even if | |
2176 | your machine has an FPA or floating point co-processor podule. | |
2177 | ||
2178 | You may say N here if you are going to load the Acorn FPEmulator | |
2179 | early in the bootup. | |
2180 | ||
2181 | config FPE_NWFPE_XP | |
2182 | bool "Support extended precision" | |
bedf142b | 2183 | depends on FPE_NWFPE |
1da177e4 LT |
2184 | help |
2185 | Say Y to include 80-bit support in the kernel floating-point | |
2186 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2187 | Note that gcc does not generate 80-bit operations by default, | |
2188 | so in most cases this option only enlarges the size of the | |
2189 | floating point emulator without any good reason. | |
2190 | ||
2191 | You almost surely want to say N here. | |
2192 | ||
2193 | config FPE_FASTFPE | |
2194 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
8993a44c | 2195 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL |
1da177e4 LT |
2196 | ---help--- |
2197 | Say Y here to include the FAST floating point emulator in the kernel. | |
2198 | This is an experimental much faster emulator which now also has full | |
2199 | precision for the mantissa. It does not support any exceptions. | |
2200 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2201 | ||
2202 | It should be sufficient for most programs. It may be not suitable | |
2203 | for scientific calculations, but you have to check this for yourself. | |
2204 | If you do not feel you need a faster FP emulation you should better | |
2205 | choose NWFPE. | |
2206 | ||
2207 | config VFP | |
2208 | bool "VFP-format floating point maths" | |
e399b1a4 | 2209 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2210 | help |
2211 | Say Y to include VFP support code in the kernel. This is needed | |
2212 | if your hardware includes a VFP unit. | |
2213 | ||
2214 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2215 | release notes and additional status information. | |
2216 | ||
2217 | Say N if your target does not have VFP hardware. | |
2218 | ||
25ebee02 CM |
2219 | config VFPv3 |
2220 | bool | |
2221 | depends on VFP | |
2222 | default y if CPU_V7 | |
2223 | ||
b5872db4 CM |
2224 | config NEON |
2225 | bool "Advanced SIMD (NEON) Extension support" | |
2226 | depends on VFPv3 && CPU_V7 | |
2227 | help | |
2228 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2229 | Extension. | |
2230 | ||
1da177e4 LT |
2231 | endmenu |
2232 | ||
2233 | menu "Userspace binary formats" | |
2234 | ||
2235 | source "fs/Kconfig.binfmt" | |
2236 | ||
2237 | config ARTHUR | |
2238 | tristate "RISC OS personality" | |
704bdda0 | 2239 | depends on !AEABI |
1da177e4 LT |
2240 | help |
2241 | Say Y here to include the kernel code necessary if you want to run | |
2242 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2243 | experimental; if this sounds frightening, say N and sleep in peace. | |
2244 | You can also say M here to compile this support as a module (which | |
2245 | will be called arthur). | |
2246 | ||
2247 | endmenu | |
2248 | ||
2249 | menu "Power management options" | |
2250 | ||
eceab4ac | 2251 | source "kernel/power/Kconfig" |
1da177e4 | 2252 | |
f4cb5700 | 2253 | config ARCH_SUSPEND_POSSIBLE |
3d5e8af4 | 2254 | depends on !ARCH_S5PC100 && !ARCH_TEGRA |
6a786182 | 2255 | depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ |
3f5d0819 | 2256 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2257 | def_bool y |
2258 | ||
15e0d9e3 AB |
2259 | config ARM_CPU_SUSPEND |
2260 | def_bool PM_SLEEP | |
2261 | ||
1da177e4 LT |
2262 | endmenu |
2263 | ||
d5950b43 SR |
2264 | source "net/Kconfig" |
2265 | ||
ac25150f | 2266 | source "drivers/Kconfig" |
1da177e4 LT |
2267 | |
2268 | source "fs/Kconfig" | |
2269 | ||
1da177e4 LT |
2270 | source "arch/arm/Kconfig.debug" |
2271 | ||
2272 | source "security/Kconfig" | |
2273 | ||
2274 | source "crypto/Kconfig" | |
2275 | ||
2276 | source "lib/Kconfig" |