Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | config ARM |
2 | bool | |
3 | default y | |
b1b3f49c RK |
4 | select ARCH_BINFMT_ELF_RANDOMIZE_PIE |
5 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE | |
3d06770e | 6 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
171b3f0d | 7 | select ARCH_HAVE_CUSTOM_GPIO_H |
d7018848 | 8 | select ARCH_MIGHT_HAVE_PC_PARPORT |
4badad35 | 9 | select ARCH_SUPPORTS_ATOMIC_RMW |
017f161a | 10 | select ARCH_USE_BUILTIN_BSWAP |
0cbad9c9 | 11 | select ARCH_USE_CMPXCHG_LOCKREF |
b1b3f49c | 12 | select ARCH_WANT_IPC_PARSE_VERSION |
ee951c63 | 13 | select BUILDTIME_EXTABLE_SORT if MMU |
171b3f0d | 14 | select CLONE_BACKWARDS |
b1b3f49c | 15 | select CPU_PM if (SUSPEND || CPU_IDLE) |
dce5c9e3 | 16 | select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS |
36d0fd21 | 17 | select GENERIC_ALLOCATOR |
4477ca45 | 18 | select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) |
b1b3f49c | 19 | select GENERIC_CLOCKEVENTS_BROADCAST if SMP |
171b3f0d | 20 | select GENERIC_IDLE_POLL_SETUP |
b1b3f49c RK |
21 | select GENERIC_IRQ_PROBE |
22 | select GENERIC_IRQ_SHOW | |
b1b3f49c | 23 | select GENERIC_PCI_IOMAP |
38ff87f7 | 24 | select GENERIC_SCHED_CLOCK |
b1b3f49c RK |
25 | select GENERIC_SMP_IDLE_THREAD |
26 | select GENERIC_STRNCPY_FROM_USER | |
27 | select GENERIC_STRNLEN_USER | |
a71b092a | 28 | select HANDLE_DOMAIN_IRQ |
b1b3f49c | 29 | select HARDIRQS_SW_RESEND |
7a017721 | 30 | select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) |
09f05d85 | 31 | select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL |
5cbad0eb | 32 | select HAVE_ARCH_KGDB |
91702175 | 33 | select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) |
0693bf68 | 34 | select HAVE_ARCH_TRACEHOOK |
b1b3f49c | 35 | select HAVE_BPF_JIT |
51aaf81f | 36 | select HAVE_CC_STACKPROTECTOR |
171b3f0d | 37 | select HAVE_CONTEXT_TRACKING |
b1b3f49c RK |
38 | select HAVE_C_RECORDMCOUNT |
39 | select HAVE_DEBUG_KMEMLEAK | |
40 | select HAVE_DMA_API_DEBUG | |
41 | select HAVE_DMA_ATTRS | |
42 | select HAVE_DMA_CONTIGUOUS if MMU | |
80be7a7f | 43 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) |
dce5c9e3 | 44 | select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU |
b1b3f49c | 45 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
0e341af8 | 46 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) |
b1b3f49c | 47 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
1fe53268 | 48 | select HAVE_GENERIC_DMA_COHERENT |
b1b3f49c RK |
49 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
50 | select HAVE_IDE if PCI || ISA || PCMCIA | |
87c46b6c | 51 | select HAVE_IRQ_TIME_ACCOUNTING |
e7db7b42 | 52 | select HAVE_KERNEL_GZIP |
f9b493ac | 53 | select HAVE_KERNEL_LZ4 |
6e8699f7 | 54 | select HAVE_KERNEL_LZMA |
b1b3f49c | 55 | select HAVE_KERNEL_LZO |
a7f464f3 | 56 | select HAVE_KERNEL_XZ |
b1b3f49c RK |
57 | select HAVE_KPROBES if !XIP_KERNEL |
58 | select HAVE_KRETPROBES if (HAVE_KPROBES) | |
59 | select HAVE_MEMBLOCK | |
171b3f0d | 60 | select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND |
b1b3f49c | 61 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
7ada189f | 62 | select HAVE_PERF_EVENTS |
49863894 WD |
63 | select HAVE_PERF_REGS |
64 | select HAVE_PERF_USER_STACK_DUMP | |
a0ad5496 | 65 | select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) |
e513f8bf | 66 | select HAVE_REGS_AND_STACK_ACCESS_API |
b1b3f49c | 67 | select HAVE_SYSCALL_TRACEPOINTS |
af1839eb | 68 | select HAVE_UID16 |
31c1fc81 | 69 | select HAVE_VIRT_CPU_ACCOUNTING_GEN |
da0ec6f7 | 70 | select IRQ_FORCED_THREADING |
171b3f0d | 71 | select MODULES_USE_ELF_REL |
84f452b1 | 72 | select NO_BOOTMEM |
171b3f0d RK |
73 | select OLD_SIGACTION |
74 | select OLD_SIGSUSPEND3 | |
b1b3f49c RK |
75 | select PERF_USE_VMALLOC |
76 | select RTC_LIB | |
77 | select SYS_SUPPORTS_APM_EMULATION | |
171b3f0d RK |
78 | # Above selects are sorted alphabetically; please add new ones |
79 | # according to that. Thanks. | |
1da177e4 LT |
80 | help |
81 | The ARM series is a line of low-power-consumption RISC chip designs | |
f6c8965a | 82 | licensed by ARM Ltd and targeted at embedded applications and |
1da177e4 | 83 | handhelds such as the Compaq IPAQ. ARM-based PCs are no longer |
f6c8965a | 84 | manufactured, but legacy ARM-based PC hardware remains popular in |
1da177e4 LT |
85 | Europe. There is an ARM Linux project with a web page at |
86 | <http://www.arm.linux.org.uk/>. | |
87 | ||
74facffe | 88 | config ARM_HAS_SG_CHAIN |
308c09f1 | 89 | select ARCH_HAS_SG_CHAIN |
74facffe RK |
90 | bool |
91 | ||
4ce63fcd MS |
92 | config NEED_SG_DMA_LENGTH |
93 | bool | |
94 | ||
95 | config ARM_DMA_USE_IOMMU | |
4ce63fcd | 96 | bool |
b1b3f49c RK |
97 | select ARM_HAS_SG_CHAIN |
98 | select NEED_SG_DMA_LENGTH | |
4ce63fcd | 99 | |
60460abf SWK |
100 | if ARM_DMA_USE_IOMMU |
101 | ||
102 | config ARM_DMA_IOMMU_ALIGNMENT | |
103 | int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" | |
104 | range 4 9 | |
105 | default 8 | |
106 | help | |
107 | DMA mapping framework by default aligns all buffers to the smallest | |
108 | PAGE_SIZE order which is greater than or equal to the requested buffer | |
109 | size. This works well for buffers up to a few hundreds kilobytes, but | |
110 | for larger buffers it just a waste of address space. Drivers which has | |
111 | relatively small addressing window (like 64Mib) might run out of | |
112 | virtual space with just a few allocations. | |
113 | ||
114 | With this parameter you can specify the maximum PAGE_SIZE order for | |
115 | DMA IOMMU buffers. Larger buffers will be aligned only to this | |
116 | specified order. The order is expressed as a power of two multiplied | |
117 | by the PAGE_SIZE. | |
118 | ||
119 | endif | |
120 | ||
0b05da72 HUK |
121 | config MIGHT_HAVE_PCI |
122 | bool | |
123 | ||
75e7153a RB |
124 | config SYS_SUPPORTS_APM_EMULATION |
125 | bool | |
126 | ||
bc581770 LW |
127 | config HAVE_TCM |
128 | bool | |
129 | select GENERIC_ALLOCATOR | |
130 | ||
e119bfff RK |
131 | config HAVE_PROC_CPU |
132 | bool | |
133 | ||
ce816fa8 | 134 | config NO_IOPORT_MAP |
5ea81769 | 135 | bool |
5ea81769 | 136 | |
1da177e4 LT |
137 | config EISA |
138 | bool | |
139 | ---help--- | |
140 | The Extended Industry Standard Architecture (EISA) bus was | |
141 | developed as an open alternative to the IBM MicroChannel bus. | |
142 | ||
143 | The EISA bus provided some of the features of the IBM MicroChannel | |
144 | bus while maintaining backward compatibility with cards made for | |
145 | the older ISA bus. The EISA bus saw limited use between 1988 and | |
146 | 1995 when it was made obsolete by the PCI bus. | |
147 | ||
148 | Say Y here if you are building a kernel for an EISA-based machine. | |
149 | ||
150 | Otherwise, say N. | |
151 | ||
152 | config SBUS | |
153 | bool | |
154 | ||
f16fb1ec RK |
155 | config STACKTRACE_SUPPORT |
156 | bool | |
157 | default y | |
158 | ||
f76e9154 NP |
159 | config HAVE_LATENCYTOP_SUPPORT |
160 | bool | |
161 | depends on !SMP | |
162 | default y | |
163 | ||
f16fb1ec RK |
164 | config LOCKDEP_SUPPORT |
165 | bool | |
166 | default y | |
167 | ||
7ad1bcb2 RK |
168 | config TRACE_IRQFLAGS_SUPPORT |
169 | bool | |
170 | default y | |
171 | ||
1da177e4 LT |
172 | config RWSEM_XCHGADD_ALGORITHM |
173 | bool | |
8a87411b | 174 | default y |
1da177e4 | 175 | |
f0d1b0b3 DH |
176 | config ARCH_HAS_ILOG2_U32 |
177 | bool | |
f0d1b0b3 DH |
178 | |
179 | config ARCH_HAS_ILOG2_U64 | |
180 | bool | |
f0d1b0b3 | 181 | |
4a1b5733 EV |
182 | config ARCH_HAS_BANDGAP |
183 | bool | |
184 | ||
b89c3b16 AM |
185 | config GENERIC_HWEIGHT |
186 | bool | |
187 | default y | |
188 | ||
1da177e4 LT |
189 | config GENERIC_CALIBRATE_DELAY |
190 | bool | |
191 | default y | |
192 | ||
a08b6b79 Z |
193 | config ARCH_MAY_HAVE_PC_FDC |
194 | bool | |
195 | ||
5ac6da66 CL |
196 | config ZONE_DMA |
197 | bool | |
5ac6da66 | 198 | |
ccd7ab7f FT |
199 | config NEED_DMA_MAP_STATE |
200 | def_bool y | |
201 | ||
c7edc9e3 DL |
202 | config ARCH_SUPPORTS_UPROBES |
203 | def_bool y | |
204 | ||
58af4a24 RH |
205 | config ARCH_HAS_DMA_SET_COHERENT_MASK |
206 | bool | |
207 | ||
1da177e4 LT |
208 | config GENERIC_ISA_DMA |
209 | bool | |
210 | ||
1da177e4 LT |
211 | config FIQ |
212 | bool | |
213 | ||
13a5045d RH |
214 | config NEED_RET_TO_USER |
215 | bool | |
216 | ||
034d2f5a AV |
217 | config ARCH_MTD_XIP |
218 | bool | |
219 | ||
c760fc19 HC |
220 | config VECTORS_BASE |
221 | hex | |
6afd6fae | 222 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
c760fc19 HC |
223 | default DRAM_BASE if REMAP_VECTORS_TO_RAM |
224 | default 0x00000000 | |
225 | help | |
19accfd3 RK |
226 | The base address of exception vectors. This must be two pages |
227 | in size. | |
c760fc19 | 228 | |
dc21af99 | 229 | config ARM_PATCH_PHYS_VIRT |
c1becedc RK |
230 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
231 | default y | |
b511d75d | 232 | depends on !XIP_KERNEL && MMU |
dc21af99 RK |
233 | depends on !ARCH_REALVIEW || !SPARSEMEM |
234 | help | |
111e9a5c RK |
235 | Patch phys-to-virt and virt-to-phys translation functions at |
236 | boot and module load time according to the position of the | |
237 | kernel in system memory. | |
dc21af99 | 238 | |
111e9a5c | 239 | This can only be used with non-XIP MMU kernels where the base |
daece596 | 240 | of physical memory is at a 16MB boundary. |
dc21af99 | 241 | |
c1becedc RK |
242 | Only disable this option if you know that you do not require |
243 | this feature (eg, building a kernel for a single machine) and | |
244 | you need to shrink the kernel to the minimal size. | |
dc21af99 | 245 | |
c334bc15 RH |
246 | config NEED_MACH_IO_H |
247 | bool | |
248 | help | |
249 | Select this when mach/io.h is required to provide special | |
250 | definitions for this platform. The need for mach/io.h should | |
251 | be avoided when possible. | |
252 | ||
0cdc8b92 | 253 | config NEED_MACH_MEMORY_H |
1b9f95f8 NP |
254 | bool |
255 | help | |
0cdc8b92 NP |
256 | Select this when mach/memory.h is required to provide special |
257 | definitions for this platform. The need for mach/memory.h should | |
258 | be avoided when possible. | |
dc21af99 | 259 | |
1b9f95f8 | 260 | config PHYS_OFFSET |
974c0724 | 261 | hex "Physical address of main memory" if MMU |
c6f54a9b | 262 | depends on !ARM_PATCH_PHYS_VIRT |
974c0724 | 263 | default DRAM_BASE if !MMU |
c6f54a9b UKK |
264 | default 0x00000000 if ARCH_EBSA110 || \ |
265 | EP93XX_SDCE3_SYNC_PHYS_OFFSET || \ | |
266 | ARCH_FOOTBRIDGE || \ | |
267 | ARCH_INTEGRATOR || \ | |
268 | ARCH_IOP13XX || \ | |
269 | ARCH_KS8695 || \ | |
270 | (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) | |
271 | default 0x10000000 if ARCH_OMAP1 || ARCH_RPC | |
272 | default 0x20000000 if ARCH_S5PV210 | |
273 | default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET | |
274 | default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100 | |
275 | default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET | |
276 | default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET | |
277 | default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET | |
111e9a5c | 278 | help |
1b9f95f8 NP |
279 | Please provide the physical address corresponding to the |
280 | location of main memory in your system. | |
cada3c08 | 281 | |
87e040b6 SG |
282 | config GENERIC_BUG |
283 | def_bool y | |
284 | depends on BUG | |
285 | ||
1da177e4 LT |
286 | source "init/Kconfig" |
287 | ||
dc52ddc0 MH |
288 | source "kernel/Kconfig.freezer" |
289 | ||
1da177e4 LT |
290 | menu "System Type" |
291 | ||
3c427975 HC |
292 | config MMU |
293 | bool "MMU-based Paged Memory Management Support" | |
294 | default y | |
295 | help | |
296 | Select if you want MMU-based virtualised addressing space | |
297 | support by paged memory management. If unsure, say 'Y'. | |
298 | ||
ccf50e23 RK |
299 | # |
300 | # The "ARM system type" choice list is ordered alphabetically by option | |
301 | # text. Please add new entries in the option alphabetic order. | |
302 | # | |
1da177e4 LT |
303 | choice |
304 | prompt "ARM system type" | |
1420b22b AB |
305 | default ARCH_VERSATILE if !MMU |
306 | default ARCH_MULTIPLATFORM if MMU | |
1da177e4 | 307 | |
387798b3 RH |
308 | config ARCH_MULTIPLATFORM |
309 | bool "Allow multiple platforms to be selected" | |
b1b3f49c | 310 | depends on MMU |
ddb902cc | 311 | select ARCH_WANT_OPTIONAL_GPIOLIB |
42dc836d | 312 | select ARM_HAS_SG_CHAIN |
387798b3 RH |
313 | select ARM_PATCH_PHYS_VIRT |
314 | select AUTO_ZRELADDR | |
6d0add40 | 315 | select CLKSRC_OF |
66314223 | 316 | select COMMON_CLK |
ddb902cc | 317 | select GENERIC_CLOCKEVENTS |
08d38beb | 318 | select MIGHT_HAVE_PCI |
387798b3 | 319 | select MULTI_IRQ_HANDLER |
66314223 DN |
320 | select SPARSE_IRQ |
321 | select USE_OF | |
66314223 | 322 | |
4af6fee1 DS |
323 | config ARCH_REALVIEW |
324 | bool "ARM Ltd. RealView family" | |
b1b3f49c | 325 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 326 | select ARM_AMBA |
b1b3f49c | 327 | select ARM_TIMER_SP804 |
f9a6aa43 LW |
328 | select COMMON_CLK |
329 | select COMMON_CLK_VERSATILE | |
ae30ceac | 330 | select GENERIC_CLOCKEVENTS |
b56ba8aa | 331 | select GPIO_PL061 if GPIOLIB |
b1b3f49c | 332 | select ICST |
0cdc8b92 | 333 | select NEED_MACH_MEMORY_H |
b1b3f49c | 334 | select PLAT_VERSATILE |
4af6fee1 DS |
335 | help |
336 | This enables support for ARM Ltd RealView boards. | |
337 | ||
338 | config ARCH_VERSATILE | |
339 | bool "ARM Ltd. Versatile family" | |
b1b3f49c | 340 | select ARCH_WANT_OPTIONAL_GPIOLIB |
4af6fee1 | 341 | select ARM_AMBA |
b1b3f49c | 342 | select ARM_TIMER_SP804 |
4af6fee1 | 343 | select ARM_VIC |
6d803ba7 | 344 | select CLKDEV_LOOKUP |
b1b3f49c | 345 | select GENERIC_CLOCKEVENTS |
aa3831cf | 346 | select HAVE_MACH_CLKDEV |
c5a0adb5 | 347 | select ICST |
f4b8b319 | 348 | select PLAT_VERSATILE |
b1b3f49c | 349 | select PLAT_VERSATILE_CLOCK |
2389d501 | 350 | select VERSATILE_FPGA_IRQ |
4af6fee1 DS |
351 | help |
352 | This enables support for ARM Ltd Versatile board. | |
353 | ||
8fc5ffa0 AV |
354 | config ARCH_AT91 |
355 | bool "Atmel AT91" | |
f373e8c0 | 356 | select ARCH_REQUIRE_GPIOLIB |
bd602995 | 357 | select CLKDEV_LOOKUP |
e261501d | 358 | select IRQ_DOMAIN |
1ac02d79 | 359 | select NEED_MACH_IO_H if PCCARD |
6732ae5c JCPV |
360 | select PINCTRL |
361 | select PINCTRL_AT91 if USE_OF | |
4af6fee1 | 362 | help |
929e994f NF |
363 | This enables support for systems based on Atmel |
364 | AT91RM9200 and AT91SAM9* processors. | |
4af6fee1 | 365 | |
93e22567 RK |
366 | config ARCH_CLPS711X |
367 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" | |
a3b8d4a5 | 368 | select ARCH_REQUIRE_GPIOLIB |
ea7d1bc9 | 369 | select AUTO_ZRELADDR |
c99f72ad | 370 | select CLKSRC_MMIO |
93e22567 RK |
371 | select COMMON_CLK |
372 | select CPU_ARM720T | |
4a8355c4 | 373 | select GENERIC_CLOCKEVENTS |
6597619f | 374 | select MFD_SYSCON |
e4e3a37d | 375 | select SOC_BUS |
93e22567 RK |
376 | help |
377 | Support for Cirrus Logic 711x/721x/731x based boards. | |
378 | ||
788c9700 RK |
379 | config ARCH_GEMINI |
380 | bool "Cortina Systems Gemini" | |
788c9700 | 381 | select ARCH_REQUIRE_GPIOLIB |
f3372c01 | 382 | select CLKSRC_MMIO |
b1b3f49c | 383 | select CPU_FA526 |
f3372c01 | 384 | select GENERIC_CLOCKEVENTS |
788c9700 RK |
385 | help |
386 | Support for the Cortina Systems Gemini family SoCs | |
387 | ||
1da177e4 LT |
388 | config ARCH_EBSA110 |
389 | bool "EBSA-110" | |
b1b3f49c | 390 | select ARCH_USES_GETTIMEOFFSET |
c750815e | 391 | select CPU_SA110 |
f7e68bbf | 392 | select ISA |
c334bc15 | 393 | select NEED_MACH_IO_H |
0cdc8b92 | 394 | select NEED_MACH_MEMORY_H |
ce816fa8 | 395 | select NO_IOPORT_MAP |
1da177e4 LT |
396 | help |
397 | This is an evaluation board for the StrongARM processor available | |
f6c8965a | 398 | from Digital. It has limited hardware on-board, including an |
1da177e4 LT |
399 | Ethernet interface, two PCMCIA sockets, two serial ports and a |
400 | parallel port. | |
401 | ||
6d85e2b0 UKK |
402 | config ARCH_EFM32 |
403 | bool "Energy Micro efm32" | |
404 | depends on !MMU | |
405 | select ARCH_REQUIRE_GPIOLIB | |
406 | select ARM_NVIC | |
51aaf81f | 407 | select AUTO_ZRELADDR |
6d85e2b0 UKK |
408 | select CLKSRC_OF |
409 | select COMMON_CLK | |
410 | select CPU_V7M | |
411 | select GENERIC_CLOCKEVENTS | |
412 | select NO_DMA | |
ce816fa8 | 413 | select NO_IOPORT_MAP |
6d85e2b0 UKK |
414 | select SPARSE_IRQ |
415 | select USE_OF | |
416 | help | |
417 | Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko | |
418 | processors. | |
419 | ||
e7736d47 LB |
420 | config ARCH_EP93XX |
421 | bool "EP93xx-based" | |
b1b3f49c RK |
422 | select ARCH_HAS_HOLES_MEMORYMODEL |
423 | select ARCH_REQUIRE_GPIOLIB | |
424 | select ARCH_USES_GETTIMEOFFSET | |
e7736d47 LB |
425 | select ARM_AMBA |
426 | select ARM_VIC | |
6d803ba7 | 427 | select CLKDEV_LOOKUP |
b1b3f49c | 428 | select CPU_ARM920T |
e7736d47 LB |
429 | help |
430 | This enables support for the Cirrus EP93xx series of CPUs. | |
431 | ||
1da177e4 LT |
432 | config ARCH_FOOTBRIDGE |
433 | bool "FootBridge" | |
c750815e | 434 | select CPU_SA110 |
1da177e4 | 435 | select FOOTBRIDGE |
4e8d7637 | 436 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 437 | select HAVE_IDE |
8ef6e620 | 438 | select NEED_MACH_IO_H if !MMU |
0cdc8b92 | 439 | select NEED_MACH_MEMORY_H |
f999b8bd MM |
440 | help |
441 | Support for systems based on the DC21285 companion chip | |
442 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | |
1da177e4 | 443 | |
4af6fee1 DS |
444 | config ARCH_NETX |
445 | bool "Hilscher NetX based" | |
b1b3f49c | 446 | select ARM_VIC |
234b6ced | 447 | select CLKSRC_MMIO |
c750815e | 448 | select CPU_ARM926T |
2fcfe6b8 | 449 | select GENERIC_CLOCKEVENTS |
f999b8bd | 450 | help |
4af6fee1 DS |
451 | This enables support for systems based on the Hilscher NetX Soc |
452 | ||
3b938be6 RK |
453 | config ARCH_IOP13XX |
454 | bool "IOP13xx-based" | |
455 | depends on MMU | |
b1b3f49c | 456 | select CPU_XSC3 |
0cdc8b92 | 457 | select NEED_MACH_MEMORY_H |
13a5045d | 458 | select NEED_RET_TO_USER |
b1b3f49c RK |
459 | select PCI |
460 | select PLAT_IOP | |
461 | select VMSPLIT_1G | |
37ebbcff | 462 | select SPARSE_IRQ |
3b938be6 RK |
463 | help |
464 | Support for Intel's IOP13XX (XScale) family of processors. | |
465 | ||
3f7e5815 LB |
466 | config ARCH_IOP32X |
467 | bool "IOP32x-based" | |
a4f7e763 | 468 | depends on MMU |
b1b3f49c | 469 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 470 | select CPU_XSCALE |
e9004f50 | 471 | select GPIO_IOP |
13a5045d | 472 | select NEED_RET_TO_USER |
f7e68bbf | 473 | select PCI |
b1b3f49c | 474 | select PLAT_IOP |
f999b8bd | 475 | help |
3f7e5815 LB |
476 | Support for Intel's 80219 and IOP32X (XScale) family of |
477 | processors. | |
478 | ||
479 | config ARCH_IOP33X | |
480 | bool "IOP33x-based" | |
481 | depends on MMU | |
b1b3f49c | 482 | select ARCH_REQUIRE_GPIOLIB |
c750815e | 483 | select CPU_XSCALE |
e9004f50 | 484 | select GPIO_IOP |
13a5045d | 485 | select NEED_RET_TO_USER |
3f7e5815 | 486 | select PCI |
b1b3f49c | 487 | select PLAT_IOP |
3f7e5815 LB |
488 | help |
489 | Support for Intel's IOP33X (XScale) family of processors. | |
1da177e4 | 490 | |
3b938be6 RK |
491 | config ARCH_IXP4XX |
492 | bool "IXP4xx-based" | |
a4f7e763 | 493 | depends on MMU |
58af4a24 | 494 | select ARCH_HAS_DMA_SET_COHERENT_MASK |
b1b3f49c | 495 | select ARCH_REQUIRE_GPIOLIB |
51aaf81f | 496 | select ARCH_SUPPORTS_BIG_ENDIAN |
234b6ced | 497 | select CLKSRC_MMIO |
c750815e | 498 | select CPU_XSCALE |
b1b3f49c | 499 | select DMABOUNCE if PCI |
3b938be6 | 500 | select GENERIC_CLOCKEVENTS |
0b05da72 | 501 | select MIGHT_HAVE_PCI |
c334bc15 | 502 | select NEED_MACH_IO_H |
9296d94d | 503 | select USB_EHCI_BIG_ENDIAN_DESC |
171b3f0d | 504 | select USB_EHCI_BIG_ENDIAN_MMIO |
c4713074 | 505 | help |
3b938be6 | 506 | Support for Intel's IXP4XX (XScale) family of processors. |
c4713074 | 507 | |
edabd38e SB |
508 | config ARCH_DOVE |
509 | bool "Marvell Dove" | |
edabd38e | 510 | select ARCH_REQUIRE_GPIOLIB |
756b2531 | 511 | select CPU_PJ4 |
edabd38e | 512 | select GENERIC_CLOCKEVENTS |
0f81bd43 | 513 | select MIGHT_HAVE_PCI |
171b3f0d | 514 | select MVEBU_MBUS |
9139acd1 SH |
515 | select PINCTRL |
516 | select PINCTRL_DOVE | |
abcda1dc | 517 | select PLAT_ORION_LEGACY |
edabd38e SB |
518 | help |
519 | Support for the Marvell Dove SoC 88AP510 | |
520 | ||
794d15b2 SS |
521 | config ARCH_MV78XX0 |
522 | bool "Marvell MV78xx0" | |
a8865655 | 523 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 524 | select CPU_FEROCEON |
794d15b2 | 525 | select GENERIC_CLOCKEVENTS |
171b3f0d | 526 | select MVEBU_MBUS |
b1b3f49c | 527 | select PCI |
abcda1dc | 528 | select PLAT_ORION_LEGACY |
794d15b2 SS |
529 | help |
530 | Support for the following Marvell MV78xx0 series SoCs: | |
531 | MV781x0, MV782x0. | |
532 | ||
9dd0b194 | 533 | config ARCH_ORION5X |
585cf175 TP |
534 | bool "Marvell Orion" |
535 | depends on MMU | |
a8865655 | 536 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 537 | select CPU_FEROCEON |
51cbff1d | 538 | select GENERIC_CLOCKEVENTS |
171b3f0d | 539 | select MVEBU_MBUS |
b1b3f49c | 540 | select PCI |
abcda1dc | 541 | select PLAT_ORION_LEGACY |
585cf175 | 542 | help |
9dd0b194 | 543 | Support for the following Marvell Orion 5x series SoCs: |
d2b2a6bb | 544 | Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), |
d323ade1 | 545 | Orion-2 (5281), Orion-1-90 (6183). |
585cf175 | 546 | |
788c9700 | 547 | config ARCH_MMP |
2f7e8fae | 548 | bool "Marvell PXA168/910/MMP2" |
788c9700 | 549 | depends on MMU |
788c9700 | 550 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 551 | select CLKDEV_LOOKUP |
b1b3f49c | 552 | select GENERIC_ALLOCATOR |
788c9700 | 553 | select GENERIC_CLOCKEVENTS |
157d2644 | 554 | select GPIO_PXA |
c24b3114 | 555 | select IRQ_DOMAIN |
0f374561 | 556 | select MULTI_IRQ_HANDLER |
7c8f86a4 | 557 | select PINCTRL |
788c9700 | 558 | select PLAT_PXA |
0bd86961 | 559 | select SPARSE_IRQ |
788c9700 | 560 | help |
2f7e8fae | 561 | Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. |
788c9700 RK |
562 | |
563 | config ARCH_KS8695 | |
564 | bool "Micrel/Kendin KS8695" | |
98830bc9 | 565 | select ARCH_REQUIRE_GPIOLIB |
c7e783d6 | 566 | select CLKSRC_MMIO |
b1b3f49c | 567 | select CPU_ARM922T |
c7e783d6 | 568 | select GENERIC_CLOCKEVENTS |
b1b3f49c | 569 | select NEED_MACH_MEMORY_H |
788c9700 RK |
570 | help |
571 | Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based | |
572 | System-on-Chip devices. | |
573 | ||
788c9700 RK |
574 | config ARCH_W90X900 |
575 | bool "Nuvoton W90X900 CPU" | |
c52d3d68 | 576 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 577 | select CLKDEV_LOOKUP |
6fa5d5f7 | 578 | select CLKSRC_MMIO |
b1b3f49c | 579 | select CPU_ARM926T |
58b5369e | 580 | select GENERIC_CLOCKEVENTS |
788c9700 | 581 | help |
a8bc4ead | 582 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
583 | At present, the w90x900 has been renamed nuc900, regarding | |
584 | the ARM series product line, you can login the following | |
585 | link address to know more. | |
586 | ||
587 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | |
588 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | |
788c9700 | 589 | |
93e22567 RK |
590 | config ARCH_LPC32XX |
591 | bool "NXP LPC32XX" | |
592 | select ARCH_REQUIRE_GPIOLIB | |
593 | select ARM_AMBA | |
594 | select CLKDEV_LOOKUP | |
595 | select CLKSRC_MMIO | |
596 | select CPU_ARM926T | |
597 | select GENERIC_CLOCKEVENTS | |
598 | select HAVE_IDE | |
93e22567 RK |
599 | select USE_OF |
600 | help | |
601 | Support for the NXP LPC32XX family of processors | |
602 | ||
1da177e4 | 603 | config ARCH_PXA |
2c8086a5 | 604 | bool "PXA2xx/PXA3xx-based" |
a4f7e763 | 605 | depends on MMU |
b1b3f49c RK |
606 | select ARCH_MTD_XIP |
607 | select ARCH_REQUIRE_GPIOLIB | |
608 | select ARM_CPU_SUSPEND if PM | |
609 | select AUTO_ZRELADDR | |
6d803ba7 | 610 | select CLKDEV_LOOKUP |
234b6ced | 611 | select CLKSRC_MMIO |
6f6caeaa | 612 | select CLKSRC_OF |
981d0f39 | 613 | select GENERIC_CLOCKEVENTS |
157d2644 | 614 | select GPIO_PXA |
d0ee9f40 | 615 | select HAVE_IDE |
b1b3f49c | 616 | select MULTI_IRQ_HANDLER |
b1b3f49c RK |
617 | select PLAT_PXA |
618 | select SPARSE_IRQ | |
f999b8bd | 619 | help |
2c8086a5 | 620 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
1da177e4 | 621 | |
8fc1b0f8 KG |
622 | config ARCH_MSM |
623 | bool "Qualcomm MSM (non-multiplatform)" | |
923a081c | 624 | select ARCH_REQUIRE_GPIOLIB |
8cc7f533 | 625 | select COMMON_CLK |
b1b3f49c | 626 | select GENERIC_CLOCKEVENTS |
49cbe786 | 627 | help |
4b53eb4f DW |
628 | Support for Qualcomm MSM/QSD based systems. This runs on the |
629 | apps processor of the MSM/QSD and depends on a shared memory | |
630 | interface to the modem processor which runs the baseband | |
631 | stack and controls some vital subsystems | |
632 | (clock and power control, etc). | |
49cbe786 | 633 | |
bf98c1ea | 634 | config ARCH_SHMOBILE_LEGACY |
0d9fd616 | 635 | bool "Renesas ARM SoCs (non-multiplatform)" |
bf98c1ea | 636 | select ARCH_SHMOBILE |
91942d17 | 637 | select ARM_PATCH_PHYS_VIRT if MMU |
5e93c6b4 | 638 | select CLKDEV_LOOKUP |
0ed82bc9 | 639 | select CPU_V7 |
b1b3f49c | 640 | select GENERIC_CLOCKEVENTS |
4c3ffffd | 641 | select HAVE_ARM_SCU if SMP |
a894fcc2 | 642 | select HAVE_ARM_TWD if SMP |
aa3831cf | 643 | select HAVE_MACH_CLKDEV |
3b55658a | 644 | select HAVE_SMP |
ce5ea9f3 | 645 | select MIGHT_HAVE_CACHE_L2X0 |
60f1435c | 646 | select MULTI_IRQ_HANDLER |
ce816fa8 | 647 | select NO_IOPORT_MAP |
2cd3c927 | 648 | select PINCTRL |
b1b3f49c | 649 | select PM_GENERIC_DOMAINS if PM |
0cdc23df | 650 | select SH_CLK_CPG |
b1b3f49c | 651 | select SPARSE_IRQ |
c793c1b0 | 652 | help |
0d9fd616 LP |
653 | Support for Renesas ARM SoC platforms using a non-multiplatform |
654 | kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car | |
655 | and RZ families. | |
c793c1b0 | 656 | |
1da177e4 LT |
657 | config ARCH_RPC |
658 | bool "RiscPC" | |
659 | select ARCH_ACORN | |
a08b6b79 | 660 | select ARCH_MAY_HAVE_PC_FDC |
07f841b7 | 661 | select ARCH_SPARSEMEM_ENABLE |
5cfc8ee0 | 662 | select ARCH_USES_GETTIMEOFFSET |
fa04e209 | 663 | select CPU_SA110 |
b1b3f49c | 664 | select FIQ |
d0ee9f40 | 665 | select HAVE_IDE |
b1b3f49c RK |
666 | select HAVE_PATA_PLATFORM |
667 | select ISA_DMA_API | |
c334bc15 | 668 | select NEED_MACH_IO_H |
0cdc8b92 | 669 | select NEED_MACH_MEMORY_H |
ce816fa8 | 670 | select NO_IOPORT_MAP |
b4811bac | 671 | select VIRT_TO_BUS |
1da177e4 LT |
672 | help |
673 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | |
674 | CD-ROM interface, serial and parallel port, and the floppy drive. | |
675 | ||
676 | config ARCH_SA1100 | |
677 | bool "SA1100-based" | |
b1b3f49c RK |
678 | select ARCH_MTD_XIP |
679 | select ARCH_REQUIRE_GPIOLIB | |
680 | select ARCH_SPARSEMEM_ENABLE | |
681 | select CLKDEV_LOOKUP | |
682 | select CLKSRC_MMIO | |
1937f5b9 | 683 | select CPU_FREQ |
b1b3f49c | 684 | select CPU_SA1100 |
3e238be2 | 685 | select GENERIC_CLOCKEVENTS |
d0ee9f40 | 686 | select HAVE_IDE |
b1b3f49c | 687 | select ISA |
0cdc8b92 | 688 | select NEED_MACH_MEMORY_H |
375dec92 | 689 | select SPARSE_IRQ |
f999b8bd MM |
690 | help |
691 | Support for StrongARM 11x0 based boards. | |
1da177e4 | 692 | |
b130d5c2 KK |
693 | config ARCH_S3C24XX |
694 | bool "Samsung S3C24XX SoCs" | |
53650430 | 695 | select ARCH_REQUIRE_GPIOLIB |
335cce74 | 696 | select ATAGS |
b1b3f49c | 697 | select CLKDEV_LOOKUP |
4280506a | 698 | select CLKSRC_SAMSUNG_PWM |
7f78b6eb | 699 | select GENERIC_CLOCKEVENTS |
880cf071 | 700 | select GPIO_SAMSUNG |
20676c15 | 701 | select HAVE_S3C2410_I2C if I2C |
b130d5c2 | 702 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
b1b3f49c | 703 | select HAVE_S3C_RTC if RTC_CLASS |
17453dd2 | 704 | select MULTI_IRQ_HANDLER |
c334bc15 | 705 | select NEED_MACH_IO_H |
cd8dc7ae | 706 | select SAMSUNG_ATAGS |
1da177e4 | 707 | help |
b130d5c2 KK |
708 | Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 |
709 | and S3C2450 SoCs based systems, such as the Simtec Electronics BAST | |
710 | (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the | |
711 | Samsung SMDK2410 development board (and derivatives). | |
63b1f51b | 712 | |
a08ab637 BD |
713 | config ARCH_S3C64XX |
714 | bool "Samsung S3C64XX" | |
b1b3f49c | 715 | select ARCH_REQUIRE_GPIOLIB |
1db0287a | 716 | select ARM_AMBA |
89f0ce72 | 717 | select ARM_VIC |
335cce74 | 718 | select ATAGS |
b1b3f49c | 719 | select CLKDEV_LOOKUP |
4280506a | 720 | select CLKSRC_SAMSUNG_PWM |
ccecba3c | 721 | select COMMON_CLK_SAMSUNG |
70bacadb | 722 | select CPU_V6K |
04a49b71 | 723 | select GENERIC_CLOCKEVENTS |
880cf071 | 724 | select GPIO_SAMSUNG |
b1b3f49c RK |
725 | select HAVE_S3C2410_I2C if I2C |
726 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | |
6700397a | 727 | select HAVE_TCM |
ce816fa8 | 728 | select NO_IOPORT_MAP |
b1b3f49c | 729 | select PLAT_SAMSUNG |
4ab75a3f | 730 | select PM_GENERIC_DOMAINS if PM |
b1b3f49c RK |
731 | select S3C_DEV_NAND |
732 | select S3C_GPIO_TRACK | |
cd8dc7ae | 733 | select SAMSUNG_ATAGS |
6e2d9e93 | 734 | select SAMSUNG_WAKEMASK |
88f59738 | 735 | select SAMSUNG_WDT_RESET |
a08ab637 BD |
736 | help |
737 | Samsung S3C64XX series based systems | |
738 | ||
7c6337e2 KH |
739 | config ARCH_DAVINCI |
740 | bool "TI DaVinci" | |
b1b3f49c | 741 | select ARCH_HAS_HOLES_MEMORYMODEL |
dce1115b | 742 | select ARCH_REQUIRE_GPIOLIB |
6d803ba7 | 743 | select CLKDEV_LOOKUP |
20e9969b | 744 | select GENERIC_ALLOCATOR |
b1b3f49c | 745 | select GENERIC_CLOCKEVENTS |
dc7ad3b3 | 746 | select GENERIC_IRQ_CHIP |
b1b3f49c | 747 | select HAVE_IDE |
3ad7a42d | 748 | select TI_PRIV_EDMA |
689e331f | 749 | select USE_OF |
b1b3f49c | 750 | select ZONE_DMA |
7c6337e2 KH |
751 | help |
752 | Support for TI's DaVinci platform. | |
753 | ||
a0694861 TL |
754 | config ARCH_OMAP1 |
755 | bool "TI OMAP1" | |
00a36698 | 756 | depends on MMU |
9af915da | 757 | select ARCH_HAS_HOLES_MEMORYMODEL |
a0694861 | 758 | select ARCH_OMAP |
21f47fbc | 759 | select ARCH_REQUIRE_GPIOLIB |
b1b3f49c | 760 | select CLKDEV_LOOKUP |
d6e15d78 | 761 | select CLKSRC_MMIO |
b1b3f49c | 762 | select GENERIC_CLOCKEVENTS |
a0694861 | 763 | select GENERIC_IRQ_CHIP |
a0694861 TL |
764 | select HAVE_IDE |
765 | select IRQ_DOMAIN | |
766 | select NEED_MACH_IO_H if PCCARD | |
767 | select NEED_MACH_MEMORY_H | |
21f47fbc | 768 | help |
a0694861 | 769 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
02c981c0 | 770 | |
1da177e4 LT |
771 | endchoice |
772 | ||
387798b3 RH |
773 | menu "Multiple platform selection" |
774 | depends on ARCH_MULTIPLATFORM | |
775 | ||
776 | comment "CPU Core family selection" | |
777 | ||
f8afae40 AB |
778 | config ARCH_MULTI_V4 |
779 | bool "ARMv4 based platforms (FA526)" | |
780 | depends on !ARCH_MULTI_V6_V7 | |
781 | select ARCH_MULTI_V4_V5 | |
782 | select CPU_FA526 | |
783 | ||
387798b3 RH |
784 | config ARCH_MULTI_V4T |
785 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" | |
387798b3 | 786 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 787 | select ARCH_MULTI_V4_V5 |
24e860fb AB |
788 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
789 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ | |
790 | CPU_ARM925T || CPU_ARM940T) | |
387798b3 RH |
791 | |
792 | config ARCH_MULTI_V5 | |
793 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" | |
387798b3 | 794 | depends on !ARCH_MULTI_V6_V7 |
b1b3f49c | 795 | select ARCH_MULTI_V4_V5 |
12567bbd | 796 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
24e860fb AB |
797 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
798 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) | |
387798b3 RH |
799 | |
800 | config ARCH_MULTI_V4_V5 | |
801 | bool | |
802 | ||
803 | config ARCH_MULTI_V6 | |
8dda05cc | 804 | bool "ARMv6 based platforms (ARM11)" |
387798b3 | 805 | select ARCH_MULTI_V6_V7 |
42f4754a | 806 | select CPU_V6K |
387798b3 RH |
807 | |
808 | config ARCH_MULTI_V7 | |
8dda05cc | 809 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
387798b3 RH |
810 | default y |
811 | select ARCH_MULTI_V6_V7 | |
b1b3f49c | 812 | select CPU_V7 |
90bc8ac7 | 813 | select HAVE_SMP |
387798b3 RH |
814 | |
815 | config ARCH_MULTI_V6_V7 | |
816 | bool | |
9352b05b | 817 | select MIGHT_HAVE_CACHE_L2X0 |
387798b3 RH |
818 | |
819 | config ARCH_MULTI_CPU_AUTO | |
820 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) | |
821 | select ARCH_MULTI_V5 | |
822 | ||
823 | endmenu | |
824 | ||
05e2a3de RH |
825 | config ARCH_VIRT |
826 | bool "Dummy Virtual Machine" if ARCH_MULTI_V7 | |
4b8b5f25 | 827 | select ARM_AMBA |
05e2a3de | 828 | select ARM_GIC |
05e2a3de | 829 | select ARM_PSCI |
4b8b5f25 | 830 | select HAVE_ARM_ARCH_TIMER |
05e2a3de | 831 | |
ccf50e23 RK |
832 | # |
833 | # This is sorted alphabetically by mach-* pathname. However, plat-* | |
834 | # Kconfigs may be included either alphabetically (according to the | |
835 | # plat- suffix) or along side the corresponding mach-* source. | |
836 | # | |
3e93a22b GC |
837 | source "arch/arm/mach-mvebu/Kconfig" |
838 | ||
d9bfc86d OR |
839 | source "arch/arm/mach-asm9260/Kconfig" |
840 | ||
95b8f20f RK |
841 | source "arch/arm/mach-at91/Kconfig" |
842 | ||
1d22924e AB |
843 | source "arch/arm/mach-axxia/Kconfig" |
844 | ||
8ac49e04 CD |
845 | source "arch/arm/mach-bcm/Kconfig" |
846 | ||
1c37fa10 SH |
847 | source "arch/arm/mach-berlin/Kconfig" |
848 | ||
1da177e4 LT |
849 | source "arch/arm/mach-clps711x/Kconfig" |
850 | ||
d94f944e AV |
851 | source "arch/arm/mach-cns3xxx/Kconfig" |
852 | ||
95b8f20f RK |
853 | source "arch/arm/mach-davinci/Kconfig" |
854 | ||
855 | source "arch/arm/mach-dove/Kconfig" | |
856 | ||
e7736d47 LB |
857 | source "arch/arm/mach-ep93xx/Kconfig" |
858 | ||
1da177e4 LT |
859 | source "arch/arm/mach-footbridge/Kconfig" |
860 | ||
59d3a193 PZ |
861 | source "arch/arm/mach-gemini/Kconfig" |
862 | ||
387798b3 RH |
863 | source "arch/arm/mach-highbank/Kconfig" |
864 | ||
389ee0c2 HZ |
865 | source "arch/arm/mach-hisi/Kconfig" |
866 | ||
1da177e4 LT |
867 | source "arch/arm/mach-integrator/Kconfig" |
868 | ||
3f7e5815 LB |
869 | source "arch/arm/mach-iop32x/Kconfig" |
870 | ||
871 | source "arch/arm/mach-iop33x/Kconfig" | |
1da177e4 | 872 | |
285f5fa7 DW |
873 | source "arch/arm/mach-iop13xx/Kconfig" |
874 | ||
1da177e4 LT |
875 | source "arch/arm/mach-ixp4xx/Kconfig" |
876 | ||
828989ad SS |
877 | source "arch/arm/mach-keystone/Kconfig" |
878 | ||
95b8f20f RK |
879 | source "arch/arm/mach-ks8695/Kconfig" |
880 | ||
3b8f5030 CC |
881 | source "arch/arm/mach-meson/Kconfig" |
882 | ||
95b8f20f RK |
883 | source "arch/arm/mach-msm/Kconfig" |
884 | ||
17723fd3 JJ |
885 | source "arch/arm/mach-moxart/Kconfig" |
886 | ||
794d15b2 SS |
887 | source "arch/arm/mach-mv78xx0/Kconfig" |
888 | ||
3995eb82 | 889 | source "arch/arm/mach-imx/Kconfig" |
1da177e4 | 890 | |
f682a218 MB |
891 | source "arch/arm/mach-mediatek/Kconfig" |
892 | ||
1d3f33d5 SG |
893 | source "arch/arm/mach-mxs/Kconfig" |
894 | ||
95b8f20f | 895 | source "arch/arm/mach-netx/Kconfig" |
49cbe786 | 896 | |
95b8f20f | 897 | source "arch/arm/mach-nomadik/Kconfig" |
95b8f20f | 898 | |
9851ca57 DT |
899 | source "arch/arm/mach-nspire/Kconfig" |
900 | ||
d48af15e TL |
901 | source "arch/arm/plat-omap/Kconfig" |
902 | ||
903 | source "arch/arm/mach-omap1/Kconfig" | |
1da177e4 | 904 | |
1dbae815 TL |
905 | source "arch/arm/mach-omap2/Kconfig" |
906 | ||
9dd0b194 | 907 | source "arch/arm/mach-orion5x/Kconfig" |
585cf175 | 908 | |
387798b3 RH |
909 | source "arch/arm/mach-picoxcell/Kconfig" |
910 | ||
95b8f20f RK |
911 | source "arch/arm/mach-pxa/Kconfig" |
912 | source "arch/arm/plat-pxa/Kconfig" | |
585cf175 | 913 | |
95b8f20f RK |
914 | source "arch/arm/mach-mmp/Kconfig" |
915 | ||
8fc1b0f8 KG |
916 | source "arch/arm/mach-qcom/Kconfig" |
917 | ||
95b8f20f RK |
918 | source "arch/arm/mach-realview/Kconfig" |
919 | ||
d63dc051 HS |
920 | source "arch/arm/mach-rockchip/Kconfig" |
921 | ||
95b8f20f | 922 | source "arch/arm/mach-sa1100/Kconfig" |
edabd38e | 923 | |
387798b3 RH |
924 | source "arch/arm/mach-socfpga/Kconfig" |
925 | ||
a7ed099f | 926 | source "arch/arm/mach-spear/Kconfig" |
a21765a7 | 927 | |
65ebcc11 SK |
928 | source "arch/arm/mach-sti/Kconfig" |
929 | ||
85fd6d63 | 930 | source "arch/arm/mach-s3c24xx/Kconfig" |
1da177e4 | 931 | |
431107ea | 932 | source "arch/arm/mach-s3c64xx/Kconfig" |
a08ab637 | 933 | |
170f4e42 KK |
934 | source "arch/arm/mach-s5pv210/Kconfig" |
935 | ||
83014579 | 936 | source "arch/arm/mach-exynos/Kconfig" |
e509b289 | 937 | source "arch/arm/plat-samsung/Kconfig" |
cc0e72b8 | 938 | |
882d01f9 | 939 | source "arch/arm/mach-shmobile/Kconfig" |
52c543f9 | 940 | |
3b52634f MR |
941 | source "arch/arm/mach-sunxi/Kconfig" |
942 | ||
156a0997 BS |
943 | source "arch/arm/mach-prima2/Kconfig" |
944 | ||
c5f80065 EG |
945 | source "arch/arm/mach-tegra/Kconfig" |
946 | ||
95b8f20f | 947 | source "arch/arm/mach-u300/Kconfig" |
1da177e4 | 948 | |
95b8f20f | 949 | source "arch/arm/mach-ux500/Kconfig" |
1da177e4 LT |
950 | |
951 | source "arch/arm/mach-versatile/Kconfig" | |
952 | ||
ceade897 | 953 | source "arch/arm/mach-vexpress/Kconfig" |
420c34e4 | 954 | source "arch/arm/plat-versatile/Kconfig" |
ceade897 | 955 | |
6f35f9a9 TP |
956 | source "arch/arm/mach-vt8500/Kconfig" |
957 | ||
7ec80ddf | 958 | source "arch/arm/mach-w90x900/Kconfig" |
959 | ||
9a45eb69 JC |
960 | source "arch/arm/mach-zynq/Kconfig" |
961 | ||
1da177e4 LT |
962 | # Definitions to make life easier |
963 | config ARCH_ACORN | |
964 | bool | |
965 | ||
7ae1f7ec LB |
966 | config PLAT_IOP |
967 | bool | |
469d3044 | 968 | select GENERIC_CLOCKEVENTS |
7ae1f7ec | 969 | |
69b02f6a LB |
970 | config PLAT_ORION |
971 | bool | |
bfe45e0b | 972 | select CLKSRC_MMIO |
b1b3f49c | 973 | select COMMON_CLK |
dc7ad3b3 | 974 | select GENERIC_IRQ_CHIP |
278b45b0 | 975 | select IRQ_DOMAIN |
69b02f6a | 976 | |
abcda1dc TP |
977 | config PLAT_ORION_LEGACY |
978 | bool | |
979 | select PLAT_ORION | |
980 | ||
bd5ce433 EM |
981 | config PLAT_PXA |
982 | bool | |
983 | ||
f4b8b319 RK |
984 | config PLAT_VERSATILE |
985 | bool | |
986 | ||
e3887714 RK |
987 | config ARM_TIMER_SP804 |
988 | bool | |
bfe45e0b | 989 | select CLKSRC_MMIO |
7a0eca71 | 990 | select CLKSRC_OF if OF |
e3887714 | 991 | |
d9a1beaa AC |
992 | source "arch/arm/firmware/Kconfig" |
993 | ||
1da177e4 LT |
994 | source arch/arm/mm/Kconfig |
995 | ||
afe4b25e | 996 | config IWMMXT |
d93003e8 SH |
997 | bool "Enable iWMMXt support" |
998 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B | |
999 | default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B | |
afe4b25e LB |
1000 | help |
1001 | Enable support for iWMMXt context switching at run time if | |
1002 | running on a CPU that supports it. | |
1003 | ||
52108641 | 1004 | config MULTI_IRQ_HANDLER |
1005 | bool | |
1006 | help | |
1007 | Allow each machine to specify it's own IRQ handler at run time. | |
1008 | ||
3b93e7b0 HC |
1009 | if !MMU |
1010 | source "arch/arm/Kconfig-nommu" | |
1011 | endif | |
1012 | ||
3e0a07f8 GC |
1013 | config PJ4B_ERRATA_4742 |
1014 | bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" | |
1015 | depends on CPU_PJ4B && MACH_ARMADA_370 | |
1016 | default y | |
1017 | help | |
1018 | When coming out of either a Wait for Interrupt (WFI) or a Wait for | |
1019 | Event (WFE) IDLE states, a specific timing sensitivity exists between | |
1020 | the retiring WFI/WFE instructions and the newly issued subsequent | |
1021 | instructions. This sensitivity can result in a CPU hang scenario. | |
1022 | Workaround: | |
1023 | The software must insert either a Data Synchronization Barrier (DSB) | |
1024 | or Data Memory Barrier (DMB) command immediately after the WFI/WFE | |
1025 | instruction | |
1026 | ||
f0c4b8d6 WD |
1027 | config ARM_ERRATA_326103 |
1028 | bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" | |
1029 | depends on CPU_V6 | |
1030 | help | |
1031 | Executing a SWP instruction to read-only memory does not set bit 11 | |
1032 | of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to | |
1033 | treat the access as a read, preventing a COW from occurring and | |
1034 | causing the faulting task to livelock. | |
1035 | ||
9cba3ccc CM |
1036 | config ARM_ERRATA_411920 |
1037 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | |
e399b1a4 | 1038 | depends on CPU_V6 || CPU_V6K |
9cba3ccc CM |
1039 | help |
1040 | Invalidation of the Instruction Cache operation can | |
1041 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | |
1042 | It does not affect the MPCore. This option enables the ARM Ltd. | |
1043 | recommended workaround. | |
1044 | ||
7ce236fc CM |
1045 | config ARM_ERRATA_430973 |
1046 | bool "ARM errata: Stale prediction on replaced interworking branch" | |
1047 | depends on CPU_V7 | |
1048 | help | |
1049 | This option enables the workaround for the 430973 Cortex-A8 | |
1050 | (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | |
1051 | interworking branch is replaced with another code sequence at the | |
1052 | same virtual address, whether due to self-modifying code or virtual | |
1053 | to physical address re-mapping, Cortex-A8 does not recover from the | |
1054 | stale interworking branch prediction. This results in Cortex-A8 | |
1055 | executing the new code sequence in the incorrect ARM or Thumb state. | |
1056 | The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | |
1057 | and also flushes the branch target cache at every context switch. | |
1058 | Note that setting specific bits in the ACTLR register may not be | |
1059 | available in non-secure mode. | |
1060 | ||
855c551f CM |
1061 | config ARM_ERRATA_458693 |
1062 | bool "ARM errata: Processor deadlock when a false hazard is created" | |
1063 | depends on CPU_V7 | |
62e4d357 | 1064 | depends on !ARCH_MULTIPLATFORM |
855c551f CM |
1065 | help |
1066 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | |
1067 | erratum. For very specific sequences of memory operations, it is | |
1068 | possible for a hazard condition intended for a cache line to instead | |
1069 | be incorrectly associated with a different cache line. This false | |
1070 | hazard might then cause a processor deadlock. The workaround enables | |
1071 | the L1 caching of the NEON accesses and disables the PLD instruction | |
1072 | in the ACTLR register. Note that setting specific bits in the ACTLR | |
1073 | register may not be available in non-secure mode. | |
1074 | ||
0516e464 CM |
1075 | config ARM_ERRATA_460075 |
1076 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | |
1077 | depends on CPU_V7 | |
62e4d357 | 1078 | depends on !ARCH_MULTIPLATFORM |
0516e464 CM |
1079 | help |
1080 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | |
1081 | erratum. Any asynchronous access to the L2 cache may encounter a | |
1082 | situation in which recent store transactions to the L2 cache are lost | |
1083 | and overwritten with stale memory contents from external memory. The | |
1084 | workaround disables the write-allocate mode for the L2 cache via the | |
1085 | ACTLR register. Note that setting specific bits in the ACTLR register | |
1086 | may not be available in non-secure mode. | |
1087 | ||
9f05027c WD |
1088 | config ARM_ERRATA_742230 |
1089 | bool "ARM errata: DMB operation may be faulty" | |
1090 | depends on CPU_V7 && SMP | |
62e4d357 | 1091 | depends on !ARCH_MULTIPLATFORM |
9f05027c WD |
1092 | help |
1093 | This option enables the workaround for the 742230 Cortex-A9 | |
1094 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | |
1095 | between two write operations may not ensure the correct visibility | |
1096 | ordering of the two writes. This workaround sets a specific bit in | |
1097 | the diagnostic register of the Cortex-A9 which causes the DMB | |
1098 | instruction to behave as a DSB, ensuring the correct behaviour of | |
1099 | the two writes. | |
1100 | ||
a672e99b WD |
1101 | config ARM_ERRATA_742231 |
1102 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | |
1103 | depends on CPU_V7 && SMP | |
62e4d357 | 1104 | depends on !ARCH_MULTIPLATFORM |
a672e99b WD |
1105 | help |
1106 | This option enables the workaround for the 742231 Cortex-A9 | |
1107 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | |
1108 | Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, | |
1109 | accessing some data located in the same cache line, may get corrupted | |
1110 | data due to bad handling of the address hazard when the line gets | |
1111 | replaced from one of the CPUs at the same time as another CPU is | |
1112 | accessing it. This workaround sets specific bits in the diagnostic | |
1113 | register of the Cortex-A9 which reduces the linefill issuing | |
1114 | capabilities of the processor. | |
1115 | ||
69155794 JM |
1116 | config ARM_ERRATA_643719 |
1117 | bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" | |
1118 | depends on CPU_V7 && SMP | |
1119 | help | |
1120 | This option enables the workaround for the 643719 Cortex-A9 (prior to | |
1121 | r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR | |
1122 | register returns zero when it should return one. The workaround | |
1123 | corrects this value, ensuring cache maintenance operations which use | |
1124 | it behave as intended and avoiding data corruption. | |
1125 | ||
cdf357f1 WD |
1126 | config ARM_ERRATA_720789 |
1127 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | |
e66dc745 | 1128 | depends on CPU_V7 |
cdf357f1 WD |
1129 | help |
1130 | This option enables the workaround for the 720789 Cortex-A9 (prior to | |
1131 | r2p0) erratum. A faulty ASID can be sent to the other CPUs for the | |
1132 | broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. | |
1133 | As a consequence of this erratum, some TLB entries which should be | |
1134 | invalidated are not, resulting in an incoherency in the system page | |
1135 | tables. The workaround changes the TLB flushing routines to invalidate | |
1136 | entries regardless of the ASID. | |
475d92fc WD |
1137 | |
1138 | config ARM_ERRATA_743622 | |
1139 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | |
1140 | depends on CPU_V7 | |
62e4d357 | 1141 | depends on !ARCH_MULTIPLATFORM |
475d92fc WD |
1142 | help |
1143 | This option enables the workaround for the 743622 Cortex-A9 | |
efbc74ac | 1144 | (r2p*) erratum. Under very rare conditions, a faulty |
475d92fc WD |
1145 | optimisation in the Cortex-A9 Store Buffer may lead to data |
1146 | corruption. This workaround sets a specific bit in the diagnostic | |
1147 | register of the Cortex-A9 which disables the Store Buffer | |
1148 | optimisation, preventing the defect from occurring. This has no | |
1149 | visible impact on the overall performance or power consumption of the | |
1150 | processor. | |
1151 | ||
9a27c27c WD |
1152 | config ARM_ERRATA_751472 |
1153 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | |
ba90c516 | 1154 | depends on CPU_V7 |
62e4d357 | 1155 | depends on !ARCH_MULTIPLATFORM |
9a27c27c WD |
1156 | help |
1157 | This option enables the workaround for the 751472 Cortex-A9 (prior | |
1158 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | |
1159 | completion of a following broadcasted operation if the second | |
1160 | operation is received by a CPU before the ICIALLUIS has completed, | |
1161 | potentially leading to corrupted entries in the cache or TLB. | |
1162 | ||
fcbdc5fe WD |
1163 | config ARM_ERRATA_754322 |
1164 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | |
1165 | depends on CPU_V7 | |
1166 | help | |
1167 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | |
1168 | r3p*) erratum. A speculative memory access may cause a page table walk | |
1169 | which starts prior to an ASID switch but completes afterwards. This | |
1170 | can populate the micro-TLB with a stale entry which may be hit with | |
1171 | the new ASID. This workaround places two dsb instructions in the mm | |
1172 | switching code so that no page table walks can cross the ASID switch. | |
1173 | ||
5dab26af WD |
1174 | config ARM_ERRATA_754327 |
1175 | bool "ARM errata: no automatic Store Buffer drain" | |
1176 | depends on CPU_V7 && SMP | |
1177 | help | |
1178 | This option enables the workaround for the 754327 Cortex-A9 (prior to | |
1179 | r2p0) erratum. The Store Buffer does not have any automatic draining | |
1180 | mechanism and therefore a livelock may occur if an external agent | |
1181 | continuously polls a memory location waiting to observe an update. | |
1182 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | |
1183 | written polling loops from denying visibility of updates to memory. | |
1184 | ||
145e10e1 CM |
1185 | config ARM_ERRATA_364296 |
1186 | bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" | |
fd832478 | 1187 | depends on CPU_V6 |
145e10e1 CM |
1188 | help |
1189 | This options enables the workaround for the 364296 ARM1136 | |
1190 | r0p2 erratum (possible cache data corruption with | |
1191 | hit-under-miss enabled). It sets the undocumented bit 31 in | |
1192 | the auxiliary control register and the FI bit in the control | |
1193 | register, thus disabling hit-under-miss without putting the | |
1194 | processor into full low interrupt latency mode. ARM11MPCore | |
1195 | is not affected. | |
1196 | ||
f630c1bd WD |
1197 | config ARM_ERRATA_764369 |
1198 | bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" | |
1199 | depends on CPU_V7 && SMP | |
1200 | help | |
1201 | This option enables the workaround for erratum 764369 | |
1202 | affecting Cortex-A9 MPCore with two or more processors (all | |
1203 | current revisions). Under certain timing circumstances, a data | |
1204 | cache line maintenance operation by MVA targeting an Inner | |
1205 | Shareable memory region may fail to proceed up to either the | |
1206 | Point of Coherency or to the Point of Unification of the | |
1207 | system. This workaround adds a DSB instruction before the | |
1208 | relevant cache maintenance functions and sets a specific bit | |
1209 | in the diagnostic control register of the SCU. | |
1210 | ||
7253b85c SH |
1211 | config ARM_ERRATA_775420 |
1212 | bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" | |
1213 | depends on CPU_V7 | |
1214 | help | |
1215 | This option enables the workaround for the 775420 Cortex-A9 (r2p2, | |
1216 | r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance | |
1217 | operation aborts with MMU exception, it might cause the processor | |
1218 | to deadlock. This workaround puts DSB before executing ISB if | |
1219 | an abort may occur on cache maintenance. | |
1220 | ||
93dc6887 CM |
1221 | config ARM_ERRATA_798181 |
1222 | bool "ARM errata: TLBI/DSB failure on Cortex-A15" | |
1223 | depends on CPU_V7 && SMP | |
1224 | help | |
1225 | On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not | |
1226 | adequately shooting down all use of the old entries. This | |
1227 | option enables the Linux kernel workaround for this erratum | |
1228 | which sends an IPI to the CPUs that are running the same ASID | |
1229 | as the one being invalidated. | |
1230 | ||
84b6504f WD |
1231 | config ARM_ERRATA_773022 |
1232 | bool "ARM errata: incorrect instructions may be executed from loop buffer" | |
1233 | depends on CPU_V7 | |
1234 | help | |
1235 | This option enables the workaround for the 773022 Cortex-A15 | |
1236 | (up to r0p4) erratum. In certain rare sequences of code, the | |
1237 | loop buffer may deliver incorrect instructions. This | |
1238 | workaround disables the loop buffer to avoid the erratum. | |
1239 | ||
1da177e4 LT |
1240 | endmenu |
1241 | ||
1242 | source "arch/arm/common/Kconfig" | |
1243 | ||
1da177e4 LT |
1244 | menu "Bus support" |
1245 | ||
1246 | config ARM_AMBA | |
1247 | bool | |
1248 | ||
1249 | config ISA | |
1250 | bool | |
1da177e4 LT |
1251 | help |
1252 | Find out whether you have ISA slots on your motherboard. ISA is the | |
1253 | name of a bus system, i.e. the way the CPU talks to the other stuff | |
1254 | inside your box. Other bus systems are PCI, EISA, MicroChannel | |
1255 | (MCA) or VESA. ISA is an older system, now being displaced by PCI; | |
1256 | newer boards don't support it. If you have ISA, say Y, otherwise N. | |
1257 | ||
065909b9 | 1258 | # Select ISA DMA controller support |
1da177e4 LT |
1259 | config ISA_DMA |
1260 | bool | |
065909b9 | 1261 | select ISA_DMA_API |
1da177e4 | 1262 | |
065909b9 | 1263 | # Select ISA DMA interface |
5cae841b AV |
1264 | config ISA_DMA_API |
1265 | bool | |
5cae841b | 1266 | |
1da177e4 | 1267 | config PCI |
0b05da72 | 1268 | bool "PCI support" if MIGHT_HAVE_PCI |
1da177e4 LT |
1269 | help |
1270 | Find out whether you have a PCI motherboard. PCI is the name of a | |
1271 | bus system, i.e. the way the CPU talks to the other stuff inside | |
1272 | your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or | |
1273 | VESA. If you have PCI, say Y, otherwise N. | |
1274 | ||
52882173 AV |
1275 | config PCI_DOMAINS |
1276 | bool | |
1277 | depends on PCI | |
1278 | ||
b080ac8a MRJ |
1279 | config PCI_NANOENGINE |
1280 | bool "BSE nanoEngine PCI support" | |
1281 | depends on SA1100_NANOENGINE | |
1282 | help | |
1283 | Enable PCI on the BSE nanoEngine board. | |
1284 | ||
36e23590 MW |
1285 | config PCI_SYSCALL |
1286 | def_bool PCI | |
1287 | ||
a0113a99 MR |
1288 | config PCI_HOST_ITE8152 |
1289 | bool | |
1290 | depends on PCI && MACH_ARMCORE | |
1291 | default y | |
1292 | select DMABOUNCE | |
1293 | ||
1da177e4 | 1294 | source "drivers/pci/Kconfig" |
3f06d157 | 1295 | source "drivers/pci/pcie/Kconfig" |
1da177e4 LT |
1296 | |
1297 | source "drivers/pcmcia/Kconfig" | |
1298 | ||
1299 | endmenu | |
1300 | ||
1301 | menu "Kernel Features" | |
1302 | ||
3b55658a DM |
1303 | config HAVE_SMP |
1304 | bool | |
1305 | help | |
1306 | This option should be selected by machines which have an SMP- | |
1307 | capable CPU. | |
1308 | ||
1309 | The only effect of this option is to make the SMP-related | |
1310 | options available to the user for configuration. | |
1311 | ||
1da177e4 | 1312 | config SMP |
bb2d8130 | 1313 | bool "Symmetric Multi-Processing" |
fbb4ddac | 1314 | depends on CPU_V6K || CPU_V7 |
bc28248e | 1315 | depends on GENERIC_CLOCKEVENTS |
3b55658a | 1316 | depends on HAVE_SMP |
801bb21c | 1317 | depends on MMU || ARM_MPU |
1da177e4 LT |
1318 | help |
1319 | This enables support for systems with more than one CPU. If you have | |
4a474157 RG |
1320 | a system with only one CPU, say N. If you have a system with more |
1321 | than one CPU, say Y. | |
1da177e4 | 1322 | |
4a474157 | 1323 | If you say N here, the kernel will run on uni- and multiprocessor |
1da177e4 | 1324 | machines, but will use only one CPU of a multiprocessor machine. If |
4a474157 RG |
1325 | you say Y here, the kernel will run on many, but not all, |
1326 | uniprocessor machines. On a uniprocessor machine, the kernel | |
1327 | will run faster if you say N here. | |
1da177e4 | 1328 | |
395cf969 | 1329 | See also <file:Documentation/x86/i386/IO-APIC.txt>, |
1da177e4 | 1330 | <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at |
50a23e6e | 1331 | <http://tldp.org/HOWTO/SMP-HOWTO.html>. |
1da177e4 LT |
1332 | |
1333 | If you don't know what to do here, say N. | |
1334 | ||
f00ec48f RK |
1335 | config SMP_ON_UP |
1336 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | |
801bb21c | 1337 | depends on SMP && !XIP_KERNEL && MMU |
f00ec48f RK |
1338 | default y |
1339 | help | |
1340 | SMP kernels contain instructions which fail on non-SMP processors. | |
1341 | Enabling this option allows the kernel to modify itself to make | |
1342 | these instructions safe. Disabling it allows about 1K of space | |
1343 | savings. | |
1344 | ||
1345 | If you don't know what to do here, say Y. | |
1346 | ||
c9018aab VG |
1347 | config ARM_CPU_TOPOLOGY |
1348 | bool "Support cpu topology definition" | |
1349 | depends on SMP && CPU_V7 | |
1350 | default y | |
1351 | help | |
1352 | Support ARM cpu topology definition. The MPIDR register defines | |
1353 | affinity between processors which is then used to describe the cpu | |
1354 | topology of an ARM System. | |
1355 | ||
1356 | config SCHED_MC | |
1357 | bool "Multi-core scheduler support" | |
1358 | depends on ARM_CPU_TOPOLOGY | |
1359 | help | |
1360 | Multi-core scheduler support improves the CPU scheduler's decision | |
1361 | making when dealing with multi-core CPU chips at a cost of slightly | |
1362 | increased overhead in some places. If unsure say N here. | |
1363 | ||
1364 | config SCHED_SMT | |
1365 | bool "SMT scheduler support" | |
1366 | depends on ARM_CPU_TOPOLOGY | |
1367 | help | |
1368 | Improves the CPU scheduler's decision making when dealing with | |
1369 | MultiThreading at a cost of slightly increased overhead in some | |
1370 | places. If unsure say N here. | |
1371 | ||
a8cbcd92 RK |
1372 | config HAVE_ARM_SCU |
1373 | bool | |
a8cbcd92 RK |
1374 | help |
1375 | This option enables support for the ARM system coherency unit | |
1376 | ||
8a4da6e3 | 1377 | config HAVE_ARM_ARCH_TIMER |
022c03a2 MZ |
1378 | bool "Architected timer support" |
1379 | depends on CPU_V7 | |
8a4da6e3 | 1380 | select ARM_ARCH_TIMER |
0c403462 | 1381 | select GENERIC_CLOCKEVENTS |
022c03a2 MZ |
1382 | help |
1383 | This option enables support for the ARM architected timer | |
1384 | ||
f32f4ce2 RK |
1385 | config HAVE_ARM_TWD |
1386 | bool | |
1387 | depends on SMP | |
da4a686a | 1388 | select CLKSRC_OF if OF |
f32f4ce2 RK |
1389 | help |
1390 | This options enables support for the ARM timer and watchdog unit | |
1391 | ||
e8db288e NP |
1392 | config MCPM |
1393 | bool "Multi-Cluster Power Management" | |
1394 | depends on CPU_V7 && SMP | |
1395 | help | |
1396 | This option provides the common power management infrastructure | |
1397 | for (multi-)cluster based systems, such as big.LITTLE based | |
1398 | systems. | |
1399 | ||
ebf4a5c5 HZ |
1400 | config MCPM_QUAD_CLUSTER |
1401 | bool | |
1402 | depends on MCPM | |
1403 | help | |
1404 | To avoid wasting resources unnecessarily, MCPM only supports up | |
1405 | to 2 clusters by default. | |
1406 | Platforms with 3 or 4 clusters that use MCPM must select this | |
1407 | option to allow the additional clusters to be managed. | |
1408 | ||
1c33be57 NP |
1409 | config BIG_LITTLE |
1410 | bool "big.LITTLE support (Experimental)" | |
1411 | depends on CPU_V7 && SMP | |
1412 | select MCPM | |
1413 | help | |
1414 | This option enables support selections for the big.LITTLE | |
1415 | system architecture. | |
1416 | ||
1417 | config BL_SWITCHER | |
1418 | bool "big.LITTLE switcher support" | |
1419 | depends on BIG_LITTLE && MCPM && HOTPLUG_CPU | |
1c33be57 | 1420 | select ARM_CPU_SUSPEND |
51aaf81f | 1421 | select CPU_PM |
1c33be57 NP |
1422 | help |
1423 | The big.LITTLE "switcher" provides the core functionality to | |
1424 | transparently handle transition between a cluster of A15's | |
1425 | and a cluster of A7's in a big.LITTLE system. | |
1426 | ||
b22537c6 NP |
1427 | config BL_SWITCHER_DUMMY_IF |
1428 | tristate "Simple big.LITTLE switcher user interface" | |
1429 | depends on BL_SWITCHER && DEBUG_KERNEL | |
1430 | help | |
1431 | This is a simple and dummy char dev interface to control | |
1432 | the big.LITTLE switcher core code. It is meant for | |
1433 | debugging purposes only. | |
1434 | ||
8d5796d2 LB |
1435 | choice |
1436 | prompt "Memory split" | |
006fa259 | 1437 | depends on MMU |
8d5796d2 LB |
1438 | default VMSPLIT_3G |
1439 | help | |
1440 | Select the desired split between kernel and user memory. | |
1441 | ||
1442 | If you are not absolutely sure what you are doing, leave this | |
1443 | option alone! | |
1444 | ||
1445 | config VMSPLIT_3G | |
1446 | bool "3G/1G user/kernel split" | |
1447 | config VMSPLIT_2G | |
1448 | bool "2G/2G user/kernel split" | |
1449 | config VMSPLIT_1G | |
1450 | bool "1G/3G user/kernel split" | |
1451 | endchoice | |
1452 | ||
1453 | config PAGE_OFFSET | |
1454 | hex | |
006fa259 | 1455 | default PHYS_OFFSET if !MMU |
8d5796d2 LB |
1456 | default 0x40000000 if VMSPLIT_1G |
1457 | default 0x80000000 if VMSPLIT_2G | |
1458 | default 0xC0000000 | |
1459 | ||
1da177e4 LT |
1460 | config NR_CPUS |
1461 | int "Maximum number of CPUs (2-32)" | |
1462 | range 2 32 | |
1463 | depends on SMP | |
1464 | default "4" | |
1465 | ||
a054a811 | 1466 | config HOTPLUG_CPU |
00b7dede | 1467 | bool "Support for hot-pluggable CPUs" |
40b31360 | 1468 | depends on SMP |
a054a811 RK |
1469 | help |
1470 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1471 | can be controlled through /sys/devices/system/cpu. | |
1472 | ||
2bdd424f WD |
1473 | config ARM_PSCI |
1474 | bool "Support for the ARM Power State Coordination Interface (PSCI)" | |
1475 | depends on CPU_V7 | |
1476 | help | |
1477 | Say Y here if you want Linux to communicate with system firmware | |
1478 | implementing the PSCI specification for CPU-centric power | |
1479 | management operations described in ARM document number ARM DEN | |
1480 | 0022A ("Power State Coordination Interface System Software on | |
1481 | ARM processors"). | |
1482 | ||
2a6ad871 MR |
1483 | # The GPIO number here must be sorted by descending number. In case of |
1484 | # a multiplatform kernel, we just want the highest value required by the | |
1485 | # selected platforms. | |
44986ab0 PDSN |
1486 | config ARCH_NR_GPIO |
1487 | int | |
3dea19e8 | 1488 | default 1024 if ARCH_SHMOBILE || ARCH_TEGRA |
aa42587a TF |
1489 | default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ |
1490 | SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 | |
eb171a99 | 1491 | default 416 if ARCH_SUNXI |
06b851e5 | 1492 | default 392 if ARCH_U8500 |
01bb914c | 1493 | default 352 if ARCH_VT8500 |
7b5da4c3 | 1494 | default 288 if ARCH_ROCKCHIP |
2a6ad871 | 1495 | default 264 if MACH_H4700 |
44986ab0 PDSN |
1496 | default 0 |
1497 | help | |
1498 | Maximum number of GPIOs in the system. | |
1499 | ||
1500 | If unsure, leave the default value. | |
1501 | ||
d45a398f | 1502 | source kernel/Kconfig.preempt |
1da177e4 | 1503 | |
c9218b16 | 1504 | config HZ_FIXED |
f8065813 | 1505 | int |
070b8b43 | 1506 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ |
a73ddc61 | 1507 | ARCH_S5PV210 || ARCH_EXYNOS4 |
5248c657 | 1508 | default AT91_TIMER_HZ if ARCH_AT91 |
bf98c1ea | 1509 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY |
47d84682 | 1510 | default 0 |
c9218b16 RK |
1511 | |
1512 | choice | |
47d84682 | 1513 | depends on HZ_FIXED = 0 |
c9218b16 RK |
1514 | prompt "Timer frequency" |
1515 | ||
1516 | config HZ_100 | |
1517 | bool "100 Hz" | |
1518 | ||
1519 | config HZ_200 | |
1520 | bool "200 Hz" | |
1521 | ||
1522 | config HZ_250 | |
1523 | bool "250 Hz" | |
1524 | ||
1525 | config HZ_300 | |
1526 | bool "300 Hz" | |
1527 | ||
1528 | config HZ_500 | |
1529 | bool "500 Hz" | |
1530 | ||
1531 | config HZ_1000 | |
1532 | bool "1000 Hz" | |
1533 | ||
1534 | endchoice | |
1535 | ||
1536 | config HZ | |
1537 | int | |
47d84682 | 1538 | default HZ_FIXED if HZ_FIXED != 0 |
c9218b16 RK |
1539 | default 100 if HZ_100 |
1540 | default 200 if HZ_200 | |
1541 | default 250 if HZ_250 | |
1542 | default 300 if HZ_300 | |
1543 | default 500 if HZ_500 | |
1544 | default 1000 | |
1545 | ||
1546 | config SCHED_HRTICK | |
1547 | def_bool HIGH_RES_TIMERS | |
f8065813 | 1548 | |
16c79651 | 1549 | config THUMB2_KERNEL |
bc7dea00 | 1550 | bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY |
4477ca45 | 1551 | depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K |
bc7dea00 | 1552 | default y if CPU_THUMBONLY |
16c79651 CM |
1553 | select AEABI |
1554 | select ARM_ASM_UNIFIED | |
89bace65 | 1555 | select ARM_UNWIND |
16c79651 CM |
1556 | help |
1557 | By enabling this option, the kernel will be compiled in | |
1558 | Thumb-2 mode. A compiler/assembler that understand the unified | |
1559 | ARM-Thumb syntax is needed. | |
1560 | ||
1561 | If unsure, say N. | |
1562 | ||
6f685c5c DM |
1563 | config THUMB2_AVOID_R_ARM_THM_JUMP11 |
1564 | bool "Work around buggy Thumb-2 short branch relocations in gas" | |
1565 | depends on THUMB2_KERNEL && MODULES | |
1566 | default y | |
1567 | help | |
1568 | Various binutils versions can resolve Thumb-2 branches to | |
1569 | locally-defined, preemptible global symbols as short-range "b.n" | |
1570 | branch instructions. | |
1571 | ||
1572 | This is a problem, because there's no guarantee the final | |
1573 | destination of the symbol, or any candidate locations for a | |
1574 | trampoline, are within range of the branch. For this reason, the | |
1575 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | |
1576 | relocation in modules at all, and it makes little sense to add | |
1577 | support. | |
1578 | ||
1579 | The symptom is that the kernel fails with an "unsupported | |
1580 | relocation" error when loading some modules. | |
1581 | ||
1582 | Until fixed tools are available, passing | |
1583 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | |
1584 | code which hits this problem, at the cost of a bit of extra runtime | |
1585 | stack usage in some cases. | |
1586 | ||
1587 | The problem is described in more detail at: | |
1588 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | |
1589 | ||
1590 | Only Thumb-2 kernels are affected. | |
1591 | ||
1592 | Unless you are sure your tools don't have this problem, say Y. | |
1593 | ||
0becb088 CM |
1594 | config ARM_ASM_UNIFIED |
1595 | bool | |
1596 | ||
704bdda0 NP |
1597 | config AEABI |
1598 | bool "Use the ARM EABI to compile the kernel" | |
1599 | help | |
1600 | This option allows for the kernel to be compiled using the latest | |
1601 | ARM ABI (aka EABI). This is only useful if you are using a user | |
1602 | space environment that is also compiled with EABI. | |
1603 | ||
1604 | Since there are major incompatibilities between the legacy ABI and | |
1605 | EABI, especially with regard to structure member alignment, this | |
1606 | option also changes the kernel syscall calling convention to | |
1607 | disambiguate both ABIs and allow for backward compatibility support | |
1608 | (selected with CONFIG_OABI_COMPAT). | |
1609 | ||
1610 | To use this you need GCC version 4.0.0 or later. | |
1611 | ||
6c90c872 | 1612 | config OABI_COMPAT |
a73a3ff1 | 1613 | bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" |
d6f94fa0 | 1614 | depends on AEABI && !THUMB2_KERNEL |
6c90c872 NP |
1615 | help |
1616 | This option preserves the old syscall interface along with the | |
1617 | new (ARM EABI) one. It also provides a compatibility layer to | |
1618 | intercept syscalls that have structure arguments which layout | |
1619 | in memory differs between the legacy ABI and the new ARM EABI | |
1620 | (only for non "thumb" binaries). This option adds a tiny | |
1621 | overhead to all syscalls and produces a slightly larger kernel. | |
91702175 KC |
1622 | |
1623 | The seccomp filter system will not be available when this is | |
1624 | selected, since there is no way yet to sensibly distinguish | |
1625 | between calling conventions during filtering. | |
1626 | ||
6c90c872 NP |
1627 | If you know you'll be using only pure EABI user space then you |
1628 | can say N here. If this option is not selected and you attempt | |
1629 | to execute a legacy ABI binary then the result will be | |
1630 | UNPREDICTABLE (in fact it can be predicted that it won't work | |
b02f8467 | 1631 | at all). If in doubt say N. |
6c90c872 | 1632 | |
eb33575c | 1633 | config ARCH_HAS_HOLES_MEMORYMODEL |
e80d6a24 | 1634 | bool |
e80d6a24 | 1635 | |
05944d74 RK |
1636 | config ARCH_SPARSEMEM_ENABLE |
1637 | bool | |
1638 | ||
07a2f737 RK |
1639 | config ARCH_SPARSEMEM_DEFAULT |
1640 | def_bool ARCH_SPARSEMEM_ENABLE | |
1641 | ||
05944d74 | 1642 | config ARCH_SELECT_MEMORY_MODEL |
be370302 | 1643 | def_bool ARCH_SPARSEMEM_ENABLE |
c80d79d7 | 1644 | |
7b7bf499 WD |
1645 | config HAVE_ARCH_PFN_VALID |
1646 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
1647 | ||
b8cd51af SC |
1648 | config HAVE_GENERIC_RCU_GUP |
1649 | def_bool y | |
1650 | depends on ARM_LPAE | |
1651 | ||
053a96ca | 1652 | config HIGHMEM |
e8db89a2 RK |
1653 | bool "High Memory Support" |
1654 | depends on MMU | |
053a96ca NP |
1655 | help |
1656 | The address space of ARM processors is only 4 Gigabytes large | |
1657 | and it has to accommodate user address space, kernel address | |
1658 | space as well as some memory mapped IO. That means that, if you | |
1659 | have a large amount of physical memory and/or IO, not all of the | |
1660 | memory can be "permanently mapped" by the kernel. The physical | |
1661 | memory that is not permanently mapped is called "high memory". | |
1662 | ||
1663 | Depending on the selected kernel/user memory split, minimum | |
1664 | vmalloc space and actual amount of RAM, you may not need this | |
1665 | option which should result in a slightly faster kernel. | |
1666 | ||
1667 | If unsure, say n. | |
1668 | ||
65cec8e3 RK |
1669 | config HIGHPTE |
1670 | bool "Allocate 2nd-level pagetables from highmem" | |
1671 | depends on HIGHMEM | |
65cec8e3 | 1672 | |
1b8873a0 JI |
1673 | config HW_PERF_EVENTS |
1674 | bool "Enable hardware performance counter support for perf events" | |
f0d1bc47 | 1675 | depends on PERF_EVENTS |
1b8873a0 JI |
1676 | default y |
1677 | help | |
1678 | Enable hardware performance counter support for perf events. If | |
1679 | disabled, perf events will use software events only. | |
1680 | ||
1355e2a6 CM |
1681 | config SYS_SUPPORTS_HUGETLBFS |
1682 | def_bool y | |
1683 | depends on ARM_LPAE | |
1684 | ||
8d962507 CM |
1685 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
1686 | def_bool y | |
1687 | depends on ARM_LPAE | |
1688 | ||
4bfab203 SC |
1689 | config ARCH_WANT_GENERAL_HUGETLB |
1690 | def_bool y | |
1691 | ||
3f22ab27 DH |
1692 | source "mm/Kconfig" |
1693 | ||
c1b2d970 | 1694 | config FORCE_MAX_ZONEORDER |
bf98c1ea LP |
1695 | int "Maximum zone order" if ARCH_SHMOBILE_LEGACY |
1696 | range 11 64 if ARCH_SHMOBILE_LEGACY | |
898f08e1 | 1697 | default "12" if SOC_AM33XX |
6d85e2b0 | 1698 | default "9" if SA1111 || ARCH_EFM32 |
c1b2d970 MD |
1699 | default "11" |
1700 | help | |
1701 | The kernel memory allocator divides physically contiguous memory | |
1702 | blocks into "zones", where each zone is a power of two number of | |
1703 | pages. This option selects the largest power of two that the kernel | |
1704 | keeps in the memory allocator. If you need to allocate very large | |
1705 | blocks of physically contiguous memory, then you may need to | |
1706 | increase this value. | |
1707 | ||
1708 | This config option is actually maximum order plus one. For example, | |
1709 | a value of 11 means that the largest free memory block is 2^10 pages. | |
1710 | ||
1da177e4 LT |
1711 | config ALIGNMENT_TRAP |
1712 | bool | |
f12d0d7c | 1713 | depends on CPU_CP15_MMU |
1da177e4 | 1714 | default y if !ARCH_EBSA110 |
e119bfff | 1715 | select HAVE_PROC_CPU if PROC_FS |
1da177e4 | 1716 | help |
84eb8d06 | 1717 | ARM processors cannot fetch/store information which is not |
1da177e4 LT |
1718 | naturally aligned on the bus, i.e., a 4 byte fetch must start at an |
1719 | address divisible by 4. On 32-bit ARM processors, these non-aligned | |
1720 | fetch/store instructions will be emulated in software if you say | |
1721 | here, which has a severe performance impact. This is necessary for | |
1722 | correct operation of some network protocols. With an IP-only | |
1723 | configuration it is safe to say N, otherwise say Y. | |
1724 | ||
39ec58f3 | 1725 | config UACCESS_WITH_MEMCPY |
38ef2ad5 LW |
1726 | bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" |
1727 | depends on MMU | |
39ec58f3 LB |
1728 | default y if CPU_FEROCEON |
1729 | help | |
1730 | Implement faster copy_to_user and clear_user methods for CPU | |
1731 | cores where a 8-word STM instruction give significantly higher | |
1732 | memory write throughput than a sequence of individual 32bit stores. | |
1733 | ||
1734 | A possible side effect is a slight increase in scheduling latency | |
1735 | between threads sharing the same address space if they invoke | |
1736 | such copy operations with large buffers. | |
1737 | ||
1738 | However, if the CPU data cache is using a write-allocate mode, | |
1739 | this option is unlikely to provide any performance gain. | |
1740 | ||
70c70d97 NP |
1741 | config SECCOMP |
1742 | bool | |
1743 | prompt "Enable seccomp to safely compute untrusted bytecode" | |
1744 | ---help--- | |
1745 | This kernel feature is useful for number crunching applications | |
1746 | that may need to compute untrusted bytecode during their | |
1747 | execution. By using pipes or other transports made available to | |
1748 | the process as file descriptors supporting the read/write | |
1749 | syscalls, it's possible to isolate those applications in | |
1750 | their own address space using seccomp. Once seccomp is | |
1751 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
1752 | and the task is only allowed to execute a few safe syscalls | |
1753 | defined by each seccomp mode. | |
1754 | ||
06e6295b SS |
1755 | config SWIOTLB |
1756 | def_bool y | |
1757 | ||
1758 | config IOMMU_HELPER | |
1759 | def_bool SWIOTLB | |
1760 | ||
eff8d644 SS |
1761 | config XEN_DOM0 |
1762 | def_bool y | |
1763 | depends on XEN | |
1764 | ||
1765 | config XEN | |
c2ba1f7d | 1766 | bool "Xen guest support on ARM" |
85323a99 | 1767 | depends on ARM && AEABI && OF |
f880b67d | 1768 | depends on CPU_V7 && !CPU_V6 |
85323a99 | 1769 | depends on !GENERIC_ATOMIC64 |
7693decc | 1770 | depends on MMU |
51aaf81f | 1771 | select ARCH_DMA_ADDR_T_64BIT |
17b7ab80 | 1772 | select ARM_PSCI |
83862ccf | 1773 | select SWIOTLB_XEN |
eff8d644 SS |
1774 | help |
1775 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. | |
1776 | ||
1da177e4 LT |
1777 | endmenu |
1778 | ||
1779 | menu "Boot options" | |
1780 | ||
9eb8f674 GL |
1781 | config USE_OF |
1782 | bool "Flattened Device Tree support" | |
b1b3f49c | 1783 | select IRQ_DOMAIN |
9eb8f674 GL |
1784 | select OF |
1785 | select OF_EARLY_FLATTREE | |
bcedb5f9 | 1786 | select OF_RESERVED_MEM |
9eb8f674 GL |
1787 | help |
1788 | Include support for flattened device tree machine descriptions. | |
1789 | ||
bd51e2f5 NP |
1790 | config ATAGS |
1791 | bool "Support for the traditional ATAGS boot data passing" if USE_OF | |
1792 | default y | |
1793 | help | |
1794 | This is the traditional way of passing data to the kernel at boot | |
1795 | time. If you are solely relying on the flattened device tree (or | |
1796 | the ARM_ATAG_DTB_COMPAT option) then you may unselect this option | |
1797 | to remove ATAGS support from your kernel binary. If unsure, | |
1798 | leave this to y. | |
1799 | ||
1800 | config DEPRECATED_PARAM_STRUCT | |
1801 | bool "Provide old way to pass kernel parameters" | |
1802 | depends on ATAGS | |
1803 | help | |
1804 | This was deprecated in 2001 and announced to live on for 5 years. | |
1805 | Some old boot loaders still use this way. | |
1806 | ||
1da177e4 LT |
1807 | # Compressed boot loader in ROM. Yes, we really want to ask about |
1808 | # TEXT and BSS so we preserve their values in the config files. | |
1809 | config ZBOOT_ROM_TEXT | |
1810 | hex "Compressed ROM boot loader base address" | |
1811 | default "0" | |
1812 | help | |
1813 | The physical address at which the ROM-able zImage is to be | |
1814 | placed in the target. Platforms which normally make use of | |
1815 | ROM-able zImage formats normally set this to a suitable | |
1816 | value in their defconfig file. | |
1817 | ||
1818 | If ZBOOT_ROM is not enabled, this has no effect. | |
1819 | ||
1820 | config ZBOOT_ROM_BSS | |
1821 | hex "Compressed ROM boot loader BSS address" | |
1822 | default "0" | |
1823 | help | |
f8c440b2 DF |
1824 | The base address of an area of read/write memory in the target |
1825 | for the ROM-able zImage which must be available while the | |
1826 | decompressor is running. It must be large enough to hold the | |
1827 | entire decompressed kernel plus an additional 128 KiB. | |
1828 | Platforms which normally make use of ROM-able zImage formats | |
1829 | normally set this to a suitable value in their defconfig file. | |
1da177e4 LT |
1830 | |
1831 | If ZBOOT_ROM is not enabled, this has no effect. | |
1832 | ||
1833 | config ZBOOT_ROM | |
1834 | bool "Compressed boot loader in ROM/flash" | |
1835 | depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS | |
10968131 | 1836 | depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR |
1da177e4 LT |
1837 | help |
1838 | Say Y here if you intend to execute your compressed kernel image | |
1839 | (zImage) directly from ROM or flash. If unsure, say N. | |
1840 | ||
090ab3ff SH |
1841 | choice |
1842 | prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)" | |
d6f94fa0 | 1843 | depends on ZBOOT_ROM && ARCH_SH7372 |
090ab3ff SH |
1844 | default ZBOOT_ROM_NONE |
1845 | help | |
1846 | Include experimental SD/MMC loading code in the ROM-able zImage. | |
59bf8964 | 1847 | With this enabled it is possible to write the ROM-able zImage |
090ab3ff SH |
1848 | kernel image to an MMC or SD card and boot the kernel straight |
1849 | from the reset vector. At reset the processor Mask ROM will load | |
59bf8964 | 1850 | the first part of the ROM-able zImage which in turn loads the |
090ab3ff SH |
1851 | rest the kernel image to RAM. |
1852 | ||
1853 | config ZBOOT_ROM_NONE | |
1854 | bool "No SD/MMC loader in zImage (EXPERIMENTAL)" | |
1855 | help | |
1856 | Do not load image from SD or MMC | |
1857 | ||
f45b1149 SH |
1858 | config ZBOOT_ROM_MMCIF |
1859 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | |
f45b1149 | 1860 | help |
090ab3ff SH |
1861 | Load image from MMCIF hardware block. |
1862 | ||
1863 | config ZBOOT_ROM_SH_MOBILE_SDHI | |
1864 | bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)" | |
1865 | help | |
1866 | Load image from SDHI hardware block | |
1867 | ||
1868 | endchoice | |
f45b1149 | 1869 | |
e2a6a3aa JB |
1870 | config ARM_APPENDED_DTB |
1871 | bool "Use appended device tree blob to zImage (EXPERIMENTAL)" | |
10968131 | 1872 | depends on OF |
e2a6a3aa JB |
1873 | help |
1874 | With this option, the boot code will look for a device tree binary | |
1875 | (DTB) appended to zImage | |
1876 | (e.g. cat zImage <filename>.dtb > zImage_w_dtb). | |
1877 | ||
1878 | This is meant as a backward compatibility convenience for those | |
1879 | systems with a bootloader that can't be upgraded to accommodate | |
1880 | the documented boot protocol using a device tree. | |
1881 | ||
1882 | Beware that there is very little in terms of protection against | |
1883 | this option being confused by leftover garbage in memory that might | |
1884 | look like a DTB header after a reboot if no actual DTB is appended | |
1885 | to zImage. Do not leave this option active in a production kernel | |
1886 | if you don't intend to always append a DTB. Proper passing of the | |
1887 | location into r2 of a bootloader provided DTB is always preferable | |
1888 | to this option. | |
1889 | ||
b90b9a38 NP |
1890 | config ARM_ATAG_DTB_COMPAT |
1891 | bool "Supplement the appended DTB with traditional ATAG information" | |
1892 | depends on ARM_APPENDED_DTB | |
1893 | help | |
1894 | Some old bootloaders can't be updated to a DTB capable one, yet | |
1895 | they provide ATAGs with memory configuration, the ramdisk address, | |
1896 | the kernel cmdline string, etc. Such information is dynamically | |
1897 | provided by the bootloader and can't always be stored in a static | |
1898 | DTB. To allow a device tree enabled kernel to be used with such | |
1899 | bootloaders, this option allows zImage to extract the information | |
1900 | from the ATAG list and store it at run time into the appended DTB. | |
1901 | ||
d0f34a11 GR |
1902 | choice |
1903 | prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT | |
1904 | default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1905 | ||
1906 | config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER | |
1907 | bool "Use bootloader kernel arguments if available" | |
1908 | help | |
1909 | Uses the command-line options passed by the boot loader instead of | |
1910 | the device tree bootargs property. If the boot loader doesn't provide | |
1911 | any, the device tree bootargs property will be used. | |
1912 | ||
1913 | config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND | |
1914 | bool "Extend with bootloader kernel arguments" | |
1915 | help | |
1916 | The command-line arguments provided by the boot loader will be | |
1917 | appended to the the device tree bootargs property. | |
1918 | ||
1919 | endchoice | |
1920 | ||
1da177e4 LT |
1921 | config CMDLINE |
1922 | string "Default kernel command string" | |
1923 | default "" | |
1924 | help | |
1925 | On some architectures (EBSA110 and CATS), there is currently no way | |
1926 | for the boot loader to pass arguments to the kernel. For these | |
1927 | architectures, you should supply some command-line options at build | |
1928 | time by entering them here. As a minimum, you should specify the | |
1929 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | |
1930 | ||
4394c124 VB |
1931 | choice |
1932 | prompt "Kernel command line type" if CMDLINE != "" | |
1933 | default CMDLINE_FROM_BOOTLOADER | |
bd51e2f5 | 1934 | depends on ATAGS |
4394c124 VB |
1935 | |
1936 | config CMDLINE_FROM_BOOTLOADER | |
1937 | bool "Use bootloader kernel arguments if available" | |
1938 | help | |
1939 | Uses the command-line options passed by the boot loader. If | |
1940 | the boot loader doesn't provide any, the default kernel command | |
1941 | string provided in CMDLINE will be used. | |
1942 | ||
1943 | config CMDLINE_EXTEND | |
1944 | bool "Extend bootloader kernel arguments" | |
1945 | help | |
1946 | The command-line arguments provided by the boot loader will be | |
1947 | appended to the default kernel command string. | |
1948 | ||
92d2040d AH |
1949 | config CMDLINE_FORCE |
1950 | bool "Always use the default kernel command string" | |
92d2040d AH |
1951 | help |
1952 | Always use the default kernel command string, even if the boot | |
1953 | loader passes other arguments to the kernel. | |
1954 | This is useful if you cannot or don't want to change the | |
1955 | command-line options your boot loader passes to the kernel. | |
4394c124 | 1956 | endchoice |
92d2040d | 1957 | |
1da177e4 LT |
1958 | config XIP_KERNEL |
1959 | bool "Kernel Execute-In-Place from ROM" | |
10968131 | 1960 | depends on !ARM_LPAE && !ARCH_MULTIPLATFORM |
1da177e4 LT |
1961 | help |
1962 | Execute-In-Place allows the kernel to run from non-volatile storage | |
1963 | directly addressable by the CPU, such as NOR flash. This saves RAM | |
1964 | space since the text section of the kernel is not loaded from flash | |
1965 | to RAM. Read-write sections, such as the data section and stack, | |
1966 | are still copied to RAM. The XIP kernel is not compressed since | |
1967 | it has to run directly from flash, so it will take more space to | |
1968 | store it. The flash address used to link the kernel object files, | |
1969 | and for storing it, is configuration dependent. Therefore, if you | |
1970 | say Y here, you must know the proper physical address where to | |
1971 | store the kernel image depending on your own flash memory usage. | |
1972 | ||
1973 | Also note that the make target becomes "make xipImage" rather than | |
1974 | "make zImage" or "make Image". The final kernel binary to put in | |
1975 | ROM memory will be arch/arm/boot/xipImage. | |
1976 | ||
1977 | If unsure, say N. | |
1978 | ||
1979 | config XIP_PHYS_ADDR | |
1980 | hex "XIP Kernel Physical Location" | |
1981 | depends on XIP_KERNEL | |
1982 | default "0x00080000" | |
1983 | help | |
1984 | This is the physical address in your flash memory the kernel will | |
1985 | be linked for and stored to. This address is dependent on your | |
1986 | own flash usage. | |
1987 | ||
c587e4a6 RP |
1988 | config KEXEC |
1989 | bool "Kexec system call (EXPERIMENTAL)" | |
19ab428f | 1990 | depends on (!SMP || PM_SLEEP_SMP) |
c587e4a6 RP |
1991 | help |
1992 | kexec is a system call that implements the ability to shutdown your | |
1993 | current kernel, and to start another kernel. It is like a reboot | |
01dd2fbf | 1994 | but it is independent of the system firmware. And like a reboot |
c587e4a6 RP |
1995 | you can start any kernel with it, not just Linux. |
1996 | ||
1997 | It is an ongoing process to be certain the hardware in a machine | |
1998 | is properly shutdown, so do not be surprised if this code does not | |
bf220695 | 1999 | initially work for you. |
c587e4a6 | 2000 | |
4cd9d6f7 RP |
2001 | config ATAGS_PROC |
2002 | bool "Export atags in procfs" | |
bd51e2f5 | 2003 | depends on ATAGS && KEXEC |
b98d7291 | 2004 | default y |
4cd9d6f7 RP |
2005 | help |
2006 | Should the atags used to boot the kernel be exported in an "atags" | |
2007 | file in procfs. Useful with kexec. | |
2008 | ||
cb5d39b3 MW |
2009 | config CRASH_DUMP |
2010 | bool "Build kdump crash kernel (EXPERIMENTAL)" | |
cb5d39b3 MW |
2011 | help |
2012 | Generate crash dump after being started by kexec. This should | |
2013 | be normally only set in special crash dump kernels which are | |
2014 | loaded in the main kernel with kexec-tools into a specially | |
2015 | reserved region and then later executed after a crash by | |
2016 | kdump/kexec. The crash dump kernel must be compiled to a | |
2017 | memory address not used by the main kernel | |
2018 | ||
2019 | For more details see Documentation/kdump/kdump.txt | |
2020 | ||
e69edc79 EM |
2021 | config AUTO_ZRELADDR |
2022 | bool "Auto calculation of the decompressed kernel image address" | |
e69edc79 EM |
2023 | help |
2024 | ZRELADDR is the physical address where the decompressed kernel | |
2025 | image will be placed. If AUTO_ZRELADDR is selected, the address | |
2026 | will be determined at run-time by masking the current IP with | |
2027 | 0xf8000000. This assumes the zImage being placed in the first 128MB | |
2028 | from start of memory. | |
2029 | ||
1da177e4 LT |
2030 | endmenu |
2031 | ||
ac9d7efc | 2032 | menu "CPU Power Management" |
1da177e4 | 2033 | |
1da177e4 | 2034 | source "drivers/cpufreq/Kconfig" |
1da177e4 | 2035 | |
ac9d7efc RK |
2036 | source "drivers/cpuidle/Kconfig" |
2037 | ||
2038 | endmenu | |
2039 | ||
1da177e4 LT |
2040 | menu "Floating point emulation" |
2041 | ||
2042 | comment "At least one emulation must be selected" | |
2043 | ||
2044 | config FPE_NWFPE | |
2045 | bool "NWFPE math emulation" | |
593c252a | 2046 | depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL |
1da177e4 LT |
2047 | ---help--- |
2048 | Say Y to include the NWFPE floating point emulator in the kernel. | |
2049 | This is necessary to run most binaries. Linux does not currently | |
2050 | support floating point hardware so you need to say Y here even if | |
2051 | your machine has an FPA or floating point co-processor podule. | |
2052 | ||
2053 | You may say N here if you are going to load the Acorn FPEmulator | |
2054 | early in the bootup. | |
2055 | ||
2056 | config FPE_NWFPE_XP | |
2057 | bool "Support extended precision" | |
bedf142b | 2058 | depends on FPE_NWFPE |
1da177e4 LT |
2059 | help |
2060 | Say Y to include 80-bit support in the kernel floating-point | |
2061 | emulator. Otherwise, only 32 and 64-bit support is compiled in. | |
2062 | Note that gcc does not generate 80-bit operations by default, | |
2063 | so in most cases this option only enlarges the size of the | |
2064 | floating point emulator without any good reason. | |
2065 | ||
2066 | You almost surely want to say N here. | |
2067 | ||
2068 | config FPE_FASTFPE | |
2069 | bool "FastFPE math emulation (EXPERIMENTAL)" | |
d6f94fa0 | 2070 | depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 |
1da177e4 LT |
2071 | ---help--- |
2072 | Say Y here to include the FAST floating point emulator in the kernel. | |
2073 | This is an experimental much faster emulator which now also has full | |
2074 | precision for the mantissa. It does not support any exceptions. | |
2075 | It is very simple, and approximately 3-6 times faster than NWFPE. | |
2076 | ||
2077 | It should be sufficient for most programs. It may be not suitable | |
2078 | for scientific calculations, but you have to check this for yourself. | |
2079 | If you do not feel you need a faster FP emulation you should better | |
2080 | choose NWFPE. | |
2081 | ||
2082 | config VFP | |
2083 | bool "VFP-format floating point maths" | |
e399b1a4 | 2084 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
2085 | help |
2086 | Say Y to include VFP support code in the kernel. This is needed | |
2087 | if your hardware includes a VFP unit. | |
2088 | ||
2089 | Please see <file:Documentation/arm/VFP/release-notes.txt> for | |
2090 | release notes and additional status information. | |
2091 | ||
2092 | Say N if your target does not have VFP hardware. | |
2093 | ||
25ebee02 CM |
2094 | config VFPv3 |
2095 | bool | |
2096 | depends on VFP | |
2097 | default y if CPU_V7 | |
2098 | ||
b5872db4 CM |
2099 | config NEON |
2100 | bool "Advanced SIMD (NEON) Extension support" | |
2101 | depends on VFPv3 && CPU_V7 | |
2102 | help | |
2103 | Say Y to include support code for NEON, the ARMv7 Advanced SIMD | |
2104 | Extension. | |
2105 | ||
73c132c1 AB |
2106 | config KERNEL_MODE_NEON |
2107 | bool "Support for NEON in kernel mode" | |
c4a30c3b | 2108 | depends on NEON && AEABI |
73c132c1 AB |
2109 | help |
2110 | Say Y to include support for NEON in kernel mode. | |
2111 | ||
1da177e4 LT |
2112 | endmenu |
2113 | ||
2114 | menu "Userspace binary formats" | |
2115 | ||
2116 | source "fs/Kconfig.binfmt" | |
2117 | ||
2118 | config ARTHUR | |
2119 | tristate "RISC OS personality" | |
704bdda0 | 2120 | depends on !AEABI |
1da177e4 LT |
2121 | help |
2122 | Say Y here to include the kernel code necessary if you want to run | |
2123 | Acorn RISC OS/Arthur binaries under Linux. This code is still very | |
2124 | experimental; if this sounds frightening, say N and sleep in peace. | |
2125 | You can also say M here to compile this support as a module (which | |
2126 | will be called arthur). | |
2127 | ||
2128 | endmenu | |
2129 | ||
2130 | menu "Power management options" | |
2131 | ||
eceab4ac | 2132 | source "kernel/power/Kconfig" |
1da177e4 | 2133 | |
f4cb5700 | 2134 | config ARCH_SUSPEND_POSSIBLE |
19a0519d | 2135 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
f0d75153 | 2136 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
f4cb5700 JB |
2137 | def_bool y |
2138 | ||
15e0d9e3 AB |
2139 | config ARM_CPU_SUSPEND |
2140 | def_bool PM_SLEEP | |
2141 | ||
603fb42a SC |
2142 | config ARCH_HIBERNATION_POSSIBLE |
2143 | bool | |
2144 | depends on MMU | |
2145 | default y if ARCH_SUSPEND_POSSIBLE | |
2146 | ||
1da177e4 LT |
2147 | endmenu |
2148 | ||
d5950b43 SR |
2149 | source "net/Kconfig" |
2150 | ||
ac25150f | 2151 | source "drivers/Kconfig" |
1da177e4 LT |
2152 | |
2153 | source "fs/Kconfig" | |
2154 | ||
1da177e4 LT |
2155 | source "arch/arm/Kconfig.debug" |
2156 | ||
2157 | source "security/Kconfig" | |
2158 | ||
2159 | source "crypto/Kconfig" | |
2160 | ||
2161 | source "lib/Kconfig" | |
749cf76c CD |
2162 | |
2163 | source "arch/arm/kvm/Kconfig" |