ARM: Kconfig: Introduce MACH_STM32F429 flag
[deliverable/linux.git] / arch / arm / Kconfig
CommitLineData
1da177e4
LT
1config ARM
2 bool
3 default y
b1b3f49c 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
21266be9 5 select ARCH_HAS_DEVMEM_IS_ALLOWED
2b68f6ca 6 select ARCH_HAS_ELF_RANDOMIZE
3d06770e 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
171b3f0d 8 select ARCH_HAVE_CUSTOM_GPIO_H
957e3fac 9 select ARCH_HAS_GCOV_PROFILE_ALL
d7018848 10 select ARCH_MIGHT_HAVE_PC_PARPORT
4badad35 11 select ARCH_SUPPORTS_ATOMIC_RMW
017f161a 12 select ARCH_USE_BUILTIN_BSWAP
0cbad9c9 13 select ARCH_USE_CMPXCHG_LOCKREF
b1b3f49c 14 select ARCH_WANT_IPC_PARSE_VERSION
ee951c63 15 select BUILDTIME_EXTABLE_SORT if MMU
171b3f0d 16 select CLONE_BACKWARDS
b1b3f49c 17 select CPU_PM if (SUSPEND || CPU_IDLE)
dce5c9e3 18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
b01aec9b
BP
19 select EDAC_SUPPORT
20 select EDAC_ATOMIC_SCRUB
36d0fd21 21 select GENERIC_ALLOCATOR
4477ca45 22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
b1b3f49c 23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
2937367b 24 select GENERIC_EARLY_IOREMAP
171b3f0d 25 select GENERIC_IDLE_POLL_SETUP
b1b3f49c
RK
26 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW
7c07005e 28 select GENERIC_IRQ_SHOW_LEVEL
b1b3f49c 29 select GENERIC_PCI_IOMAP
38ff87f7 30 select GENERIC_SCHED_CLOCK
b1b3f49c
RK
31 select GENERIC_SMP_IDLE_THREAD
32 select GENERIC_STRNCPY_FROM_USER
33 select GENERIC_STRNLEN_USER
a71b092a 34 select HANDLE_DOMAIN_IRQ
b1b3f49c 35 select HARDIRQS_SW_RESEND
7a017721 36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
0b7857db 37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
437682ee
AB
38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
e0c25d95 40 select HAVE_ARCH_MMAP_RND_BITS if MMU
91702175 41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
0693bf68 42 select HAVE_ARCH_TRACEHOOK
b329f95d 43 select HAVE_ARM_SMCCC if CPU_V7
b1b3f49c 44 select HAVE_BPF_JIT
51aaf81f 45 select HAVE_CC_STACKPROTECTOR
171b3f0d 46 select HAVE_CONTEXT_TRACKING
b1b3f49c
RK
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_DEBUG_KMEMLEAK
49 select HAVE_DMA_API_DEBUG
b1b3f49c 50 select HAVE_DMA_CONTIGUOUS if MMU
437682ee 51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
dce5c9e3 52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
b1b3f49c 53 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
0e341af8 54 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
b1b3f49c 55 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
1fe53268 56 select HAVE_GENERIC_DMA_COHERENT
b1b3f49c
RK
57 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
58 select HAVE_IDE if PCI || ISA || PCMCIA
87c46b6c 59 select HAVE_IRQ_TIME_ACCOUNTING
e7db7b42 60 select HAVE_KERNEL_GZIP
f9b493ac 61 select HAVE_KERNEL_LZ4
6e8699f7 62 select HAVE_KERNEL_LZMA
b1b3f49c 63 select HAVE_KERNEL_LZO
a7f464f3 64 select HAVE_KERNEL_XZ
cb1293e2 65 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
b1b3f49c
RK
66 select HAVE_KRETPROBES if (HAVE_KPROBES)
67 select HAVE_MEMBLOCK
7d485f64 68 select HAVE_MOD_ARCH_SPECIFIC
b1b3f49c 69 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
0dc016db 70 select HAVE_OPTPROBES if !THUMB2_KERNEL
7ada189f 71 select HAVE_PERF_EVENTS
49863894
WD
72 select HAVE_PERF_REGS
73 select HAVE_PERF_USER_STACK_DUMP
a0ad5496 74 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
e513f8bf 75 select HAVE_REGS_AND_STACK_ACCESS_API
b1b3f49c 76 select HAVE_SYSCALL_TRACEPOINTS
af1839eb 77 select HAVE_UID16
31c1fc81 78 select HAVE_VIRT_CPU_ACCOUNTING_GEN
da0ec6f7 79 select IRQ_FORCED_THREADING
171b3f0d 80 select MODULES_USE_ELF_REL
84f452b1 81 select NO_BOOTMEM
aa7d5f18
AB
82 select OF_EARLY_FLATTREE if OF
83 select OF_RESERVED_MEM if OF
171b3f0d
RK
84 select OLD_SIGACTION
85 select OLD_SIGSUSPEND3
b1b3f49c
RK
86 select PERF_USE_VMALLOC
87 select RTC_LIB
88 select SYS_SUPPORTS_APM_EMULATION
171b3f0d
RK
89 # Above selects are sorted alphabetically; please add new ones
90 # according to that. Thanks.
1da177e4
LT
91 help
92 The ARM series is a line of low-power-consumption RISC chip designs
f6c8965a 93 licensed by ARM Ltd and targeted at embedded applications and
1da177e4 94 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
f6c8965a 95 manufactured, but legacy ARM-based PC hardware remains popular in
1da177e4
LT
96 Europe. There is an ARM Linux project with a web page at
97 <http://www.arm.linux.org.uk/>.
98
74facffe 99config ARM_HAS_SG_CHAIN
308c09f1 100 select ARCH_HAS_SG_CHAIN
74facffe
RK
101 bool
102
4ce63fcd
MS
103config NEED_SG_DMA_LENGTH
104 bool
105
106config ARM_DMA_USE_IOMMU
4ce63fcd 107 bool
b1b3f49c
RK
108 select ARM_HAS_SG_CHAIN
109 select NEED_SG_DMA_LENGTH
4ce63fcd 110
60460abf
SWK
111if ARM_DMA_USE_IOMMU
112
113config ARM_DMA_IOMMU_ALIGNMENT
114 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
115 range 4 9
116 default 8
117 help
118 DMA mapping framework by default aligns all buffers to the smallest
119 PAGE_SIZE order which is greater than or equal to the requested buffer
120 size. This works well for buffers up to a few hundreds kilobytes, but
121 for larger buffers it just a waste of address space. Drivers which has
122 relatively small addressing window (like 64Mib) might run out of
123 virtual space with just a few allocations.
124
125 With this parameter you can specify the maximum PAGE_SIZE order for
126 DMA IOMMU buffers. Larger buffers will be aligned only to this
127 specified order. The order is expressed as a power of two multiplied
128 by the PAGE_SIZE.
129
130endif
131
0b05da72
HUK
132config MIGHT_HAVE_PCI
133 bool
134
75e7153a
RB
135config SYS_SUPPORTS_APM_EMULATION
136 bool
137
bc581770
LW
138config HAVE_TCM
139 bool
140 select GENERIC_ALLOCATOR
141
e119bfff
RK
142config HAVE_PROC_CPU
143 bool
144
ce816fa8 145config NO_IOPORT_MAP
5ea81769 146 bool
5ea81769 147
1da177e4
LT
148config EISA
149 bool
150 ---help---
151 The Extended Industry Standard Architecture (EISA) bus was
152 developed as an open alternative to the IBM MicroChannel bus.
153
154 The EISA bus provided some of the features of the IBM MicroChannel
155 bus while maintaining backward compatibility with cards made for
156 the older ISA bus. The EISA bus saw limited use between 1988 and
157 1995 when it was made obsolete by the PCI bus.
158
159 Say Y here if you are building a kernel for an EISA-based machine.
160
161 Otherwise, say N.
162
163config SBUS
164 bool
165
f16fb1ec
RK
166config STACKTRACE_SUPPORT
167 bool
168 default y
169
170config LOCKDEP_SUPPORT
171 bool
172 default y
173
7ad1bcb2
RK
174config TRACE_IRQFLAGS_SUPPORT
175 bool
cb1293e2 176 default !CPU_V7M
7ad1bcb2 177
1da177e4
LT
178config RWSEM_XCHGADD_ALGORITHM
179 bool
8a87411b 180 default y
1da177e4 181
f0d1b0b3
DH
182config ARCH_HAS_ILOG2_U32
183 bool
f0d1b0b3
DH
184
185config ARCH_HAS_ILOG2_U64
186 bool
f0d1b0b3 187
4a1b5733
EV
188config ARCH_HAS_BANDGAP
189 bool
190
a5f4c561
SA
191config FIX_EARLYCON_MEM
192 def_bool y if MMU
193
b89c3b16
AM
194config GENERIC_HWEIGHT
195 bool
196 default y
197
1da177e4
LT
198config GENERIC_CALIBRATE_DELAY
199 bool
200 default y
201
a08b6b79
Z
202config ARCH_MAY_HAVE_PC_FDC
203 bool
204
5ac6da66
CL
205config ZONE_DMA
206 bool
5ac6da66 207
ccd7ab7f
FT
208config NEED_DMA_MAP_STATE
209 def_bool y
210
c7edc9e3
DL
211config ARCH_SUPPORTS_UPROBES
212 def_bool y
213
58af4a24
RH
214config ARCH_HAS_DMA_SET_COHERENT_MASK
215 bool
216
1da177e4
LT
217config GENERIC_ISA_DMA
218 bool
219
1da177e4
LT
220config FIQ
221 bool
222
13a5045d
RH
223config NEED_RET_TO_USER
224 bool
225
034d2f5a
AV
226config ARCH_MTD_XIP
227 bool
228
c760fc19
HC
229config VECTORS_BASE
230 hex
6afd6fae 231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
c760fc19
HC
232 default DRAM_BASE if REMAP_VECTORS_TO_RAM
233 default 0x00000000
234 help
19accfd3
RK
235 The base address of exception vectors. This must be two pages
236 in size.
c760fc19 237
dc21af99 238config ARM_PATCH_PHYS_VIRT
c1becedc
RK
239 bool "Patch physical to virtual translations at runtime" if EMBEDDED
240 default y
b511d75d 241 depends on !XIP_KERNEL && MMU
dc21af99 242 help
111e9a5c
RK
243 Patch phys-to-virt and virt-to-phys translation functions at
244 boot and module load time according to the position of the
245 kernel in system memory.
dc21af99 246
111e9a5c 247 This can only be used with non-XIP MMU kernels where the base
daece596 248 of physical memory is at a 16MB boundary.
dc21af99 249
c1becedc
RK
250 Only disable this option if you know that you do not require
251 this feature (eg, building a kernel for a single machine) and
252 you need to shrink the kernel to the minimal size.
dc21af99 253
c334bc15
RH
254config NEED_MACH_IO_H
255 bool
256 help
257 Select this when mach/io.h is required to provide special
258 definitions for this platform. The need for mach/io.h should
259 be avoided when possible.
260
0cdc8b92 261config NEED_MACH_MEMORY_H
1b9f95f8
NP
262 bool
263 help
0cdc8b92
NP
264 Select this when mach/memory.h is required to provide special
265 definitions for this platform. The need for mach/memory.h should
266 be avoided when possible.
dc21af99 267
1b9f95f8 268config PHYS_OFFSET
974c0724 269 hex "Physical address of main memory" if MMU
c6f54a9b 270 depends on !ARM_PATCH_PHYS_VIRT
974c0724 271 default DRAM_BASE if !MMU
c6f54a9b 272 default 0x00000000 if ARCH_EBSA110 || \
c6f54a9b
UKK
273 ARCH_FOOTBRIDGE || \
274 ARCH_INTEGRATOR || \
275 ARCH_IOP13XX || \
276 ARCH_KS8695 || \
277 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
278 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
279 default 0x20000000 if ARCH_S5PV210
280 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
b8824c9a 281 default 0xc0000000 if ARCH_SA1100
111e9a5c 282 help
1b9f95f8
NP
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
cada3c08 285
87e040b6
SG
286config GENERIC_BUG
287 def_bool y
288 depends on BUG
289
1bcad26e
KS
290config PGTABLE_LEVELS
291 int
292 default 3 if ARM_LPAE
293 default 2
294
1da177e4
LT
295source "init/Kconfig"
296
dc52ddc0
MH
297source "kernel/Kconfig.freezer"
298
1da177e4
LT
299menu "System Type"
300
3c427975
HC
301config MMU
302 bool "MMU-based Paged Memory Management Support"
303 default y
304 help
305 Select if you want MMU-based virtualised addressing space
306 support by paged memory management. If unsure, say 'Y'.
307
e0c25d95
DC
308config ARCH_MMAP_RND_BITS_MIN
309 default 8
310
311config ARCH_MMAP_RND_BITS_MAX
312 default 14 if PAGE_OFFSET=0x40000000
313 default 15 if PAGE_OFFSET=0x80000000
314 default 16
315
ccf50e23
RK
316#
317# The "ARM system type" choice list is ordered alphabetically by option
318# text. Please add new entries in the option alphabetic order.
319#
1da177e4
LT
320choice
321 prompt "ARM system type"
70722803 322 default ARM_SINGLE_ARMV7M if !MMU
1420b22b 323 default ARCH_MULTIPLATFORM if MMU
1da177e4 324
387798b3
RH
325config ARCH_MULTIPLATFORM
326 bool "Allow multiple platforms to be selected"
b1b3f49c 327 depends on MMU
ddb902cc 328 select ARCH_WANT_OPTIONAL_GPIOLIB
42dc836d 329 select ARM_HAS_SG_CHAIN
387798b3
RH
330 select ARM_PATCH_PHYS_VIRT
331 select AUTO_ZRELADDR
6d0add40 332 select CLKSRC_OF
66314223 333 select COMMON_CLK
ddb902cc 334 select GENERIC_CLOCKEVENTS
08d38beb 335 select MIGHT_HAVE_PCI
387798b3 336 select MULTI_IRQ_HANDLER
66314223
DN
337 select SPARSE_IRQ
338 select USE_OF
66314223 339
9c77bc43
SA
340config ARM_SINGLE_ARMV7M
341 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
342 depends on !MMU
343 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_NVIC
499f1640 345 select AUTO_ZRELADDR
9c77bc43
SA
346 select CLKSRC_OF
347 select COMMON_CLK
348 select CPU_V7M
349 select GENERIC_CLOCKEVENTS
350 select NO_IOPORT_MAP
351 select SPARSE_IRQ
352 select USE_OF
353
4af6fee1 354
93e22567
RK
355config ARCH_CLPS711X
356 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
a3b8d4a5 357 select ARCH_REQUIRE_GPIOLIB
ea7d1bc9 358 select AUTO_ZRELADDR
c99f72ad 359 select CLKSRC_MMIO
93e22567
RK
360 select COMMON_CLK
361 select CPU_ARM720T
4a8355c4 362 select GENERIC_CLOCKEVENTS
6597619f 363 select MFD_SYSCON
e4e3a37d 364 select SOC_BUS
93e22567
RK
365 help
366 Support for Cirrus Logic 711x/721x/731x based boards.
367
788c9700
RK
368config ARCH_GEMINI
369 bool "Cortina Systems Gemini"
788c9700 370 select ARCH_REQUIRE_GPIOLIB
f3372c01 371 select CLKSRC_MMIO
b1b3f49c 372 select CPU_FA526
f3372c01 373 select GENERIC_CLOCKEVENTS
788c9700
RK
374 help
375 Support for the Cortina Systems Gemini family SoCs
376
1da177e4
LT
377config ARCH_EBSA110
378 bool "EBSA-110"
b1b3f49c 379 select ARCH_USES_GETTIMEOFFSET
c750815e 380 select CPU_SA110
f7e68bbf 381 select ISA
c334bc15 382 select NEED_MACH_IO_H
0cdc8b92 383 select NEED_MACH_MEMORY_H
ce816fa8 384 select NO_IOPORT_MAP
1da177e4
LT
385 help
386 This is an evaluation board for the StrongARM processor available
f6c8965a 387 from Digital. It has limited hardware on-board, including an
1da177e4
LT
388 Ethernet interface, two PCMCIA sockets, two serial ports and a
389 parallel port.
390
e7736d47
LB
391config ARCH_EP93XX
392 bool "EP93xx-based"
b1b3f49c
RK
393 select ARCH_HAS_HOLES_MEMORYMODEL
394 select ARCH_REQUIRE_GPIOLIB
e7736d47 395 select ARM_AMBA
b8824c9a 396 select ARM_PATCH_PHYS_VIRT
e7736d47 397 select ARM_VIC
b8824c9a 398 select AUTO_ZRELADDR
6d803ba7 399 select CLKDEV_LOOKUP
000bc178 400 select CLKSRC_MMIO
b1b3f49c 401 select CPU_ARM920T
000bc178 402 select GENERIC_CLOCKEVENTS
e7736d47
LB
403 help
404 This enables support for the Cirrus EP93xx series of CPUs.
405
1da177e4
LT
406config ARCH_FOOTBRIDGE
407 bool "FootBridge"
c750815e 408 select CPU_SA110
1da177e4 409 select FOOTBRIDGE
4e8d7637 410 select GENERIC_CLOCKEVENTS
d0ee9f40 411 select HAVE_IDE
8ef6e620 412 select NEED_MACH_IO_H if !MMU
0cdc8b92 413 select NEED_MACH_MEMORY_H
f999b8bd
MM
414 help
415 Support for systems based on the DC21285 companion chip
416 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
1da177e4 417
4af6fee1
DS
418config ARCH_NETX
419 bool "Hilscher NetX based"
b1b3f49c 420 select ARM_VIC
234b6ced 421 select CLKSRC_MMIO
c750815e 422 select CPU_ARM926T
2fcfe6b8 423 select GENERIC_CLOCKEVENTS
f999b8bd 424 help
4af6fee1
DS
425 This enables support for systems based on the Hilscher NetX Soc
426
3b938be6
RK
427config ARCH_IOP13XX
428 bool "IOP13xx-based"
429 depends on MMU
b1b3f49c 430 select CPU_XSC3
0cdc8b92 431 select NEED_MACH_MEMORY_H
13a5045d 432 select NEED_RET_TO_USER
b1b3f49c
RK
433 select PCI
434 select PLAT_IOP
435 select VMSPLIT_1G
37ebbcff 436 select SPARSE_IRQ
3b938be6
RK
437 help
438 Support for Intel's IOP13XX (XScale) family of processors.
439
3f7e5815
LB
440config ARCH_IOP32X
441 bool "IOP32x-based"
a4f7e763 442 depends on MMU
b1b3f49c 443 select ARCH_REQUIRE_GPIOLIB
c750815e 444 select CPU_XSCALE
e9004f50 445 select GPIO_IOP
13a5045d 446 select NEED_RET_TO_USER
f7e68bbf 447 select PCI
b1b3f49c 448 select PLAT_IOP
f999b8bd 449 help
3f7e5815
LB
450 Support for Intel's 80219 and IOP32X (XScale) family of
451 processors.
452
453config ARCH_IOP33X
454 bool "IOP33x-based"
455 depends on MMU
b1b3f49c 456 select ARCH_REQUIRE_GPIOLIB
c750815e 457 select CPU_XSCALE
e9004f50 458 select GPIO_IOP
13a5045d 459 select NEED_RET_TO_USER
3f7e5815 460 select PCI
b1b3f49c 461 select PLAT_IOP
3f7e5815
LB
462 help
463 Support for Intel's IOP33X (XScale) family of processors.
1da177e4 464
3b938be6
RK
465config ARCH_IXP4XX
466 bool "IXP4xx-based"
a4f7e763 467 depends on MMU
58af4a24 468 select ARCH_HAS_DMA_SET_COHERENT_MASK
b1b3f49c 469 select ARCH_REQUIRE_GPIOLIB
51aaf81f 470 select ARCH_SUPPORTS_BIG_ENDIAN
234b6ced 471 select CLKSRC_MMIO
c750815e 472 select CPU_XSCALE
b1b3f49c 473 select DMABOUNCE if PCI
3b938be6 474 select GENERIC_CLOCKEVENTS
0b05da72 475 select MIGHT_HAVE_PCI
c334bc15 476 select NEED_MACH_IO_H
9296d94d 477 select USB_EHCI_BIG_ENDIAN_DESC
171b3f0d 478 select USB_EHCI_BIG_ENDIAN_MMIO
c4713074 479 help
3b938be6 480 Support for Intel's IXP4XX (XScale) family of processors.
c4713074 481
edabd38e
SB
482config ARCH_DOVE
483 bool "Marvell Dove"
edabd38e 484 select ARCH_REQUIRE_GPIOLIB
756b2531 485 select CPU_PJ4
edabd38e 486 select GENERIC_CLOCKEVENTS
0f81bd43 487 select MIGHT_HAVE_PCI
b8cd337c 488 select MULTI_IRQ_HANDLER
171b3f0d 489 select MVEBU_MBUS
9139acd1
SH
490 select PINCTRL
491 select PINCTRL_DOVE
abcda1dc 492 select PLAT_ORION_LEGACY
0bd86961 493 select SPARSE_IRQ
c5d431e8 494 select PM_GENERIC_DOMAINS if PM
788c9700 495 help
edabd38e 496 Support for the Marvell Dove SoC 88AP510
788c9700
RK
497
498config ARCH_KS8695
499 bool "Micrel/Kendin KS8695"
98830bc9 500 select ARCH_REQUIRE_GPIOLIB
c7e783d6 501 select CLKSRC_MMIO
b1b3f49c 502 select CPU_ARM922T
c7e783d6 503 select GENERIC_CLOCKEVENTS
b1b3f49c 504 select NEED_MACH_MEMORY_H
788c9700
RK
505 help
506 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
507 System-on-Chip devices.
508
788c9700
RK
509config ARCH_W90X900
510 bool "Nuvoton W90X900 CPU"
c52d3d68 511 select ARCH_REQUIRE_GPIOLIB
6d803ba7 512 select CLKDEV_LOOKUP
6fa5d5f7 513 select CLKSRC_MMIO
b1b3f49c 514 select CPU_ARM926T
58b5369e 515 select GENERIC_CLOCKEVENTS
788c9700 516 help
a8bc4ead 517 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
518 At present, the w90x900 has been renamed nuc900, regarding
519 the ARM series product line, you can login the following
520 link address to know more.
521
522 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
523 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
788c9700 524
93e22567
RK
525config ARCH_LPC32XX
526 bool "NXP LPC32XX"
527 select ARCH_REQUIRE_GPIOLIB
528 select ARM_AMBA
529 select CLKDEV_LOOKUP
530 select CLKSRC_MMIO
531 select CPU_ARM926T
532 select GENERIC_CLOCKEVENTS
533 select HAVE_IDE
93e22567
RK
534 select USE_OF
535 help
536 Support for the NXP LPC32XX family of processors
537
1da177e4 538config ARCH_PXA
2c8086a5 539 bool "PXA2xx/PXA3xx-based"
a4f7e763 540 depends on MMU
b1b3f49c
RK
541 select ARCH_MTD_XIP
542 select ARCH_REQUIRE_GPIOLIB
543 select ARM_CPU_SUSPEND if PM
544 select AUTO_ZRELADDR
a1c0a6ad 545 select COMMON_CLK
6d803ba7 546 select CLKDEV_LOOKUP
389d9b58 547 select CLKSRC_PXA
234b6ced 548 select CLKSRC_MMIO
6f6caeaa 549 select CLKSRC_OF
981d0f39 550 select GENERIC_CLOCKEVENTS
157d2644 551 select GPIO_PXA
d0ee9f40 552 select HAVE_IDE
d6cf30ca 553 select IRQ_DOMAIN
b1b3f49c 554 select MULTI_IRQ_HANDLER
b1b3f49c
RK
555 select PLAT_PXA
556 select SPARSE_IRQ
f999b8bd 557 help
2c8086a5 558 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
1da177e4
LT
559
560config ARCH_RPC
561 bool "RiscPC"
868e87cc 562 depends on MMU
1da177e4 563 select ARCH_ACORN
a08b6b79 564 select ARCH_MAY_HAVE_PC_FDC
07f841b7 565 select ARCH_SPARSEMEM_ENABLE
5cfc8ee0 566 select ARCH_USES_GETTIMEOFFSET
fa04e209 567 select CPU_SA110
b1b3f49c 568 select FIQ
d0ee9f40 569 select HAVE_IDE
b1b3f49c
RK
570 select HAVE_PATA_PLATFORM
571 select ISA_DMA_API
c334bc15 572 select NEED_MACH_IO_H
0cdc8b92 573 select NEED_MACH_MEMORY_H
ce816fa8 574 select NO_IOPORT_MAP
b4811bac 575 select VIRT_TO_BUS
1da177e4
LT
576 help
577 On the Acorn Risc-PC, Linux can support the internal IDE disk and
578 CD-ROM interface, serial and parallel port, and the floppy drive.
579
580config ARCH_SA1100
581 bool "SA1100-based"
b1b3f49c
RK
582 select ARCH_MTD_XIP
583 select ARCH_REQUIRE_GPIOLIB
584 select ARCH_SPARSEMEM_ENABLE
585 select CLKDEV_LOOKUP
586 select CLKSRC_MMIO
389d9b58
DL
587 select CLKSRC_PXA
588 select CLKSRC_OF if OF
1937f5b9 589 select CPU_FREQ
b1b3f49c 590 select CPU_SA1100
3e238be2 591 select GENERIC_CLOCKEVENTS
d0ee9f40 592 select HAVE_IDE
1eca42b4 593 select IRQ_DOMAIN
b1b3f49c 594 select ISA
affcab32 595 select MULTI_IRQ_HANDLER
0cdc8b92 596 select NEED_MACH_MEMORY_H
375dec92 597 select SPARSE_IRQ
f999b8bd
MM
598 help
599 Support for StrongARM 11x0 based boards.
1da177e4 600
b130d5c2
KK
601config ARCH_S3C24XX
602 bool "Samsung S3C24XX SoCs"
53650430 603 select ARCH_REQUIRE_GPIOLIB
335cce74 604 select ATAGS
b1b3f49c 605 select CLKDEV_LOOKUP
4280506a 606 select CLKSRC_SAMSUNG_PWM
7f78b6eb 607 select GENERIC_CLOCKEVENTS
880cf071 608 select GPIO_SAMSUNG
20676c15 609 select HAVE_S3C2410_I2C if I2C
b130d5c2 610 select HAVE_S3C2410_WATCHDOG if WATCHDOG
b1b3f49c 611 select HAVE_S3C_RTC if RTC_CLASS
17453dd2 612 select MULTI_IRQ_HANDLER
c334bc15 613 select NEED_MACH_IO_H
cd8dc7ae 614 select SAMSUNG_ATAGS
1da177e4 615 help
b130d5c2
KK
616 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
617 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
618 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
619 Samsung SMDK2410 development board (and derivatives).
63b1f51b 620
7c6337e2
KH
621config ARCH_DAVINCI
622 bool "TI DaVinci"
b1b3f49c 623 select ARCH_HAS_HOLES_MEMORYMODEL
dce1115b 624 select ARCH_REQUIRE_GPIOLIB
6d803ba7 625 select CLKDEV_LOOKUP
20e9969b 626 select GENERIC_ALLOCATOR
b1b3f49c 627 select GENERIC_CLOCKEVENTS
dc7ad3b3 628 select GENERIC_IRQ_CHIP
b1b3f49c 629 select HAVE_IDE
689e331f 630 select USE_OF
b1b3f49c 631 select ZONE_DMA
7c6337e2
KH
632 help
633 Support for TI's DaVinci platform.
634
a0694861
TL
635config ARCH_OMAP1
636 bool "TI OMAP1"
00a36698 637 depends on MMU
9af915da 638 select ARCH_HAS_HOLES_MEMORYMODEL
a0694861 639 select ARCH_OMAP
21f47fbc 640 select ARCH_REQUIRE_GPIOLIB
b1b3f49c 641 select CLKDEV_LOOKUP
d6e15d78 642 select CLKSRC_MMIO
b1b3f49c 643 select GENERIC_CLOCKEVENTS
a0694861 644 select GENERIC_IRQ_CHIP
a0694861
TL
645 select HAVE_IDE
646 select IRQ_DOMAIN
b694331c 647 select MULTI_IRQ_HANDLER
a0694861
TL
648 select NEED_MACH_IO_H if PCCARD
649 select NEED_MACH_MEMORY_H
685e2d08 650 select SPARSE_IRQ
21f47fbc 651 help
a0694861 652 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
02c981c0 653
1da177e4
LT
654endchoice
655
387798b3
RH
656menu "Multiple platform selection"
657 depends on ARCH_MULTIPLATFORM
658
659comment "CPU Core family selection"
660
f8afae40
AB
661config ARCH_MULTI_V4
662 bool "ARMv4 based platforms (FA526)"
663 depends on !ARCH_MULTI_V6_V7
664 select ARCH_MULTI_V4_V5
665 select CPU_FA526
666
387798b3
RH
667config ARCH_MULTI_V4T
668 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
387798b3 669 depends on !ARCH_MULTI_V6_V7
b1b3f49c 670 select ARCH_MULTI_V4_V5
24e860fb
AB
671 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
672 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
673 CPU_ARM925T || CPU_ARM940T)
387798b3
RH
674
675config ARCH_MULTI_V5
676 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
387798b3 677 depends on !ARCH_MULTI_V6_V7
b1b3f49c 678 select ARCH_MULTI_V4_V5
12567bbd 679 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
24e860fb
AB
680 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
681 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
387798b3
RH
682
683config ARCH_MULTI_V4_V5
684 bool
685
686config ARCH_MULTI_V6
8dda05cc 687 bool "ARMv6 based platforms (ARM11)"
387798b3 688 select ARCH_MULTI_V6_V7
42f4754a 689 select CPU_V6K
387798b3
RH
690
691config ARCH_MULTI_V7
8dda05cc 692 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
387798b3
RH
693 default y
694 select ARCH_MULTI_V6_V7
b1b3f49c 695 select CPU_V7
90bc8ac7 696 select HAVE_SMP
387798b3
RH
697
698config ARCH_MULTI_V6_V7
699 bool
9352b05b 700 select MIGHT_HAVE_CACHE_L2X0
387798b3
RH
701
702config ARCH_MULTI_CPU_AUTO
703 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
704 select ARCH_MULTI_V5
705
706endmenu
707
05e2a3de 708config ARCH_VIRT
e3246542
MY
709 bool "Dummy Virtual Machine"
710 depends on ARCH_MULTI_V7
4b8b5f25 711 select ARM_AMBA
05e2a3de 712 select ARM_GIC
0e2f91e9 713 select ARM_GIC_V2M if PCI_MSI
0b28f1db 714 select ARM_GIC_V3
05e2a3de 715 select ARM_PSCI
4b8b5f25 716 select HAVE_ARM_ARCH_TIMER
05e2a3de 717
ccf50e23
RK
718#
719# This is sorted alphabetically by mach-* pathname. However, plat-*
720# Kconfigs may be included either alphabetically (according to the
721# plat- suffix) or along side the corresponding mach-* source.
722#
3e93a22b
GC
723source "arch/arm/mach-mvebu/Kconfig"
724
445d9b30
TZ
725source "arch/arm/mach-alpine/Kconfig"
726
d9bfc86d
OR
727source "arch/arm/mach-asm9260/Kconfig"
728
95b8f20f
RK
729source "arch/arm/mach-at91/Kconfig"
730
1d22924e
AB
731source "arch/arm/mach-axxia/Kconfig"
732
8ac49e04
CD
733source "arch/arm/mach-bcm/Kconfig"
734
1c37fa10
SH
735source "arch/arm/mach-berlin/Kconfig"
736
1da177e4
LT
737source "arch/arm/mach-clps711x/Kconfig"
738
d94f944e
AV
739source "arch/arm/mach-cns3xxx/Kconfig"
740
95b8f20f
RK
741source "arch/arm/mach-davinci/Kconfig"
742
df8d742e
BS
743source "arch/arm/mach-digicolor/Kconfig"
744
95b8f20f
RK
745source "arch/arm/mach-dove/Kconfig"
746
e7736d47
LB
747source "arch/arm/mach-ep93xx/Kconfig"
748
1da177e4
LT
749source "arch/arm/mach-footbridge/Kconfig"
750
59d3a193
PZ
751source "arch/arm/mach-gemini/Kconfig"
752
387798b3
RH
753source "arch/arm/mach-highbank/Kconfig"
754
389ee0c2
HZ
755source "arch/arm/mach-hisi/Kconfig"
756
1da177e4
LT
757source "arch/arm/mach-integrator/Kconfig"
758
3f7e5815
LB
759source "arch/arm/mach-iop32x/Kconfig"
760
761source "arch/arm/mach-iop33x/Kconfig"
1da177e4 762
285f5fa7
DW
763source "arch/arm/mach-iop13xx/Kconfig"
764
1da177e4
LT
765source "arch/arm/mach-ixp4xx/Kconfig"
766
828989ad
SS
767source "arch/arm/mach-keystone/Kconfig"
768
95b8f20f
RK
769source "arch/arm/mach-ks8695/Kconfig"
770
3b8f5030
CC
771source "arch/arm/mach-meson/Kconfig"
772
17723fd3
JJ
773source "arch/arm/mach-moxart/Kconfig"
774
794d15b2
SS
775source "arch/arm/mach-mv78xx0/Kconfig"
776
3995eb82 777source "arch/arm/mach-imx/Kconfig"
1da177e4 778
f682a218
MB
779source "arch/arm/mach-mediatek/Kconfig"
780
1d3f33d5
SG
781source "arch/arm/mach-mxs/Kconfig"
782
95b8f20f 783source "arch/arm/mach-netx/Kconfig"
49cbe786 784
95b8f20f 785source "arch/arm/mach-nomadik/Kconfig"
95b8f20f 786
9851ca57
DT
787source "arch/arm/mach-nspire/Kconfig"
788
d48af15e
TL
789source "arch/arm/plat-omap/Kconfig"
790
791source "arch/arm/mach-omap1/Kconfig"
1da177e4 792
1dbae815
TL
793source "arch/arm/mach-omap2/Kconfig"
794
9dd0b194 795source "arch/arm/mach-orion5x/Kconfig"
585cf175 796
387798b3
RH
797source "arch/arm/mach-picoxcell/Kconfig"
798
95b8f20f
RK
799source "arch/arm/mach-pxa/Kconfig"
800source "arch/arm/plat-pxa/Kconfig"
585cf175 801
95b8f20f
RK
802source "arch/arm/mach-mmp/Kconfig"
803
8fc1b0f8
KG
804source "arch/arm/mach-qcom/Kconfig"
805
95b8f20f
RK
806source "arch/arm/mach-realview/Kconfig"
807
d63dc051
HS
808source "arch/arm/mach-rockchip/Kconfig"
809
95b8f20f 810source "arch/arm/mach-sa1100/Kconfig"
edabd38e 811
387798b3
RH
812source "arch/arm/mach-socfpga/Kconfig"
813
a7ed099f 814source "arch/arm/mach-spear/Kconfig"
a21765a7 815
65ebcc11
SK
816source "arch/arm/mach-sti/Kconfig"
817
85fd6d63 818source "arch/arm/mach-s3c24xx/Kconfig"
1da177e4 819
431107ea 820source "arch/arm/mach-s3c64xx/Kconfig"
a08ab637 821
170f4e42
KK
822source "arch/arm/mach-s5pv210/Kconfig"
823
83014579 824source "arch/arm/mach-exynos/Kconfig"
e509b289 825source "arch/arm/plat-samsung/Kconfig"
cc0e72b8 826
882d01f9 827source "arch/arm/mach-shmobile/Kconfig"
52c543f9 828
3b52634f
MR
829source "arch/arm/mach-sunxi/Kconfig"
830
156a0997
BS
831source "arch/arm/mach-prima2/Kconfig"
832
d6de5b02
MG
833source "arch/arm/mach-tango/Kconfig"
834
c5f80065
EG
835source "arch/arm/mach-tegra/Kconfig"
836
95b8f20f 837source "arch/arm/mach-u300/Kconfig"
1da177e4 838
ba56a987
MY
839source "arch/arm/mach-uniphier/Kconfig"
840
95b8f20f 841source "arch/arm/mach-ux500/Kconfig"
1da177e4
LT
842
843source "arch/arm/mach-versatile/Kconfig"
844
ceade897 845source "arch/arm/mach-vexpress/Kconfig"
420c34e4 846source "arch/arm/plat-versatile/Kconfig"
ceade897 847
6f35f9a9
TP
848source "arch/arm/mach-vt8500/Kconfig"
849
7ec80ddf 850source "arch/arm/mach-w90x900/Kconfig"
851
acede515
JN
852source "arch/arm/mach-zx/Kconfig"
853
9a45eb69
JC
854source "arch/arm/mach-zynq/Kconfig"
855
499f1640
SA
856# ARMv7-M architecture
857config ARCH_EFM32
858 bool "Energy Micro efm32"
859 depends on ARM_SINGLE_ARMV7M
860 select ARCH_REQUIRE_GPIOLIB
861 help
862 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
863 processors.
864
865config ARCH_LPC18XX
866 bool "NXP LPC18xx/LPC43xx"
867 depends on ARM_SINGLE_ARMV7M
868 select ARCH_HAS_RESET_CONTROLLER
869 select ARM_AMBA
870 select CLKSRC_LPC32XX
871 select PINCTRL
872 help
873 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
874 high performance microcontrollers.
875
876config ARCH_STM32
877 bool "STMicrolectronics STM32"
878 depends on ARM_SINGLE_ARMV7M
879 select ARCH_HAS_RESET_CONTROLLER
880 select ARMV7M_SYSTICK
25263186 881 select CLKSRC_STM32
499f1640
SA
882 select RESET_CONTROLLER
883 help
884 Support for STMicroelectronics STM32 processors.
885
fa65fc6b
MC
886config MACH_STM32F429
887 bool "STMicrolectronics STM32F429"
888 depends on ARCH_STM32
889 default y
890
1da177e4
LT
891# Definitions to make life easier
892config ARCH_ACORN
893 bool
894
7ae1f7ec
LB
895config PLAT_IOP
896 bool
469d3044 897 select GENERIC_CLOCKEVENTS
7ae1f7ec 898
69b02f6a
LB
899config PLAT_ORION
900 bool
bfe45e0b 901 select CLKSRC_MMIO
b1b3f49c 902 select COMMON_CLK
dc7ad3b3 903 select GENERIC_IRQ_CHIP
278b45b0 904 select IRQ_DOMAIN
69b02f6a 905
abcda1dc
TP
906config PLAT_ORION_LEGACY
907 bool
908 select PLAT_ORION
909
bd5ce433
EM
910config PLAT_PXA
911 bool
912
f4b8b319
RK
913config PLAT_VERSATILE
914 bool
915
d9a1beaa
AC
916source "arch/arm/firmware/Kconfig"
917
1da177e4
LT
918source arch/arm/mm/Kconfig
919
afe4b25e 920config IWMMXT
d93003e8
SH
921 bool "Enable iWMMXt support"
922 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
923 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
afe4b25e
LB
924 help
925 Enable support for iWMMXt context switching at run time if
926 running on a CPU that supports it.
927
52108641 928config MULTI_IRQ_HANDLER
929 bool
930 help
931 Allow each machine to specify it's own IRQ handler at run time.
932
3b93e7b0
HC
933if !MMU
934source "arch/arm/Kconfig-nommu"
935endif
936
3e0a07f8
GC
937config PJ4B_ERRATA_4742
938 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
939 depends on CPU_PJ4B && MACH_ARMADA_370
940 default y
941 help
942 When coming out of either a Wait for Interrupt (WFI) or a Wait for
943 Event (WFE) IDLE states, a specific timing sensitivity exists between
944 the retiring WFI/WFE instructions and the newly issued subsequent
945 instructions. This sensitivity can result in a CPU hang scenario.
946 Workaround:
947 The software must insert either a Data Synchronization Barrier (DSB)
948 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
949 instruction
950
f0c4b8d6
WD
951config ARM_ERRATA_326103
952 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
953 depends on CPU_V6
954 help
955 Executing a SWP instruction to read-only memory does not set bit 11
956 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
957 treat the access as a read, preventing a COW from occurring and
958 causing the faulting task to livelock.
959
9cba3ccc
CM
960config ARM_ERRATA_411920
961 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
e399b1a4 962 depends on CPU_V6 || CPU_V6K
9cba3ccc
CM
963 help
964 Invalidation of the Instruction Cache operation can
965 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
966 It does not affect the MPCore. This option enables the ARM Ltd.
967 recommended workaround.
968
7ce236fc
CM
969config ARM_ERRATA_430973
970 bool "ARM errata: Stale prediction on replaced interworking branch"
971 depends on CPU_V7
972 help
973 This option enables the workaround for the 430973 Cortex-A8
79403cda 974 r1p* erratum. If a code sequence containing an ARM/Thumb
7ce236fc
CM
975 interworking branch is replaced with another code sequence at the
976 same virtual address, whether due to self-modifying code or virtual
977 to physical address re-mapping, Cortex-A8 does not recover from the
978 stale interworking branch prediction. This results in Cortex-A8
979 executing the new code sequence in the incorrect ARM or Thumb state.
980 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
981 and also flushes the branch target cache at every context switch.
982 Note that setting specific bits in the ACTLR register may not be
983 available in non-secure mode.
984
855c551f
CM
985config ARM_ERRATA_458693
986 bool "ARM errata: Processor deadlock when a false hazard is created"
987 depends on CPU_V7
62e4d357 988 depends on !ARCH_MULTIPLATFORM
855c551f
CM
989 help
990 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
991 erratum. For very specific sequences of memory operations, it is
992 possible for a hazard condition intended for a cache line to instead
993 be incorrectly associated with a different cache line. This false
994 hazard might then cause a processor deadlock. The workaround enables
995 the L1 caching of the NEON accesses and disables the PLD instruction
996 in the ACTLR register. Note that setting specific bits in the ACTLR
997 register may not be available in non-secure mode.
998
0516e464
CM
999config ARM_ERRATA_460075
1000 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1001 depends on CPU_V7
62e4d357 1002 depends on !ARCH_MULTIPLATFORM
0516e464
CM
1003 help
1004 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1005 erratum. Any asynchronous access to the L2 cache may encounter a
1006 situation in which recent store transactions to the L2 cache are lost
1007 and overwritten with stale memory contents from external memory. The
1008 workaround disables the write-allocate mode for the L2 cache via the
1009 ACTLR register. Note that setting specific bits in the ACTLR register
1010 may not be available in non-secure mode.
1011
9f05027c
WD
1012config ARM_ERRATA_742230
1013 bool "ARM errata: DMB operation may be faulty"
1014 depends on CPU_V7 && SMP
62e4d357 1015 depends on !ARCH_MULTIPLATFORM
9f05027c
WD
1016 help
1017 This option enables the workaround for the 742230 Cortex-A9
1018 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1019 between two write operations may not ensure the correct visibility
1020 ordering of the two writes. This workaround sets a specific bit in
1021 the diagnostic register of the Cortex-A9 which causes the DMB
1022 instruction to behave as a DSB, ensuring the correct behaviour of
1023 the two writes.
1024
a672e99b
WD
1025config ARM_ERRATA_742231
1026 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1027 depends on CPU_V7 && SMP
62e4d357 1028 depends on !ARCH_MULTIPLATFORM
a672e99b
WD
1029 help
1030 This option enables the workaround for the 742231 Cortex-A9
1031 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1032 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1033 accessing some data located in the same cache line, may get corrupted
1034 data due to bad handling of the address hazard when the line gets
1035 replaced from one of the CPUs at the same time as another CPU is
1036 accessing it. This workaround sets specific bits in the diagnostic
1037 register of the Cortex-A9 which reduces the linefill issuing
1038 capabilities of the processor.
1039
69155794
JM
1040config ARM_ERRATA_643719
1041 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1042 depends on CPU_V7 && SMP
e5a5de44 1043 default y
69155794
JM
1044 help
1045 This option enables the workaround for the 643719 Cortex-A9 (prior to
1046 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1047 register returns zero when it should return one. The workaround
1048 corrects this value, ensuring cache maintenance operations which use
1049 it behave as intended and avoiding data corruption.
1050
cdf357f1
WD
1051config ARM_ERRATA_720789
1052 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
e66dc745 1053 depends on CPU_V7
cdf357f1
WD
1054 help
1055 This option enables the workaround for the 720789 Cortex-A9 (prior to
1056 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1057 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1058 As a consequence of this erratum, some TLB entries which should be
1059 invalidated are not, resulting in an incoherency in the system page
1060 tables. The workaround changes the TLB flushing routines to invalidate
1061 entries regardless of the ASID.
475d92fc
WD
1062
1063config ARM_ERRATA_743622
1064 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1065 depends on CPU_V7
62e4d357 1066 depends on !ARCH_MULTIPLATFORM
475d92fc
WD
1067 help
1068 This option enables the workaround for the 743622 Cortex-A9
efbc74ac 1069 (r2p*) erratum. Under very rare conditions, a faulty
475d92fc
WD
1070 optimisation in the Cortex-A9 Store Buffer may lead to data
1071 corruption. This workaround sets a specific bit in the diagnostic
1072 register of the Cortex-A9 which disables the Store Buffer
1073 optimisation, preventing the defect from occurring. This has no
1074 visible impact on the overall performance or power consumption of the
1075 processor.
1076
9a27c27c
WD
1077config ARM_ERRATA_751472
1078 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
ba90c516 1079 depends on CPU_V7
62e4d357 1080 depends on !ARCH_MULTIPLATFORM
9a27c27c
WD
1081 help
1082 This option enables the workaround for the 751472 Cortex-A9 (prior
1083 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1084 completion of a following broadcasted operation if the second
1085 operation is received by a CPU before the ICIALLUIS has completed,
1086 potentially leading to corrupted entries in the cache or TLB.
1087
fcbdc5fe
WD
1088config ARM_ERRATA_754322
1089 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1090 depends on CPU_V7
1091 help
1092 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1093 r3p*) erratum. A speculative memory access may cause a page table walk
1094 which starts prior to an ASID switch but completes afterwards. This
1095 can populate the micro-TLB with a stale entry which may be hit with
1096 the new ASID. This workaround places two dsb instructions in the mm
1097 switching code so that no page table walks can cross the ASID switch.
1098
5dab26af
WD
1099config ARM_ERRATA_754327
1100 bool "ARM errata: no automatic Store Buffer drain"
1101 depends on CPU_V7 && SMP
1102 help
1103 This option enables the workaround for the 754327 Cortex-A9 (prior to
1104 r2p0) erratum. The Store Buffer does not have any automatic draining
1105 mechanism and therefore a livelock may occur if an external agent
1106 continuously polls a memory location waiting to observe an update.
1107 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1108 written polling loops from denying visibility of updates to memory.
1109
145e10e1
CM
1110config ARM_ERRATA_364296
1111 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
fd832478 1112 depends on CPU_V6
145e10e1
CM
1113 help
1114 This options enables the workaround for the 364296 ARM1136
1115 r0p2 erratum (possible cache data corruption with
1116 hit-under-miss enabled). It sets the undocumented bit 31 in
1117 the auxiliary control register and the FI bit in the control
1118 register, thus disabling hit-under-miss without putting the
1119 processor into full low interrupt latency mode. ARM11MPCore
1120 is not affected.
1121
f630c1bd
WD
1122config ARM_ERRATA_764369
1123 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1124 depends on CPU_V7 && SMP
1125 help
1126 This option enables the workaround for erratum 764369
1127 affecting Cortex-A9 MPCore with two or more processors (all
1128 current revisions). Under certain timing circumstances, a data
1129 cache line maintenance operation by MVA targeting an Inner
1130 Shareable memory region may fail to proceed up to either the
1131 Point of Coherency or to the Point of Unification of the
1132 system. This workaround adds a DSB instruction before the
1133 relevant cache maintenance functions and sets a specific bit
1134 in the diagnostic control register of the SCU.
1135
7253b85c
SH
1136config ARM_ERRATA_775420
1137 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1138 depends on CPU_V7
1139 help
1140 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1141 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1142 operation aborts with MMU exception, it might cause the processor
1143 to deadlock. This workaround puts DSB before executing ISB if
1144 an abort may occur on cache maintenance.
1145
93dc6887
CM
1146config ARM_ERRATA_798181
1147 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1148 depends on CPU_V7 && SMP
1149 help
1150 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1151 adequately shooting down all use of the old entries. This
1152 option enables the Linux kernel workaround for this erratum
1153 which sends an IPI to the CPUs that are running the same ASID
1154 as the one being invalidated.
1155
84b6504f
WD
1156config ARM_ERRATA_773022
1157 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1158 depends on CPU_V7
1159 help
1160 This option enables the workaround for the 773022 Cortex-A15
1161 (up to r0p4) erratum. In certain rare sequences of code, the
1162 loop buffer may deliver incorrect instructions. This
1163 workaround disables the loop buffer to avoid the erratum.
1164
1da177e4
LT
1165endmenu
1166
1167source "arch/arm/common/Kconfig"
1168
1da177e4
LT
1169menu "Bus support"
1170
1da177e4
LT
1171config ISA
1172 bool
1da177e4
LT
1173 help
1174 Find out whether you have ISA slots on your motherboard. ISA is the
1175 name of a bus system, i.e. the way the CPU talks to the other stuff
1176 inside your box. Other bus systems are PCI, EISA, MicroChannel
1177 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1178 newer boards don't support it. If you have ISA, say Y, otherwise N.
1179
065909b9 1180# Select ISA DMA controller support
1da177e4
LT
1181config ISA_DMA
1182 bool
065909b9 1183 select ISA_DMA_API
1da177e4 1184
065909b9 1185# Select ISA DMA interface
5cae841b
AV
1186config ISA_DMA_API
1187 bool
5cae841b 1188
1da177e4 1189config PCI
0b05da72 1190 bool "PCI support" if MIGHT_HAVE_PCI
1da177e4
LT
1191 help
1192 Find out whether you have a PCI motherboard. PCI is the name of a
1193 bus system, i.e. the way the CPU talks to the other stuff inside
1194 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1195 VESA. If you have PCI, say Y, otherwise N.
1196
52882173
AV
1197config PCI_DOMAINS
1198 bool
1199 depends on PCI
1200
8c7d1474
LP
1201config PCI_DOMAINS_GENERIC
1202 def_bool PCI_DOMAINS
1203
b080ac8a
MRJ
1204config PCI_NANOENGINE
1205 bool "BSE nanoEngine PCI support"
1206 depends on SA1100_NANOENGINE
1207 help
1208 Enable PCI on the BSE nanoEngine board.
1209
36e23590
MW
1210config PCI_SYSCALL
1211 def_bool PCI
1212
a0113a99
MR
1213config PCI_HOST_ITE8152
1214 bool
1215 depends on PCI && MACH_ARMCORE
1216 default y
1217 select DMABOUNCE
1218
1da177e4 1219source "drivers/pci/Kconfig"
3f06d157 1220source "drivers/pci/pcie/Kconfig"
1da177e4
LT
1221
1222source "drivers/pcmcia/Kconfig"
1223
1224endmenu
1225
1226menu "Kernel Features"
1227
3b55658a
DM
1228config HAVE_SMP
1229 bool
1230 help
1231 This option should be selected by machines which have an SMP-
1232 capable CPU.
1233
1234 The only effect of this option is to make the SMP-related
1235 options available to the user for configuration.
1236
1da177e4 1237config SMP
bb2d8130 1238 bool "Symmetric Multi-Processing"
fbb4ddac 1239 depends on CPU_V6K || CPU_V7
bc28248e 1240 depends on GENERIC_CLOCKEVENTS
3b55658a 1241 depends on HAVE_SMP
801bb21c 1242 depends on MMU || ARM_MPU
0361748f 1243 select IRQ_WORK
1da177e4
LT
1244 help
1245 This enables support for systems with more than one CPU. If you have
4a474157
RG
1246 a system with only one CPU, say N. If you have a system with more
1247 than one CPU, say Y.
1da177e4 1248
4a474157 1249 If you say N here, the kernel will run on uni- and multiprocessor
1da177e4 1250 machines, but will use only one CPU of a multiprocessor machine. If
4a474157
RG
1251 you say Y here, the kernel will run on many, but not all,
1252 uniprocessor machines. On a uniprocessor machine, the kernel
1253 will run faster if you say N here.
1da177e4 1254
395cf969 1255 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1da177e4 1256 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
50a23e6e 1257 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1da177e4
LT
1258
1259 If you don't know what to do here, say N.
1260
f00ec48f 1261config SMP_ON_UP
5744ff43 1262 bool "Allow booting SMP kernel on uniprocessor systems"
801bb21c 1263 depends on SMP && !XIP_KERNEL && MMU
f00ec48f
RK
1264 default y
1265 help
1266 SMP kernels contain instructions which fail on non-SMP processors.
1267 Enabling this option allows the kernel to modify itself to make
1268 these instructions safe. Disabling it allows about 1K of space
1269 savings.
1270
1271 If you don't know what to do here, say Y.
1272
c9018aab
VG
1273config ARM_CPU_TOPOLOGY
1274 bool "Support cpu topology definition"
1275 depends on SMP && CPU_V7
1276 default y
1277 help
1278 Support ARM cpu topology definition. The MPIDR register defines
1279 affinity between processors which is then used to describe the cpu
1280 topology of an ARM System.
1281
1282config SCHED_MC
1283 bool "Multi-core scheduler support"
1284 depends on ARM_CPU_TOPOLOGY
1285 help
1286 Multi-core scheduler support improves the CPU scheduler's decision
1287 making when dealing with multi-core CPU chips at a cost of slightly
1288 increased overhead in some places. If unsure say N here.
1289
1290config SCHED_SMT
1291 bool "SMT scheduler support"
1292 depends on ARM_CPU_TOPOLOGY
1293 help
1294 Improves the CPU scheduler's decision making when dealing with
1295 MultiThreading at a cost of slightly increased overhead in some
1296 places. If unsure say N here.
1297
a8cbcd92
RK
1298config HAVE_ARM_SCU
1299 bool
a8cbcd92
RK
1300 help
1301 This option enables support for the ARM system coherency unit
1302
8a4da6e3 1303config HAVE_ARM_ARCH_TIMER
022c03a2
MZ
1304 bool "Architected timer support"
1305 depends on CPU_V7
8a4da6e3 1306 select ARM_ARCH_TIMER
0c403462 1307 select GENERIC_CLOCKEVENTS
022c03a2
MZ
1308 help
1309 This option enables support for the ARM architected timer
1310
f32f4ce2
RK
1311config HAVE_ARM_TWD
1312 bool
da4a686a 1313 select CLKSRC_OF if OF
f32f4ce2
RK
1314 help
1315 This options enables support for the ARM timer and watchdog unit
1316
e8db288e
NP
1317config MCPM
1318 bool "Multi-Cluster Power Management"
1319 depends on CPU_V7 && SMP
1320 help
1321 This option provides the common power management infrastructure
1322 for (multi-)cluster based systems, such as big.LITTLE based
1323 systems.
1324
ebf4a5c5
HZ
1325config MCPM_QUAD_CLUSTER
1326 bool
1327 depends on MCPM
1328 help
1329 To avoid wasting resources unnecessarily, MCPM only supports up
1330 to 2 clusters by default.
1331 Platforms with 3 or 4 clusters that use MCPM must select this
1332 option to allow the additional clusters to be managed.
1333
1c33be57
NP
1334config BIG_LITTLE
1335 bool "big.LITTLE support (Experimental)"
1336 depends on CPU_V7 && SMP
1337 select MCPM
1338 help
1339 This option enables support selections for the big.LITTLE
1340 system architecture.
1341
1342config BL_SWITCHER
1343 bool "big.LITTLE switcher support"
6c044fec 1344 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1c33be57 1345 select ARM_CPU_SUSPEND
51aaf81f 1346 select CPU_PM
1c33be57
NP
1347 help
1348 The big.LITTLE "switcher" provides the core functionality to
1349 transparently handle transition between a cluster of A15's
1350 and a cluster of A7's in a big.LITTLE system.
1351
b22537c6
NP
1352config BL_SWITCHER_DUMMY_IF
1353 tristate "Simple big.LITTLE switcher user interface"
1354 depends on BL_SWITCHER && DEBUG_KERNEL
1355 help
1356 This is a simple and dummy char dev interface to control
1357 the big.LITTLE switcher core code. It is meant for
1358 debugging purposes only.
1359
8d5796d2
LB
1360choice
1361 prompt "Memory split"
006fa259 1362 depends on MMU
8d5796d2
LB
1363 default VMSPLIT_3G
1364 help
1365 Select the desired split between kernel and user memory.
1366
1367 If you are not absolutely sure what you are doing, leave this
1368 option alone!
1369
1370 config VMSPLIT_3G
1371 bool "3G/1G user/kernel split"
63ce446c
NP
1372 config VMSPLIT_3G_OPT
1373 bool "3G/1G user/kernel split (for full 1G low memory)"
8d5796d2
LB
1374 config VMSPLIT_2G
1375 bool "2G/2G user/kernel split"
1376 config VMSPLIT_1G
1377 bool "1G/3G user/kernel split"
1378endchoice
1379
1380config PAGE_OFFSET
1381 hex
006fa259 1382 default PHYS_OFFSET if !MMU
8d5796d2
LB
1383 default 0x40000000 if VMSPLIT_1G
1384 default 0x80000000 if VMSPLIT_2G
63ce446c 1385 default 0xB0000000 if VMSPLIT_3G_OPT
8d5796d2
LB
1386 default 0xC0000000
1387
1da177e4
LT
1388config NR_CPUS
1389 int "Maximum number of CPUs (2-32)"
1390 range 2 32
1391 depends on SMP
1392 default "4"
1393
a054a811 1394config HOTPLUG_CPU
00b7dede 1395 bool "Support for hot-pluggable CPUs"
40b31360 1396 depends on SMP
a054a811
RK
1397 help
1398 Say Y here to experiment with turning CPUs off and on. CPUs
1399 can be controlled through /sys/devices/system/cpu.
1400
2bdd424f
WD
1401config ARM_PSCI
1402 bool "Support for the ARM Power State Coordination Interface (PSCI)"
e679660d 1403 depends on HAVE_ARM_SMCCC
be120397 1404 select ARM_PSCI_FW
2bdd424f
WD
1405 help
1406 Say Y here if you want Linux to communicate with system firmware
1407 implementing the PSCI specification for CPU-centric power
1408 management operations described in ARM document number ARM DEN
1409 0022A ("Power State Coordination Interface System Software on
1410 ARM processors").
1411
2a6ad871
MR
1412# The GPIO number here must be sorted by descending number. In case of
1413# a multiplatform kernel, we just want the highest value required by the
1414# selected platforms.
44986ab0
PDSN
1415config ARCH_NR_GPIO
1416 int
b35d2e56
GF
1417 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1418 ARCH_ZYNQ
aa42587a
TF
1419 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1420 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
eb171a99 1421 default 416 if ARCH_SUNXI
06b851e5 1422 default 392 if ARCH_U8500
01bb914c 1423 default 352 if ARCH_VT8500
7b5da4c3 1424 default 288 if ARCH_ROCKCHIP
2a6ad871 1425 default 264 if MACH_H4700
44986ab0
PDSN
1426 default 0
1427 help
1428 Maximum number of GPIOs in the system.
1429
1430 If unsure, leave the default value.
1431
d45a398f 1432source kernel/Kconfig.preempt
1da177e4 1433
c9218b16 1434config HZ_FIXED
f8065813 1435 int
070b8b43 1436 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
a73ddc61 1437 ARCH_S5PV210 || ARCH_EXYNOS4
1164f672 1438 default 128 if SOC_AT91RM9200
47d84682 1439 default 0
c9218b16
RK
1440
1441choice
47d84682 1442 depends on HZ_FIXED = 0
c9218b16
RK
1443 prompt "Timer frequency"
1444
1445config HZ_100
1446 bool "100 Hz"
1447
1448config HZ_200
1449 bool "200 Hz"
1450
1451config HZ_250
1452 bool "250 Hz"
1453
1454config HZ_300
1455 bool "300 Hz"
1456
1457config HZ_500
1458 bool "500 Hz"
1459
1460config HZ_1000
1461 bool "1000 Hz"
1462
1463endchoice
1464
1465config HZ
1466 int
47d84682 1467 default HZ_FIXED if HZ_FIXED != 0
c9218b16
RK
1468 default 100 if HZ_100
1469 default 200 if HZ_200
1470 default 250 if HZ_250
1471 default 300 if HZ_300
1472 default 500 if HZ_500
1473 default 1000
1474
1475config SCHED_HRTICK
1476 def_bool HIGH_RES_TIMERS
f8065813 1477
16c79651 1478config THUMB2_KERNEL
bc7dea00 1479 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
4477ca45 1480 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
bc7dea00 1481 default y if CPU_THUMBONLY
16c79651
CM
1482 select AEABI
1483 select ARM_ASM_UNIFIED
89bace65 1484 select ARM_UNWIND
16c79651
CM
1485 help
1486 By enabling this option, the kernel will be compiled in
1487 Thumb-2 mode. A compiler/assembler that understand the unified
1488 ARM-Thumb syntax is needed.
1489
1490 If unsure, say N.
1491
6f685c5c
DM
1492config THUMB2_AVOID_R_ARM_THM_JUMP11
1493 bool "Work around buggy Thumb-2 short branch relocations in gas"
1494 depends on THUMB2_KERNEL && MODULES
1495 default y
1496 help
1497 Various binutils versions can resolve Thumb-2 branches to
1498 locally-defined, preemptible global symbols as short-range "b.n"
1499 branch instructions.
1500
1501 This is a problem, because there's no guarantee the final
1502 destination of the symbol, or any candidate locations for a
1503 trampoline, are within range of the branch. For this reason, the
1504 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1505 relocation in modules at all, and it makes little sense to add
1506 support.
1507
1508 The symptom is that the kernel fails with an "unsupported
1509 relocation" error when loading some modules.
1510
1511 Until fixed tools are available, passing
1512 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1513 code which hits this problem, at the cost of a bit of extra runtime
1514 stack usage in some cases.
1515
1516 The problem is described in more detail at:
1517 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1518
1519 Only Thumb-2 kernels are affected.
1520
1521 Unless you are sure your tools don't have this problem, say Y.
1522
0becb088
CM
1523config ARM_ASM_UNIFIED
1524 bool
1525
42f25bdd
NP
1526config ARM_PATCH_IDIV
1527 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1528 depends on CPU_32v7 && !XIP_KERNEL
1529 default y
1530 help
1531 The ARM compiler inserts calls to __aeabi_idiv() and
1532 __aeabi_uidiv() when it needs to perform division on signed
1533 and unsigned integers. Some v7 CPUs have support for the sdiv
1534 and udiv instructions that can be used to implement those
1535 functions.
1536
1537 Enabling this option allows the kernel to modify itself to
1538 replace the first two instructions of these library functions
1539 with the sdiv or udiv plus "bx lr" instructions when the CPU
1540 it is running on supports them. Typically this will be faster
1541 and less power intensive than running the original library
1542 code to do integer division.
1543
704bdda0
NP
1544config AEABI
1545 bool "Use the ARM EABI to compile the kernel"
1546 help
1547 This option allows for the kernel to be compiled using the latest
1548 ARM ABI (aka EABI). This is only useful if you are using a user
1549 space environment that is also compiled with EABI.
1550
1551 Since there are major incompatibilities between the legacy ABI and
1552 EABI, especially with regard to structure member alignment, this
1553 option also changes the kernel syscall calling convention to
1554 disambiguate both ABIs and allow for backward compatibility support
1555 (selected with CONFIG_OABI_COMPAT).
1556
1557 To use this you need GCC version 4.0.0 or later.
1558
6c90c872 1559config OABI_COMPAT
a73a3ff1 1560 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
d6f94fa0 1561 depends on AEABI && !THUMB2_KERNEL
6c90c872
NP
1562 help
1563 This option preserves the old syscall interface along with the
1564 new (ARM EABI) one. It also provides a compatibility layer to
1565 intercept syscalls that have structure arguments which layout
1566 in memory differs between the legacy ABI and the new ARM EABI
1567 (only for non "thumb" binaries). This option adds a tiny
1568 overhead to all syscalls and produces a slightly larger kernel.
91702175
KC
1569
1570 The seccomp filter system will not be available when this is
1571 selected, since there is no way yet to sensibly distinguish
1572 between calling conventions during filtering.
1573
6c90c872
NP
1574 If you know you'll be using only pure EABI user space then you
1575 can say N here. If this option is not selected and you attempt
1576 to execute a legacy ABI binary then the result will be
1577 UNPREDICTABLE (in fact it can be predicted that it won't work
b02f8467 1578 at all). If in doubt say N.
6c90c872 1579
eb33575c 1580config ARCH_HAS_HOLES_MEMORYMODEL
e80d6a24 1581 bool
e80d6a24 1582
05944d74
RK
1583config ARCH_SPARSEMEM_ENABLE
1584 bool
1585
07a2f737
RK
1586config ARCH_SPARSEMEM_DEFAULT
1587 def_bool ARCH_SPARSEMEM_ENABLE
1588
05944d74 1589config ARCH_SELECT_MEMORY_MODEL
be370302 1590 def_bool ARCH_SPARSEMEM_ENABLE
c80d79d7 1591
7b7bf499
WD
1592config HAVE_ARCH_PFN_VALID
1593 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1594
b8cd51af
SC
1595config HAVE_GENERIC_RCU_GUP
1596 def_bool y
1597 depends on ARM_LPAE
1598
053a96ca 1599config HIGHMEM
e8db89a2
RK
1600 bool "High Memory Support"
1601 depends on MMU
053a96ca
NP
1602 help
1603 The address space of ARM processors is only 4 Gigabytes large
1604 and it has to accommodate user address space, kernel address
1605 space as well as some memory mapped IO. That means that, if you
1606 have a large amount of physical memory and/or IO, not all of the
1607 memory can be "permanently mapped" by the kernel. The physical
1608 memory that is not permanently mapped is called "high memory".
1609
1610 Depending on the selected kernel/user memory split, minimum
1611 vmalloc space and actual amount of RAM, you may not need this
1612 option which should result in a slightly faster kernel.
1613
1614 If unsure, say n.
1615
65cec8e3 1616config HIGHPTE
9a431bd5 1617 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
65cec8e3 1618 depends on HIGHMEM
9a431bd5 1619 default y
b4d103d1
RK
1620 help
1621 The VM uses one page of physical memory for each page table.
1622 For systems with a lot of processes, this can use a lot of
1623 precious low memory, eventually leading to low memory being
1624 consumed by page tables. Setting this option will allow
1625 user-space 2nd level page tables to reside in high memory.
65cec8e3 1626
a5e090ac
RK
1627config CPU_SW_DOMAIN_PAN
1628 bool "Enable use of CPU domains to implement privileged no-access"
1629 depends on MMU && !ARM_LPAE
1b8873a0
JI
1630 default y
1631 help
a5e090ac
RK
1632 Increase kernel security by ensuring that normal kernel accesses
1633 are unable to access userspace addresses. This can help prevent
1634 use-after-free bugs becoming an exploitable privilege escalation
1635 by ensuring that magic values (such as LIST_POISON) will always
1636 fault when dereferenced.
1637
1638 CPUs with low-vector mappings use a best-efforts implementation.
1639 Their lower 1MB needs to remain accessible for the vectors, but
1640 the remainder of userspace will become appropriately inaccessible.
65cec8e3 1641
1b8873a0 1642config HW_PERF_EVENTS
fa8ad788
MR
1643 def_bool y
1644 depends on ARM_PMU
1b8873a0 1645
1355e2a6
CM
1646config SYS_SUPPORTS_HUGETLBFS
1647 def_bool y
1648 depends on ARM_LPAE
1649
8d962507
CM
1650config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1651 def_bool y
1652 depends on ARM_LPAE
1653
4bfab203
SC
1654config ARCH_WANT_GENERAL_HUGETLB
1655 def_bool y
1656
7d485f64
AB
1657config ARM_MODULE_PLTS
1658 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1659 depends on MODULES
1660 help
1661 Allocate PLTs when loading modules so that jumps and calls whose
1662 targets are too far away for their relative offsets to be encoded
1663 in the instructions themselves can be bounced via veneers in the
1664 module's PLT. This allows modules to be allocated in the generic
1665 vmalloc area after the dedicated module memory area has been
1666 exhausted. The modules will use slightly more memory, but after
1667 rounding up to page size, the actual memory footprint is usually
1668 the same.
1669
1670 Say y if you are getting out of memory errors while loading modules
1671
3f22ab27
DH
1672source "mm/Kconfig"
1673
c1b2d970 1674config FORCE_MAX_ZONEORDER
36d6c928 1675 int "Maximum zone order"
898f08e1 1676 default "12" if SOC_AM33XX
6d85e2b0 1677 default "9" if SA1111 || ARCH_EFM32
c1b2d970
MD
1678 default "11"
1679 help
1680 The kernel memory allocator divides physically contiguous memory
1681 blocks into "zones", where each zone is a power of two number of
1682 pages. This option selects the largest power of two that the kernel
1683 keeps in the memory allocator. If you need to allocate very large
1684 blocks of physically contiguous memory, then you may need to
1685 increase this value.
1686
1687 This config option is actually maximum order plus one. For example,
1688 a value of 11 means that the largest free memory block is 2^10 pages.
1689
1da177e4
LT
1690config ALIGNMENT_TRAP
1691 bool
f12d0d7c 1692 depends on CPU_CP15_MMU
1da177e4 1693 default y if !ARCH_EBSA110
e119bfff 1694 select HAVE_PROC_CPU if PROC_FS
1da177e4 1695 help
84eb8d06 1696 ARM processors cannot fetch/store information which is not
1da177e4
LT
1697 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1698 address divisible by 4. On 32-bit ARM processors, these non-aligned
1699 fetch/store instructions will be emulated in software if you say
1700 here, which has a severe performance impact. This is necessary for
1701 correct operation of some network protocols. With an IP-only
1702 configuration it is safe to say N, otherwise say Y.
1703
39ec58f3 1704config UACCESS_WITH_MEMCPY
38ef2ad5
LW
1705 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1706 depends on MMU
39ec58f3
LB
1707 default y if CPU_FEROCEON
1708 help
1709 Implement faster copy_to_user and clear_user methods for CPU
1710 cores where a 8-word STM instruction give significantly higher
1711 memory write throughput than a sequence of individual 32bit stores.
1712
1713 A possible side effect is a slight increase in scheduling latency
1714 between threads sharing the same address space if they invoke
1715 such copy operations with large buffers.
1716
1717 However, if the CPU data cache is using a write-allocate mode,
1718 this option is unlikely to provide any performance gain.
1719
70c70d97
NP
1720config SECCOMP
1721 bool
1722 prompt "Enable seccomp to safely compute untrusted bytecode"
1723 ---help---
1724 This kernel feature is useful for number crunching applications
1725 that may need to compute untrusted bytecode during their
1726 execution. By using pipes or other transports made available to
1727 the process as file descriptors supporting the read/write
1728 syscalls, it's possible to isolate those applications in
1729 their own address space using seccomp. Once seccomp is
1730 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1731 and the task is only allowed to execute a few safe syscalls
1732 defined by each seccomp mode.
1733
06e6295b
SS
1734config SWIOTLB
1735 def_bool y
1736
1737config IOMMU_HELPER
1738 def_bool SWIOTLB
1739
02c2433b
SS
1740config PARAVIRT
1741 bool "Enable paravirtualization code"
1742 help
1743 This changes the kernel so it can modify itself when it is run
1744 under a hypervisor, potentially improving performance significantly
1745 over full virtualization.
1746
1747config PARAVIRT_TIME_ACCOUNTING
1748 bool "Paravirtual steal time accounting"
1749 select PARAVIRT
1750 default n
1751 help
1752 Select this option to enable fine granularity task steal time
1753 accounting. Time spent executing other tasks in parallel with
1754 the current vCPU is discounted from the vCPU power. To account for
1755 that, there can be a small performance impact.
1756
1757 If in doubt, say N here.
1758
eff8d644
SS
1759config XEN_DOM0
1760 def_bool y
1761 depends on XEN
1762
1763config XEN
c2ba1f7d 1764 bool "Xen guest support on ARM"
85323a99 1765 depends on ARM && AEABI && OF
f880b67d 1766 depends on CPU_V7 && !CPU_V6
85323a99 1767 depends on !GENERIC_ATOMIC64
7693decc 1768 depends on MMU
51aaf81f 1769 select ARCH_DMA_ADDR_T_64BIT
17b7ab80 1770 select ARM_PSCI
83862ccf 1771 select SWIOTLB_XEN
02c2433b 1772 select PARAVIRT
eff8d644
SS
1773 help
1774 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1775
1da177e4
LT
1776endmenu
1777
1778menu "Boot options"
1779
9eb8f674
GL
1780config USE_OF
1781 bool "Flattened Device Tree support"
b1b3f49c 1782 select IRQ_DOMAIN
9eb8f674 1783 select OF
9eb8f674
GL
1784 help
1785 Include support for flattened device tree machine descriptions.
1786
bd51e2f5
NP
1787config ATAGS
1788 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1789 default y
1790 help
1791 This is the traditional way of passing data to the kernel at boot
1792 time. If you are solely relying on the flattened device tree (or
1793 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1794 to remove ATAGS support from your kernel binary. If unsure,
1795 leave this to y.
1796
1797config DEPRECATED_PARAM_STRUCT
1798 bool "Provide old way to pass kernel parameters"
1799 depends on ATAGS
1800 help
1801 This was deprecated in 2001 and announced to live on for 5 years.
1802 Some old boot loaders still use this way.
1803
1da177e4
LT
1804# Compressed boot loader in ROM. Yes, we really want to ask about
1805# TEXT and BSS so we preserve their values in the config files.
1806config ZBOOT_ROM_TEXT
1807 hex "Compressed ROM boot loader base address"
1808 default "0"
1809 help
1810 The physical address at which the ROM-able zImage is to be
1811 placed in the target. Platforms which normally make use of
1812 ROM-able zImage formats normally set this to a suitable
1813 value in their defconfig file.
1814
1815 If ZBOOT_ROM is not enabled, this has no effect.
1816
1817config ZBOOT_ROM_BSS
1818 hex "Compressed ROM boot loader BSS address"
1819 default "0"
1820 help
f8c440b2
DF
1821 The base address of an area of read/write memory in the target
1822 for the ROM-able zImage which must be available while the
1823 decompressor is running. It must be large enough to hold the
1824 entire decompressed kernel plus an additional 128 KiB.
1825 Platforms which normally make use of ROM-able zImage formats
1826 normally set this to a suitable value in their defconfig file.
1da177e4
LT
1827
1828 If ZBOOT_ROM is not enabled, this has no effect.
1829
1830config ZBOOT_ROM
1831 bool "Compressed boot loader in ROM/flash"
1832 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
10968131 1833 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1da177e4
LT
1834 help
1835 Say Y here if you intend to execute your compressed kernel image
1836 (zImage) directly from ROM or flash. If unsure, say N.
1837
e2a6a3aa
JB
1838config ARM_APPENDED_DTB
1839 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
10968131 1840 depends on OF
e2a6a3aa
JB
1841 help
1842 With this option, the boot code will look for a device tree binary
1843 (DTB) appended to zImage
1844 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1845
1846 This is meant as a backward compatibility convenience for those
1847 systems with a bootloader that can't be upgraded to accommodate
1848 the documented boot protocol using a device tree.
1849
1850 Beware that there is very little in terms of protection against
1851 this option being confused by leftover garbage in memory that might
1852 look like a DTB header after a reboot if no actual DTB is appended
1853 to zImage. Do not leave this option active in a production kernel
1854 if you don't intend to always append a DTB. Proper passing of the
1855 location into r2 of a bootloader provided DTB is always preferable
1856 to this option.
1857
b90b9a38
NP
1858config ARM_ATAG_DTB_COMPAT
1859 bool "Supplement the appended DTB with traditional ATAG information"
1860 depends on ARM_APPENDED_DTB
1861 help
1862 Some old bootloaders can't be updated to a DTB capable one, yet
1863 they provide ATAGs with memory configuration, the ramdisk address,
1864 the kernel cmdline string, etc. Such information is dynamically
1865 provided by the bootloader and can't always be stored in a static
1866 DTB. To allow a device tree enabled kernel to be used with such
1867 bootloaders, this option allows zImage to extract the information
1868 from the ATAG list and store it at run time into the appended DTB.
1869
d0f34a11
GR
1870choice
1871 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1872 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1873
1874config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1875 bool "Use bootloader kernel arguments if available"
1876 help
1877 Uses the command-line options passed by the boot loader instead of
1878 the device tree bootargs property. If the boot loader doesn't provide
1879 any, the device tree bootargs property will be used.
1880
1881config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1882 bool "Extend with bootloader kernel arguments"
1883 help
1884 The command-line arguments provided by the boot loader will be
1885 appended to the the device tree bootargs property.
1886
1887endchoice
1888
1da177e4
LT
1889config CMDLINE
1890 string "Default kernel command string"
1891 default ""
1892 help
1893 On some architectures (EBSA110 and CATS), there is currently no way
1894 for the boot loader to pass arguments to the kernel. For these
1895 architectures, you should supply some command-line options at build
1896 time by entering them here. As a minimum, you should specify the
1897 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1898
4394c124
VB
1899choice
1900 prompt "Kernel command line type" if CMDLINE != ""
1901 default CMDLINE_FROM_BOOTLOADER
bd51e2f5 1902 depends on ATAGS
4394c124
VB
1903
1904config CMDLINE_FROM_BOOTLOADER
1905 bool "Use bootloader kernel arguments if available"
1906 help
1907 Uses the command-line options passed by the boot loader. If
1908 the boot loader doesn't provide any, the default kernel command
1909 string provided in CMDLINE will be used.
1910
1911config CMDLINE_EXTEND
1912 bool "Extend bootloader kernel arguments"
1913 help
1914 The command-line arguments provided by the boot loader will be
1915 appended to the default kernel command string.
1916
92d2040d
AH
1917config CMDLINE_FORCE
1918 bool "Always use the default kernel command string"
92d2040d
AH
1919 help
1920 Always use the default kernel command string, even if the boot
1921 loader passes other arguments to the kernel.
1922 This is useful if you cannot or don't want to change the
1923 command-line options your boot loader passes to the kernel.
4394c124 1924endchoice
92d2040d 1925
1da177e4
LT
1926config XIP_KERNEL
1927 bool "Kernel Execute-In-Place from ROM"
10968131 1928 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1da177e4
LT
1929 help
1930 Execute-In-Place allows the kernel to run from non-volatile storage
1931 directly addressable by the CPU, such as NOR flash. This saves RAM
1932 space since the text section of the kernel is not loaded from flash
1933 to RAM. Read-write sections, such as the data section and stack,
1934 are still copied to RAM. The XIP kernel is not compressed since
1935 it has to run directly from flash, so it will take more space to
1936 store it. The flash address used to link the kernel object files,
1937 and for storing it, is configuration dependent. Therefore, if you
1938 say Y here, you must know the proper physical address where to
1939 store the kernel image depending on your own flash memory usage.
1940
1941 Also note that the make target becomes "make xipImage" rather than
1942 "make zImage" or "make Image". The final kernel binary to put in
1943 ROM memory will be arch/arm/boot/xipImage.
1944
1945 If unsure, say N.
1946
1947config XIP_PHYS_ADDR
1948 hex "XIP Kernel Physical Location"
1949 depends on XIP_KERNEL
1950 default "0x00080000"
1951 help
1952 This is the physical address in your flash memory the kernel will
1953 be linked for and stored to. This address is dependent on your
1954 own flash usage.
1955
c587e4a6
RP
1956config KEXEC
1957 bool "Kexec system call (EXPERIMENTAL)"
19ab428f 1958 depends on (!SMP || PM_SLEEP_SMP)
cb1293e2 1959 depends on !CPU_V7M
2965faa5 1960 select KEXEC_CORE
c587e4a6
RP
1961 help
1962 kexec is a system call that implements the ability to shutdown your
1963 current kernel, and to start another kernel. It is like a reboot
01dd2fbf 1964 but it is independent of the system firmware. And like a reboot
c587e4a6
RP
1965 you can start any kernel with it, not just Linux.
1966
1967 It is an ongoing process to be certain the hardware in a machine
1968 is properly shutdown, so do not be surprised if this code does not
bf220695 1969 initially work for you.
c587e4a6 1970
4cd9d6f7
RP
1971config ATAGS_PROC
1972 bool "Export atags in procfs"
bd51e2f5 1973 depends on ATAGS && KEXEC
b98d7291 1974 default y
4cd9d6f7
RP
1975 help
1976 Should the atags used to boot the kernel be exported in an "atags"
1977 file in procfs. Useful with kexec.
1978
cb5d39b3
MW
1979config CRASH_DUMP
1980 bool "Build kdump crash kernel (EXPERIMENTAL)"
cb5d39b3
MW
1981 help
1982 Generate crash dump after being started by kexec. This should
1983 be normally only set in special crash dump kernels which are
1984 loaded in the main kernel with kexec-tools into a specially
1985 reserved region and then later executed after a crash by
1986 kdump/kexec. The crash dump kernel must be compiled to a
1987 memory address not used by the main kernel
1988
1989 For more details see Documentation/kdump/kdump.txt
1990
e69edc79
EM
1991config AUTO_ZRELADDR
1992 bool "Auto calculation of the decompressed kernel image address"
e69edc79
EM
1993 help
1994 ZRELADDR is the physical address where the decompressed kernel
1995 image will be placed. If AUTO_ZRELADDR is selected, the address
1996 will be determined at run-time by masking the current IP with
1997 0xf8000000. This assumes the zImage being placed in the first 128MB
1998 from start of memory.
1999
81a0bc39
RF
2000config EFI_STUB
2001 bool
2002
2003config EFI
2004 bool "UEFI runtime support"
2005 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2006 select UCS2_STRING
2007 select EFI_PARAMS_FROM_FDT
2008 select EFI_STUB
2009 select EFI_ARMSTUB
2010 select EFI_RUNTIME_WRAPPERS
2011 ---help---
2012 This option provides support for runtime services provided
2013 by UEFI firmware (such as non-volatile variables, realtime
2014 clock, and platform reset). A UEFI stub is also provided to
2015 allow the kernel to be booted as an EFI application. This
2016 is only useful for kernels that may run on systems that have
2017 UEFI firmware.
2018
1da177e4
LT
2019endmenu
2020
ac9d7efc 2021menu "CPU Power Management"
1da177e4 2022
1da177e4 2023source "drivers/cpufreq/Kconfig"
1da177e4 2024
ac9d7efc
RK
2025source "drivers/cpuidle/Kconfig"
2026
2027endmenu
2028
1da177e4
LT
2029menu "Floating point emulation"
2030
2031comment "At least one emulation must be selected"
2032
2033config FPE_NWFPE
2034 bool "NWFPE math emulation"
593c252a 2035 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1da177e4
LT
2036 ---help---
2037 Say Y to include the NWFPE floating point emulator in the kernel.
2038 This is necessary to run most binaries. Linux does not currently
2039 support floating point hardware so you need to say Y here even if
2040 your machine has an FPA or floating point co-processor podule.
2041
2042 You may say N here if you are going to load the Acorn FPEmulator
2043 early in the bootup.
2044
2045config FPE_NWFPE_XP
2046 bool "Support extended precision"
bedf142b 2047 depends on FPE_NWFPE
1da177e4
LT
2048 help
2049 Say Y to include 80-bit support in the kernel floating-point
2050 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2051 Note that gcc does not generate 80-bit operations by default,
2052 so in most cases this option only enlarges the size of the
2053 floating point emulator without any good reason.
2054
2055 You almost surely want to say N here.
2056
2057config FPE_FASTFPE
2058 bool "FastFPE math emulation (EXPERIMENTAL)"
d6f94fa0 2059 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1da177e4
LT
2060 ---help---
2061 Say Y here to include the FAST floating point emulator in the kernel.
2062 This is an experimental much faster emulator which now also has full
2063 precision for the mantissa. It does not support any exceptions.
2064 It is very simple, and approximately 3-6 times faster than NWFPE.
2065
2066 It should be sufficient for most programs. It may be not suitable
2067 for scientific calculations, but you have to check this for yourself.
2068 If you do not feel you need a faster FP emulation you should better
2069 choose NWFPE.
2070
2071config VFP
2072 bool "VFP-format floating point maths"
e399b1a4 2073 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1da177e4
LT
2074 help
2075 Say Y to include VFP support code in the kernel. This is needed
2076 if your hardware includes a VFP unit.
2077
2078 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2079 release notes and additional status information.
2080
2081 Say N if your target does not have VFP hardware.
2082
25ebee02
CM
2083config VFPv3
2084 bool
2085 depends on VFP
2086 default y if CPU_V7
2087
b5872db4
CM
2088config NEON
2089 bool "Advanced SIMD (NEON) Extension support"
2090 depends on VFPv3 && CPU_V7
2091 help
2092 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2093 Extension.
2094
73c132c1
AB
2095config KERNEL_MODE_NEON
2096 bool "Support for NEON in kernel mode"
c4a30c3b 2097 depends on NEON && AEABI
73c132c1
AB
2098 help
2099 Say Y to include support for NEON in kernel mode.
2100
1da177e4
LT
2101endmenu
2102
2103menu "Userspace binary formats"
2104
2105source "fs/Kconfig.binfmt"
2106
1da177e4
LT
2107endmenu
2108
2109menu "Power management options"
2110
eceab4ac 2111source "kernel/power/Kconfig"
1da177e4 2112
f4cb5700 2113config ARCH_SUSPEND_POSSIBLE
19a0519d 2114 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
f0d75153 2115 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
f4cb5700
JB
2116 def_bool y
2117
15e0d9e3
AB
2118config ARM_CPU_SUSPEND
2119 def_bool PM_SLEEP
2120
603fb42a
SC
2121config ARCH_HIBERNATION_POSSIBLE
2122 bool
2123 depends on MMU
2124 default y if ARCH_SUSPEND_POSSIBLE
2125
1da177e4
LT
2126endmenu
2127
d5950b43
SR
2128source "net/Kconfig"
2129
ac25150f 2130source "drivers/Kconfig"
1da177e4 2131
916f743d
KG
2132source "drivers/firmware/Kconfig"
2133
1da177e4
LT
2134source "fs/Kconfig"
2135
1da177e4
LT
2136source "arch/arm/Kconfig.debug"
2137
2138source "security/Kconfig"
2139
2140source "crypto/Kconfig"
652ccae5
AB
2141if CRYPTO
2142source "arch/arm/crypto/Kconfig"
2143endif
1da177e4
LT
2144
2145source "lib/Kconfig"
749cf76c
CD
2146
2147source "arch/arm/kvm/Kconfig"
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