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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/config.h> | |
11 | #include <linux/linkage.h> | |
12 | ||
13 | /* | |
14 | * Debugging stuff | |
15 | * | |
16 | * Note that these macros must not contain any code which is not | |
17 | * 100% relocatable. Any attempt to do so will result in a crash. | |
18 | * Please select one of the following when turning on debugging. | |
19 | */ | |
20 | #ifdef DEBUG | |
5cd0c344 RK |
21 | |
22 | #include <asm/arch/debug-macro.S> | |
23 | ||
24 | #if defined(CONFIG_DEBUG_ICEDCC) | |
1da177e4 LT |
25 | .macro loadsp, rb |
26 | .endm | |
5cd0c344 RK |
27 | .macro writeb, ch, rb |
28 | mcr p14, 0, \ch, c0, c1, 0 | |
1da177e4 | 29 | .endm |
5cd0c344 RK |
30 | #else |
31 | .macro writeb, ch, rb | |
32 | senduart \ch, \rb | |
1da177e4 | 33 | .endm |
5cd0c344 RK |
34 | |
35 | #if defined(CONFIG_FOOTBRIDGE) || \ | |
36 | defined(CONFIG_ARCH_RPC) || \ | |
37 | defined(CONFIG_ARCH_INTEGRATOR) || \ | |
38 | defined(CONFIG_ARCH_PXA) || \ | |
39 | defined(CONFIG_ARCH_IXP4XX) || \ | |
40 | defined(CONFIG_ARCH_IXP2000) || \ | |
41 | defined(CONFIG_ARCH_LH7A40X) || \ | |
0b83f140 JR |
42 | defined(CONFIG_ARCH_OMAP) || \ |
43 | defined(CONFIG_MACH_MP1000) | |
1da177e4 | 44 | .macro loadsp, rb |
5cd0c344 | 45 | addruart \rb |
1da177e4 LT |
46 | .endm |
47 | #elif defined(CONFIG_ARCH_SA1100) | |
48 | .macro loadsp, rb | |
49 | mov \rb, #0x80000000 @ physical base address | |
50 | # if defined(CONFIG_DEBUG_LL_SER3) | |
51 | add \rb, \rb, #0x00050000 @ Ser3 | |
52 | # else | |
53 | add \rb, \rb, #0x00010000 @ Ser1 | |
54 | # endif | |
55 | .endm | |
1da177e4 LT |
56 | #elif defined(CONFIG_ARCH_IOP331) |
57 | .macro loadsp, rb | |
58 | mov \rb, #0xff000000 | |
59 | orr \rb, \rb, #0x00ff0000 | |
60 | orr \rb, \rb, #0x0000f700 @ location of the UART | |
61 | .endm | |
1da177e4 | 62 | #elif defined(CONFIG_ARCH_S3C2410) |
5cd0c344 | 63 | .macro loadsp, rb |
1da177e4 LT |
64 | mov \rb, #0x50000000 |
65 | add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT | |
66 | .endm | |
1da177e4 LT |
67 | #else |
68 | #error no serial architecture defined | |
69 | #endif | |
5cd0c344 | 70 | #endif |
1da177e4 LT |
71 | #endif |
72 | ||
73 | .macro kputc,val | |
74 | mov r0, \val | |
75 | bl putc | |
76 | .endm | |
77 | ||
78 | .macro kphex,val,len | |
79 | mov r0, \val | |
80 | mov r1, #\len | |
81 | bl phex | |
82 | .endm | |
83 | ||
84 | .macro debug_reloc_start | |
85 | #ifdef DEBUG | |
86 | kputc #'\n' | |
87 | kphex r6, 8 /* processor id */ | |
88 | kputc #':' | |
89 | kphex r7, 8 /* architecture id */ | |
90 | kputc #':' | |
91 | mrc p15, 0, r0, c1, c0 | |
92 | kphex r0, 8 /* control reg */ | |
93 | kputc #'\n' | |
94 | kphex r5, 8 /* decompressed kernel start */ | |
95 | kputc #'-' | |
96 | kphex r8, 8 /* decompressed kernel end */ | |
97 | kputc #'>' | |
98 | kphex r4, 8 /* kernel execution address */ | |
99 | kputc #'\n' | |
100 | #endif | |
101 | .endm | |
102 | ||
103 | .macro debug_reloc_end | |
104 | #ifdef DEBUG | |
105 | kphex r5, 8 /* end of kernel */ | |
106 | kputc #'\n' | |
107 | mov r0, r4 | |
108 | bl memdump /* dump 256 bytes at start of kernel */ | |
109 | #endif | |
110 | .endm | |
111 | ||
112 | .section ".start", #alloc, #execinstr | |
113 | /* | |
114 | * sort out different calling conventions | |
115 | */ | |
116 | .align | |
117 | start: | |
118 | .type start,#function | |
119 | .rept 8 | |
120 | mov r0, r0 | |
121 | .endr | |
122 | ||
123 | b 1f | |
124 | .word 0x016f2818 @ Magic numbers to help the loader | |
125 | .word start @ absolute load/run zImage address | |
126 | .word _edata @ zImage end address | |
127 | 1: mov r7, r1 @ save architecture ID | |
128 | mov r8, #0 @ save r0 | |
129 | ||
130 | #ifndef __ARM_ARCH_2__ | |
131 | /* | |
132 | * Booting from Angel - need to enter SVC mode and disable | |
133 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
134 | * We only do this if we were in user mode on entry. | |
135 | */ | |
136 | mrs r2, cpsr @ get current mode | |
137 | tst r2, #3 @ not user? | |
138 | bne not_angel | |
139 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
140 | swi 0x123456 @ angel_SWI_ARM | |
141 | not_angel: | |
142 | mrs r2, cpsr @ turn off interrupts to | |
143 | orr r2, r2, #0xc0 @ prevent angel from running | |
144 | msr cpsr_c, r2 | |
145 | #else | |
146 | teqp pc, #0x0c000003 @ turn off interrupts | |
147 | #endif | |
148 | ||
149 | /* | |
150 | * Note that some cache flushing and other stuff may | |
151 | * be needed here - is there an Angel SWI call for this? | |
152 | */ | |
153 | ||
154 | /* | |
155 | * some architecture specific code can be inserted | |
156 | * by the linker here, but it should preserve r7 and r8. | |
157 | */ | |
158 | ||
159 | .text | |
160 | adr r0, LC0 | |
161 | ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} | |
162 | subs r0, r0, r1 @ calculate the delta offset | |
163 | ||
164 | @ if delta is zero, we are | |
165 | beq not_relocated @ running at the address we | |
166 | @ were linked at. | |
167 | ||
168 | /* | |
169 | * We're running at a different address. We need to fix | |
170 | * up various pointers: | |
171 | * r5 - zImage base address | |
172 | * r6 - GOT start | |
173 | * ip - GOT end | |
174 | */ | |
175 | add r5, r5, r0 | |
176 | add r6, r6, r0 | |
177 | add ip, ip, r0 | |
178 | ||
179 | #ifndef CONFIG_ZBOOT_ROM | |
180 | /* | |
181 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
182 | * we need to fix up pointers into the BSS region. | |
183 | * r2 - BSS start | |
184 | * r3 - BSS end | |
185 | * sp - stack pointer | |
186 | */ | |
187 | add r2, r2, r0 | |
188 | add r3, r3, r0 | |
189 | add sp, sp, r0 | |
190 | ||
191 | /* | |
192 | * Relocate all entries in the GOT table. | |
193 | */ | |
194 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
195 | add r1, r1, r0 @ table. This fixes up the | |
196 | str r1, [r6], #4 @ C references. | |
197 | cmp r6, ip | |
198 | blo 1b | |
199 | #else | |
200 | ||
201 | /* | |
202 | * Relocate entries in the GOT table. We only relocate | |
203 | * the entries that are outside the (relocated) BSS region. | |
204 | */ | |
205 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
206 | cmp r1, r2 @ entry < bss_start || | |
207 | cmphs r3, r1 @ _end < entry | |
208 | addlo r1, r1, r0 @ table. This fixes up the | |
209 | str r1, [r6], #4 @ C references. | |
210 | cmp r6, ip | |
211 | blo 1b | |
212 | #endif | |
213 | ||
214 | not_relocated: mov r0, #0 | |
215 | 1: str r0, [r2], #4 @ clear bss | |
216 | str r0, [r2], #4 | |
217 | str r0, [r2], #4 | |
218 | str r0, [r2], #4 | |
219 | cmp r2, r3 | |
220 | blo 1b | |
221 | ||
222 | /* | |
223 | * The C runtime environment should now be setup | |
224 | * sufficiently. Turn the cache on, set up some | |
225 | * pointers, and start decompressing. | |
226 | */ | |
227 | bl cache_on | |
228 | ||
229 | mov r1, sp @ malloc space above stack | |
230 | add r2, sp, #0x10000 @ 64k max | |
231 | ||
232 | /* | |
233 | * Check to see if we will overwrite ourselves. | |
234 | * r4 = final kernel address | |
235 | * r5 = start of this image | |
236 | * r2 = end of malloc space (and therefore this image) | |
237 | * We basically want: | |
238 | * r4 >= r2 -> OK | |
239 | * r4 + image length <= r5 -> OK | |
240 | */ | |
241 | cmp r4, r2 | |
242 | bhs wont_overwrite | |
243 | add r0, r4, #4096*1024 @ 4MB largest kernel size | |
244 | cmp r0, r5 | |
245 | bls wont_overwrite | |
246 | ||
247 | mov r5, r2 @ decompress after malloc space | |
248 | mov r0, r5 | |
249 | mov r3, r7 | |
250 | bl decompress_kernel | |
251 | ||
252 | add r0, r0, #127 | |
253 | bic r0, r0, #127 @ align the kernel length | |
254 | /* | |
255 | * r0 = decompressed kernel length | |
256 | * r1-r3 = unused | |
257 | * r4 = kernel execution address | |
258 | * r5 = decompressed kernel start | |
259 | * r6 = processor ID | |
260 | * r7 = architecture ID | |
261 | * r8-r14 = unused | |
262 | */ | |
263 | add r1, r5, r0 @ end of decompressed kernel | |
264 | adr r2, reloc_start | |
265 | ldr r3, LC1 | |
266 | add r3, r2, r3 | |
267 | 1: ldmia r2!, {r8 - r13} @ copy relocation code | |
268 | stmia r1!, {r8 - r13} | |
269 | ldmia r2!, {r8 - r13} | |
270 | stmia r1!, {r8 - r13} | |
271 | cmp r2, r3 | |
272 | blo 1b | |
273 | ||
274 | bl cache_clean_flush | |
275 | add pc, r5, r0 @ call relocation code | |
276 | ||
277 | /* | |
278 | * We're not in danger of overwriting ourselves. Do this the simple way. | |
279 | * | |
280 | * r4 = kernel execution address | |
281 | * r7 = architecture ID | |
282 | */ | |
283 | wont_overwrite: mov r0, r4 | |
284 | mov r3, r7 | |
285 | bl decompress_kernel | |
286 | b call_kernel | |
287 | ||
288 | .type LC0, #object | |
289 | LC0: .word LC0 @ r1 | |
290 | .word __bss_start @ r2 | |
291 | .word _end @ r3 | |
292 | .word zreladdr @ r4 | |
293 | .word _start @ r5 | |
294 | .word _got_start @ r6 | |
295 | .word _got_end @ ip | |
296 | .word user_stack+4096 @ sp | |
297 | LC1: .word reloc_end - reloc_start | |
298 | .size LC0, . - LC0 | |
299 | ||
300 | #ifdef CONFIG_ARCH_RPC | |
301 | .globl params | |
302 | params: ldr r0, =params_phys | |
303 | mov pc, lr | |
304 | .ltorg | |
305 | .align | |
306 | #endif | |
307 | ||
308 | /* | |
309 | * Turn on the cache. We need to setup some page tables so that we | |
310 | * can have both the I and D caches on. | |
311 | * | |
312 | * We place the page tables 16k down from the kernel execution address, | |
313 | * and we hope that nothing else is using it. If we're using it, we | |
314 | * will go pop! | |
315 | * | |
316 | * On entry, | |
317 | * r4 = kernel execution address | |
318 | * r6 = processor ID | |
319 | * r7 = architecture number | |
320 | * r8 = run-time address of "start" | |
321 | * On exit, | |
322 | * r1, r2, r3, r8, r9, r12 corrupted | |
323 | * This routine must preserve: | |
324 | * r4, r5, r6, r7 | |
325 | */ | |
326 | .align 5 | |
327 | cache_on: mov r3, #8 @ cache_on function | |
328 | b call_cache_fn | |
329 | ||
330 | __setup_mmu: sub r3, r4, #16384 @ Page directory size | |
331 | bic r3, r3, #0xff @ Align the pointer | |
332 | bic r3, r3, #0x3f00 | |
333 | /* | |
334 | * Initialise the page tables, turning on the cacheable and bufferable | |
335 | * bits for the RAM area only. | |
336 | */ | |
337 | mov r0, r3 | |
338 | mov r8, r0, lsr #18 | |
339 | mov r8, r8, lsl #18 @ start of RAM | |
340 | add r9, r8, #0x10000000 @ a reasonable RAM size | |
341 | mov r1, #0x12 | |
342 | orr r1, r1, #3 << 10 | |
343 | add r2, r3, #16384 | |
344 | 1: cmp r1, r8 @ if virt > start of RAM | |
345 | orrhs r1, r1, #0x0c @ set cacheable, bufferable | |
346 | cmp r1, r9 @ if virt > end of RAM | |
347 | bichs r1, r1, #0x0c @ clear cacheable, bufferable | |
348 | str r1, [r0], #4 @ 1:1 mapping | |
349 | add r1, r1, #1048576 | |
350 | teq r0, r2 | |
351 | bne 1b | |
352 | /* | |
353 | * If ever we are running from Flash, then we surely want the cache | |
354 | * to be enabled also for our execution instance... We map 2MB of it | |
355 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
356 | * If the execution is in RAM then we would only be duplicating the above. | |
357 | */ | |
358 | mov r1, #0x1e | |
359 | orr r1, r1, #3 << 10 | |
360 | mov r2, pc, lsr #20 | |
361 | orr r1, r1, r2, lsl #20 | |
362 | add r0, r3, r2, lsl #2 | |
363 | str r1, [r0], #4 | |
364 | add r1, r1, #1048576 | |
365 | str r1, [r0] | |
366 | mov pc, lr | |
367 | ||
368 | __armv4_cache_on: | |
369 | mov r12, lr | |
370 | bl __setup_mmu | |
371 | mov r0, #0 | |
372 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
373 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
374 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
375 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
376 | orr r0, r0, #0x0030 | |
377 | bl __common_cache_on | |
378 | mov r0, #0 | |
379 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
380 | mov pc, r12 | |
381 | ||
382 | __arm6_cache_on: | |
383 | mov r12, lr | |
384 | bl __setup_mmu | |
385 | mov r0, #0 | |
386 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
387 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
388 | mov r0, #0x30 | |
389 | bl __common_cache_on | |
390 | mov r0, #0 | |
391 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
392 | mov pc, r12 | |
393 | ||
394 | __common_cache_on: | |
395 | #ifndef DEBUG | |
396 | orr r0, r0, #0x000d @ Write buffer, mmu | |
397 | #endif | |
398 | mov r1, #-1 | |
399 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
400 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
401 | mcr p15, 0, r0, c1, c0, 0 @ load control register | |
402 | mov pc, lr | |
403 | ||
404 | /* | |
405 | * All code following this line is relocatable. It is relocated by | |
406 | * the above code to the end of the decompressed kernel image and | |
407 | * executed there. During this time, we have no stacks. | |
408 | * | |
409 | * r0 = decompressed kernel length | |
410 | * r1-r3 = unused | |
411 | * r4 = kernel execution address | |
412 | * r5 = decompressed kernel start | |
413 | * r6 = processor ID | |
414 | * r7 = architecture ID | |
415 | * r8-r14 = unused | |
416 | */ | |
417 | .align 5 | |
418 | reloc_start: add r8, r5, r0 | |
419 | debug_reloc_start | |
420 | mov r1, r4 | |
421 | 1: | |
422 | .rept 4 | |
423 | ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel | |
424 | stmia r1!, {r0, r2, r3, r9 - r13} | |
425 | .endr | |
426 | ||
427 | cmp r5, r8 | |
428 | blo 1b | |
429 | debug_reloc_end | |
430 | ||
431 | call_kernel: bl cache_clean_flush | |
432 | bl cache_off | |
433 | mov r0, #0 | |
434 | mov r1, r7 @ restore architecture number | |
435 | mov pc, r4 @ call kernel | |
436 | ||
437 | /* | |
438 | * Here follow the relocatable cache support functions for the | |
439 | * various processors. This is a generic hook for locating an | |
440 | * entry and jumping to an instruction at the specified offset | |
441 | * from the start of the block. Please note this is all position | |
442 | * independent code. | |
443 | * | |
444 | * r1 = corrupted | |
445 | * r2 = corrupted | |
446 | * r3 = block offset | |
447 | * r6 = corrupted | |
448 | * r12 = corrupted | |
449 | */ | |
450 | ||
451 | call_cache_fn: adr r12, proc_types | |
452 | mrc p15, 0, r6, c0, c0 @ get processor ID | |
453 | 1: ldr r1, [r12, #0] @ get value | |
454 | ldr r2, [r12, #4] @ get mask | |
455 | eor r1, r1, r6 @ (real ^ match) | |
456 | tst r1, r2 @ & mask | |
457 | addeq pc, r12, r3 @ call cache function | |
458 | add r12, r12, #4*5 | |
459 | b 1b | |
460 | ||
461 | /* | |
462 | * Table for cache operations. This is basically: | |
463 | * - CPU ID match | |
464 | * - CPU ID mask | |
465 | * - 'cache on' method instruction | |
466 | * - 'cache off' method instruction | |
467 | * - 'cache flush' method instruction | |
468 | * | |
469 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
470 | * | |
471 | * Writethrough caches generally only need 'on' and 'off' | |
472 | * methods. Writeback caches _must_ have the flush method | |
473 | * defined. | |
474 | */ | |
475 | .type proc_types,#object | |
476 | proc_types: | |
477 | .word 0x41560600 @ ARM6/610 | |
478 | .word 0xffffffe0 | |
479 | b __arm6_cache_off @ works, but slow | |
480 | b __arm6_cache_off | |
481 | mov pc, lr | |
482 | @ b __arm6_cache_on @ untested | |
483 | @ b __arm6_cache_off | |
484 | @ b __armv3_cache_flush | |
485 | ||
486 | .word 0x00000000 @ old ARM ID | |
487 | .word 0x0000f000 | |
488 | mov pc, lr | |
489 | mov pc, lr | |
490 | mov pc, lr | |
491 | ||
492 | .word 0x41007000 @ ARM7/710 | |
493 | .word 0xfff8fe00 | |
494 | b __arm7_cache_off | |
495 | b __arm7_cache_off | |
496 | mov pc, lr | |
497 | ||
498 | .word 0x41807200 @ ARM720T (writethrough) | |
499 | .word 0xffffff00 | |
500 | b __armv4_cache_on | |
501 | b __armv4_cache_off | |
502 | mov pc, lr | |
503 | ||
504 | .word 0x00007000 @ ARM7 IDs | |
505 | .word 0x0000f000 | |
506 | mov pc, lr | |
507 | mov pc, lr | |
508 | mov pc, lr | |
509 | ||
510 | @ Everything from here on will be the new ID system. | |
511 | ||
512 | .word 0x4401a100 @ sa110 / sa1100 | |
513 | .word 0xffffffe0 | |
514 | b __armv4_cache_on | |
515 | b __armv4_cache_off | |
516 | b __armv4_cache_flush | |
517 | ||
518 | .word 0x6901b110 @ sa1110 | |
519 | .word 0xfffffff0 | |
520 | b __armv4_cache_on | |
521 | b __armv4_cache_off | |
522 | b __armv4_cache_flush | |
523 | ||
524 | @ These match on the architecture ID | |
525 | ||
526 | .word 0x00020000 @ ARMv4T | |
527 | .word 0x000f0000 | |
528 | b __armv4_cache_on | |
529 | b __armv4_cache_off | |
530 | b __armv4_cache_flush | |
531 | ||
532 | .word 0x00050000 @ ARMv5TE | |
533 | .word 0x000f0000 | |
534 | b __armv4_cache_on | |
535 | b __armv4_cache_off | |
536 | b __armv4_cache_flush | |
537 | ||
538 | .word 0x00060000 @ ARMv5TEJ | |
539 | .word 0x000f0000 | |
540 | b __armv4_cache_on | |
541 | b __armv4_cache_off | |
542 | b __armv4_cache_flush | |
543 | ||
544 | .word 0x00070000 @ ARMv6 | |
545 | .word 0x000f0000 | |
546 | b __armv4_cache_on | |
547 | b __armv4_cache_off | |
548 | b __armv6_cache_flush | |
549 | ||
550 | .word 0 @ unrecognised type | |
551 | .word 0 | |
552 | mov pc, lr | |
553 | mov pc, lr | |
554 | mov pc, lr | |
555 | ||
556 | .size proc_types, . - proc_types | |
557 | ||
558 | /* | |
559 | * Turn off the Cache and MMU. ARMv3 does not support | |
560 | * reading the control register, but ARMv4 does. | |
561 | * | |
562 | * On entry, r6 = processor ID | |
563 | * On exit, r0, r1, r2, r3, r12 corrupted | |
564 | * This routine must preserve: r4, r6, r7 | |
565 | */ | |
566 | .align 5 | |
567 | cache_off: mov r3, #12 @ cache_off function | |
568 | b call_cache_fn | |
569 | ||
570 | __armv4_cache_off: | |
571 | mrc p15, 0, r0, c1, c0 | |
572 | bic r0, r0, #0x000d | |
573 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
574 | mov r0, #0 | |
575 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
576 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
577 | mov pc, lr | |
578 | ||
579 | __arm6_cache_off: | |
580 | mov r0, #0x00000030 @ ARM6 control reg. | |
581 | b __armv3_cache_off | |
582 | ||
583 | __arm7_cache_off: | |
584 | mov r0, #0x00000070 @ ARM7 control reg. | |
585 | b __armv3_cache_off | |
586 | ||
587 | __armv3_cache_off: | |
588 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off | |
589 | mov r0, #0 | |
590 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
591 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
592 | mov pc, lr | |
593 | ||
594 | /* | |
595 | * Clean and flush the cache to maintain consistency. | |
596 | * | |
597 | * On entry, | |
598 | * r6 = processor ID | |
599 | * On exit, | |
600 | * r1, r2, r3, r11, r12 corrupted | |
601 | * This routine must preserve: | |
602 | * r0, r4, r5, r6, r7 | |
603 | */ | |
604 | .align 5 | |
605 | cache_clean_flush: | |
606 | mov r3, #16 | |
607 | b call_cache_fn | |
608 | ||
609 | __armv6_cache_flush: | |
610 | mov r1, #0 | |
611 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
612 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
613 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
614 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
615 | mov pc, lr | |
616 | ||
617 | __armv4_cache_flush: | |
618 | mov r2, #64*1024 @ default: 32K dcache size (*2) | |
619 | mov r11, #32 @ default: 32 byte line size | |
620 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
621 | teq r3, r6 @ cache ID register present? | |
622 | beq no_cache_id | |
623 | mov r1, r3, lsr #18 | |
624 | and r1, r1, #7 | |
625 | mov r2, #1024 | |
626 | mov r2, r2, lsl r1 @ base dcache size *2 | |
627 | tst r3, #1 << 14 @ test M bit | |
628 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
629 | mov r3, r3, lsr #12 | |
630 | and r3, r3, #3 | |
631 | mov r11, #8 | |
632 | mov r11, r11, lsl r3 @ cache line size in bytes | |
633 | no_cache_id: | |
634 | bic r1, pc, #63 @ align to longest cache line | |
635 | add r2, r1, r2 | |
636 | 1: ldr r3, [r1], r11 @ s/w flush D cache | |
637 | teq r1, r2 | |
638 | bne 1b | |
639 | ||
640 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
641 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
642 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
643 | mov pc, lr | |
644 | ||
645 | __armv3_cache_flush: | |
646 | mov r1, #0 | |
647 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
648 | mov pc, lr | |
649 | ||
650 | /* | |
651 | * Various debugging routines for printing hex characters and | |
652 | * memory, which again must be relocatable. | |
653 | */ | |
654 | #ifdef DEBUG | |
655 | .type phexbuf,#object | |
656 | phexbuf: .space 12 | |
657 | .size phexbuf, . - phexbuf | |
658 | ||
659 | phex: adr r3, phexbuf | |
660 | mov r2, #0 | |
661 | strb r2, [r3, r1] | |
662 | 1: subs r1, r1, #1 | |
663 | movmi r0, r3 | |
664 | bmi puts | |
665 | and r2, r0, #15 | |
666 | mov r0, r0, lsr #4 | |
667 | cmp r2, #10 | |
668 | addge r2, r2, #7 | |
669 | add r2, r2, #'0' | |
670 | strb r2, [r3, r1] | |
671 | b 1b | |
672 | ||
673 | puts: loadsp r3 | |
674 | 1: ldrb r2, [r0], #1 | |
675 | teq r2, #0 | |
676 | moveq pc, lr | |
5cd0c344 | 677 | 2: writeb r2, r3 |
1da177e4 LT |
678 | mov r1, #0x00020000 |
679 | 3: subs r1, r1, #1 | |
680 | bne 3b | |
681 | teq r2, #'\n' | |
682 | moveq r2, #'\r' | |
683 | beq 2b | |
684 | teq r0, #0 | |
685 | bne 1b | |
686 | mov pc, lr | |
687 | putc: | |
688 | mov r2, r0 | |
689 | mov r0, #0 | |
690 | loadsp r3 | |
691 | b 2b | |
692 | ||
693 | memdump: mov r12, r0 | |
694 | mov r10, lr | |
695 | mov r11, #0 | |
696 | 2: mov r0, r11, lsl #2 | |
697 | add r0, r0, r12 | |
698 | mov r1, #8 | |
699 | bl phex | |
700 | mov r0, #':' | |
701 | bl putc | |
702 | 1: mov r0, #' ' | |
703 | bl putc | |
704 | ldr r0, [r12, r11, lsl #2] | |
705 | mov r1, #8 | |
706 | bl phex | |
707 | and r0, r11, #7 | |
708 | teq r0, #3 | |
709 | moveq r0, #' ' | |
710 | bleq putc | |
711 | and r0, r11, #7 | |
712 | add r11, r11, #1 | |
713 | teq r0, #7 | |
714 | bne 1b | |
715 | mov r0, #'\n' | |
716 | bl putc | |
717 | cmp r11, #64 | |
718 | blt 2b | |
719 | mov pc, r10 | |
720 | #endif | |
721 | ||
722 | reloc_end: | |
723 | ||
724 | .align | |
725 | .section ".stack", "w" | |
726 | user_stack: .space 4096 |