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11d938d4 RL |
1 | /* |
2 | * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/ | |
3 | * Author: Rostislav Lisovy <lisovy@jablotron.cz> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | #include "am33xx.dtsi" | |
10 | ||
11 | / { | |
12 | model = "Grinn AM335x ChiliSOM"; | |
13 | compatible = "grinn,am335x-chilisom", "ti,am33xx"; | |
14 | ||
15 | cpus { | |
16 | cpu@0 { | |
17 | cpu0-supply = <&dcdc2_reg>; | |
18 | }; | |
19 | }; | |
20 | ||
21 | memory { | |
22 | device_type = "memory"; | |
23 | reg = <0x80000000 0x20000000>; /* 512 MB */ | |
24 | }; | |
25 | }; | |
26 | ||
27 | &am33xx_pinmux { | |
28 | pinctrl-names = "default"; | |
29 | ||
30 | i2c0_pins: pinmux_i2c0_pins { | |
31 | pinctrl-single,pins = < | |
32 | 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | |
33 | 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | |
34 | >; | |
35 | }; | |
36 | ||
37 | uart0_pins: pinmux_uart0_pins { | |
38 | pinctrl-single,pins = < | |
39 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | |
40 | 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | |
41 | >; | |
42 | }; | |
43 | ||
44 | cpsw_default: cpsw_default { | |
45 | pinctrl-single,pins = < | |
46 | /* Slave 1 */ | |
47 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ | |
48 | 0x110 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ | |
49 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ | |
50 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ | |
51 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ | |
52 | 0x13c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ | |
53 | 0x140 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ | |
54 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ | |
55 | >; | |
56 | }; | |
57 | ||
58 | cpsw_sleep: cpsw_sleep { | |
59 | pinctrl-single,pins = < | |
60 | /* Slave 1 reset value */ | |
61 | 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
62 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
63 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
64 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
65 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
66 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
67 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
68 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
69 | 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
70 | >; | |
71 | }; | |
72 | ||
73 | davinci_mdio_default: davinci_mdio_default { | |
74 | pinctrl-single,pins = < | |
75 | /* mdio_data.mdio_data */ | |
76 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) | |
77 | /* mdio_clk.mdio_clk */ | |
78 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) | |
79 | >; | |
80 | }; | |
81 | ||
82 | davinci_mdio_sleep: davinci_mdio_sleep { | |
83 | pinctrl-single,pins = < | |
84 | /* MDIO reset value */ | |
85 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
86 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | |
87 | >; | |
88 | }; | |
89 | ||
90 | nandflash_pins: nandflash_pins { | |
91 | pinctrl-single,pins = < | |
92 | 0x00 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ | |
93 | 0x04 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | |
94 | 0x08 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | |
95 | 0x0c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | |
96 | 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | |
97 | 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | |
98 | 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | |
99 | 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | |
100 | ||
101 | 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | |
102 | 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | |
103 | 0x90 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | |
104 | 0x94 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | |
105 | 0x98 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | |
106 | 0x9c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ | |
107 | >; | |
108 | }; | |
109 | }; | |
110 | ||
111 | &uart0 { | |
112 | pinctrl-names = "default"; | |
113 | pinctrl-0 = <&uart0_pins>; | |
114 | ||
115 | status = "okay"; | |
116 | }; | |
117 | ||
118 | &i2c0 { | |
119 | pinctrl-names = "default"; | |
120 | pinctrl-0 = <&i2c0_pins>; | |
121 | ||
122 | status = "okay"; | |
123 | clock-frequency = <400000>; | |
124 | ||
125 | tps: tps@24 { | |
126 | reg = <0x24>; | |
127 | }; | |
128 | ||
129 | }; | |
130 | ||
131 | /include/ "tps65217.dtsi" | |
132 | ||
133 | &tps { | |
134 | regulators { | |
135 | dcdc1_reg: regulator@0 { | |
136 | regulator-name = "vdds_dpr"; | |
137 | regulator-always-on; | |
138 | }; | |
139 | ||
140 | dcdc2_reg: regulator@1 { | |
141 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ | |
142 | regulator-name = "vdd_mpu"; | |
143 | regulator-min-microvolt = <925000>; | |
144 | regulator-max-microvolt = <1325000>; | |
145 | regulator-boot-on; | |
146 | regulator-always-on; | |
147 | }; | |
148 | ||
149 | dcdc3_reg: regulator@2 { | |
150 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ | |
151 | regulator-name = "vdd_core"; | |
152 | regulator-min-microvolt = <925000>; | |
153 | regulator-max-microvolt = <1150000>; | |
154 | regulator-boot-on; | |
155 | regulator-always-on; | |
156 | }; | |
157 | ||
158 | ldo1_reg: regulator@3 { | |
159 | regulator-name = "vio,vrtc,vdds"; | |
160 | regulator-boot-on; | |
161 | regulator-always-on; | |
162 | }; | |
163 | ||
164 | ldo2_reg: regulator@4 { | |
165 | regulator-name = "vdd_3v3aux"; | |
166 | regulator-boot-on; | |
167 | regulator-always-on; | |
168 | }; | |
169 | ||
170 | ldo3_reg: regulator@5 { | |
171 | regulator-name = "vdd_1v8"; | |
172 | regulator-boot-on; | |
173 | regulator-always-on; | |
174 | }; | |
175 | ||
176 | ldo4_reg: regulator@6 { | |
177 | regulator-name = "vdd_3v3d"; | |
178 | regulator-boot-on; | |
179 | regulator-always-on; | |
180 | }; | |
181 | }; | |
182 | }; | |
183 | ||
184 | /* Ethernet MAC */ | |
185 | &mac { | |
186 | slaves = <1>; | |
187 | pinctrl-names = "default", "sleep"; | |
188 | pinctrl-0 = <&cpsw_default>; | |
189 | pinctrl-1 = <&cpsw_sleep>; | |
190 | status = "okay"; | |
191 | }; | |
192 | ||
193 | &davinci_mdio { | |
194 | pinctrl-names = "default", "sleep"; | |
195 | pinctrl-0 = <&davinci_mdio_default>; | |
196 | pinctrl-1 = <&davinci_mdio_sleep>; | |
197 | status = "okay"; | |
198 | }; | |
199 | ||
200 | /* NAND Flash */ | |
201 | &elm { | |
202 | status = "okay"; | |
203 | }; | |
204 | ||
205 | &gpmc { | |
206 | status = "okay"; | |
207 | pinctrl-names = "default"; | |
208 | pinctrl-0 = <&nandflash_pins>; | |
209 | ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ | |
210 | nand@0,0 { | |
211 | reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ | |
212 | ti,nand-ecc-opt = "bch8"; | |
213 | ti,elm-id = <&elm>; | |
214 | nand-bus-width = <8>; | |
215 | gpmc,device-width = <1>; | |
216 | gpmc,sync-clk-ps = <0>; | |
217 | gpmc,cs-on-ns = <0>; | |
218 | gpmc,cs-rd-off-ns = <44>; | |
219 | gpmc,cs-wr-off-ns = <44>; | |
220 | gpmc,adv-on-ns = <6>; | |
221 | gpmc,adv-rd-off-ns = <34>; | |
222 | gpmc,adv-wr-off-ns = <44>; | |
223 | gpmc,we-on-ns = <0>; | |
224 | gpmc,we-off-ns = <40>; | |
225 | gpmc,oe-on-ns = <0>; | |
226 | gpmc,oe-off-ns = <54>; | |
227 | gpmc,access-ns = <64>; | |
228 | gpmc,rd-cycle-ns = <82>; | |
229 | gpmc,wr-cycle-ns = <82>; | |
230 | gpmc,wait-on-read = "true"; | |
231 | gpmc,wait-on-write = "true"; | |
232 | gpmc,bus-turnaround-ns = <0>; | |
233 | gpmc,cycle2cycle-delay-ns = <0>; | |
234 | gpmc,clk-activation-ns = <0>; | |
235 | gpmc,wait-monitoring-ns = <0>; | |
236 | gpmc,wr-access-ns = <40>; | |
237 | gpmc,wr-data-mux-bus-ns = <0>; | |
238 | }; | |
239 | }; |